irq_service_dcn35.c

  1/*
  2 * Copyright 2021 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#include "dm_services.h"
 27#include "include/logger_interface.h"
 28#include "../dce110/irq_service_dce110.h"
 29
 30#include "dcn/dcn_3_5_0_offset.h"
 31#include "dcn/dcn_3_5_0_sh_mask.h"
 32
 33#include "irq_service_dcn35.h"
 34
 35#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
 36
 37static enum dc_irq_source to_dal_irq_source_dcn35(
 38		struct irq_service *irq_service,
 39		uint32_t src_id,
 40		uint32_t ext_id)
 41{
 42	switch (src_id) {
 43	case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
 44		return DC_IRQ_SOURCE_VBLANK1;
 45	case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
 46		return DC_IRQ_SOURCE_VBLANK2;
 47	case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
 48		return DC_IRQ_SOURCE_VBLANK3;
 49	case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
 50		return DC_IRQ_SOURCE_VBLANK4;
 51	case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
 52		return DC_IRQ_SOURCE_VBLANK5;
 53	case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
 54		return DC_IRQ_SOURCE_VBLANK6;
 55	case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
 56		return DC_IRQ_SOURCE_DC1_VLINE0;
 57	case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
 58		return DC_IRQ_SOURCE_DC2_VLINE0;
 59	case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
 60		return DC_IRQ_SOURCE_DC3_VLINE0;
 61	case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
 62		return DC_IRQ_SOURCE_DC4_VLINE0;
 63	case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
 64		return DC_IRQ_SOURCE_DC5_VLINE0;
 65	case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
 66		return DC_IRQ_SOURCE_DC6_VLINE0;
 67	case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
 68		return DC_IRQ_SOURCE_PFLIP1;
 69	case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
 70		return DC_IRQ_SOURCE_PFLIP2;
 71	case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
 72		return DC_IRQ_SOURCE_PFLIP3;
 73	case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
 74		return DC_IRQ_SOURCE_PFLIP4;
 75	case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
 76		return DC_IRQ_SOURCE_PFLIP5;
 77	case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
 78		return DC_IRQ_SOURCE_PFLIP6;
 79	case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 80		return DC_IRQ_SOURCE_VUPDATE1;
 81	case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 82		return DC_IRQ_SOURCE_VUPDATE2;
 83	case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 84		return DC_IRQ_SOURCE_VUPDATE3;
 85	case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 86		return DC_IRQ_SOURCE_VUPDATE4;
 87	case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 88		return DC_IRQ_SOURCE_VUPDATE5;
 89	case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 90		return DC_IRQ_SOURCE_VUPDATE6;
 91	case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
 92		return DC_IRQ_SOURCE_DMCUB_OUTBOX;
 93	case DCN_1_0__SRCID__DC_HPD1_INT:
 94		/* generic src_id for all HPD and HPDRX interrupts */
 95		switch (ext_id) {
 96		case DCN_1_0__CTXID__DC_HPD1_INT:
 97			return DC_IRQ_SOURCE_HPD1;
 98		case DCN_1_0__CTXID__DC_HPD2_INT:
 99			return DC_IRQ_SOURCE_HPD2;
100		case DCN_1_0__CTXID__DC_HPD3_INT:
101			return DC_IRQ_SOURCE_HPD3;
102		case DCN_1_0__CTXID__DC_HPD4_INT:
103			return DC_IRQ_SOURCE_HPD4;
104		case DCN_1_0__CTXID__DC_HPD5_INT:
105			return DC_IRQ_SOURCE_HPD5;
106		case DCN_1_0__CTXID__DC_HPD6_INT:
107			return DC_IRQ_SOURCE_HPD6;
108		case DCN_1_0__CTXID__DC_HPD1_RX_INT:
109			return DC_IRQ_SOURCE_HPD1RX;
110		case DCN_1_0__CTXID__DC_HPD2_RX_INT:
111			return DC_IRQ_SOURCE_HPD2RX;
112		case DCN_1_0__CTXID__DC_HPD3_RX_INT:
113			return DC_IRQ_SOURCE_HPD3RX;
114		case DCN_1_0__CTXID__DC_HPD4_RX_INT:
115			return DC_IRQ_SOURCE_HPD4RX;
116		case DCN_1_0__CTXID__DC_HPD5_RX_INT:
117			return DC_IRQ_SOURCE_HPD5RX;
118		case DCN_1_0__CTXID__DC_HPD6_RX_INT:
119			return DC_IRQ_SOURCE_HPD6RX;
120		default:
121			return DC_IRQ_SOURCE_INVALID;
122		}
123		break;
124
125	default:
126		return DC_IRQ_SOURCE_INVALID;
127	}
128}
129
130static struct irq_source_info_funcs hpd_irq_info_funcs = {
131	.set = NULL,
132	.ack = hpd0_ack
133};
134
135static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
136	.set = NULL,
137	.ack = NULL
138};
139
140static struct irq_source_info_funcs pflip_irq_info_funcs = {
141	.set = NULL,
142	.ack = NULL
143};
144
145static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
146	.set = NULL,
147	.ack = NULL
148};
149
150static struct irq_source_info_funcs vblank_irq_info_funcs = {
151	.set = NULL,
152	.ack = NULL
153};
154
155static struct irq_source_info_funcs outbox_irq_info_funcs = {
156	.set = NULL,
157	.ack = NULL
158};
159
160static struct irq_source_info_funcs vline0_irq_info_funcs = {
161	.set = NULL,
162	.ack = NULL
163};
164
165#undef BASE_INNER
166#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
167
168/* compile time expand base address. */
169#define BASE(seg) \
170	BASE_INNER(seg)
171
172#define SRI(reg_name, block, id)\
173	BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
174			reg ## block ## id ## _ ## reg_name
175
176#define SRI_DMUB(reg_name)\
177	BASE(reg ## reg_name ## _BASE_IDX) + \
178			reg ## reg_name
179
180#define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\
181	REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
182	REG_STRUCT[base + reg_num].enable_mask = \
183		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
184	REG_STRUCT[base + reg_num].enable_value[0] = \
185		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
186	REG_STRUCT[base + reg_num].enable_value[1] = \
187		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
188	REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
189	REG_STRUCT[base + reg_num].ack_mask = \
190		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
191	REG_STRUCT[base + reg_num].ack_value = \
192		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
193
194#define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\
195	REG_STRUCT[base].enable_reg = SRI_DMUB(reg1),\
196	REG_STRUCT[base].enable_mask = \
197		reg1 ## __ ## mask1 ## _MASK,\
198	REG_STRUCT[base].enable_value[0] = \
199		reg1 ## __ ## mask1 ## _MASK,\
200	REG_STRUCT[base].enable_value[1] = \
201		~reg1 ## __ ## mask1 ## _MASK, \
202	REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\
203	REG_STRUCT[base].ack_mask = \
204		reg2 ## __ ## mask2 ## _MASK,\
205	REG_STRUCT[base].ack_value = \
206		reg2 ## __ ## mask2 ## _MASK \
207
208#define hpd_int_entry(reg_num)\
209		IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1, HPD, reg_num,\
210			DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
211			DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
212		REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].funcs = &hpd_irq_info_funcs;\
213		REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\
214
215#define hpd_rx_int_entry(reg_num)\
216		IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1RX, HPD, reg_num,\
217			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
218			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
219		REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\
220		REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].funcs = &hpd_rx_irq_info_funcs;\
221
222#define pflip_int_entry(reg_num)\
223		IRQ_REG_ENTRY(DC_IRQ_SOURCE_PFLIP1, HUBPREQ, reg_num,\
224			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
225			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
226		REG_STRUCT[DC_IRQ_SOURCE_PFLIP1 + reg_num].funcs = &pflip_irq_info_funcs\
227
228/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
229 * of DCE's DC_IRQ_SOURCE_VUPDATEx.
230 */
231#define vupdate_no_lock_int_entry(reg_num)\
232		IRQ_REG_ENTRY(DC_IRQ_SOURCE_VUPDATE1, OTG, reg_num,\
233			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
234			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
235		REG_STRUCT[DC_IRQ_SOURCE_VUPDATE1 + reg_num].funcs = &vupdate_no_lock_irq_info_funcs\
236
237#define vblank_int_entry(reg_num)\
238		IRQ_REG_ENTRY(DC_IRQ_SOURCE_VBLANK1, OTG, reg_num,\
239			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
240			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
241		REG_STRUCT[DC_IRQ_SOURCE_VBLANK1 + reg_num].funcs = &vblank_irq_info_funcs\
242
243#define vline0_int_entry(reg_num)\
244		IRQ_REG_ENTRY(DC_IRQ_SOURCE_DC1_VLINE0, OTG, reg_num,\
245			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
246			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
247		REG_STRUCT[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num].funcs = &vline0_irq_info_funcs\
248
249#define dmub_outbox_int_entry()\
250		IRQ_REG_ENTRY_DMUB(DC_IRQ_SOURCE_DMCUB_OUTBOX, \
251			DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
252			DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
253		REG_STRUCT[DC_IRQ_SOURCE_DMCUB_OUTBOX].funcs = &outbox_irq_info_funcs
254
255#define dummy_irq_entry(irqno) \
256	REG_STRUCT[irqno].funcs = &dummy_irq_info_funcs\
257
258#define i2c_int_entry(reg_num) \
259	dummy_irq_entry(DC_IRQ_SOURCE_I2C_DDC ## reg_num)
260
261#define dp_sink_int_entry(reg_num) \
262	dummy_irq_entry(DC_IRQ_SOURCE_DPSINK ## reg_num)
263
264#define gpio_pad_int_entry(reg_num) \
265	dummy_irq_entry(DC_IRQ_SOURCE_GPIOPAD ## reg_num)
266
267#define dc_underflow_int_entry(reg_num) \
268	dummy_irq_entry(DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW)
269
270static struct irq_source_info_funcs dummy_irq_info_funcs = {
271	.set = dal_irq_service_dummy_set,
272	.ack = dal_irq_service_dummy_ack
273};
274
275#define dcn35_irq_init_part_1() \
276	dummy_irq_entry(DC_IRQ_SOURCE_INVALID); \
277	hpd_int_entry(0); \
278	hpd_int_entry(1); \
279	hpd_int_entry(2); \
280	hpd_int_entry(3); \
281	hpd_int_entry(4); \
282	hpd_rx_int_entry(0); \
283	hpd_rx_int_entry(1); \
284	hpd_rx_int_entry(2); \
285	hpd_rx_int_entry(3); \
286	hpd_rx_int_entry(4); \
287	i2c_int_entry(1); \
288	i2c_int_entry(2); \
289	i2c_int_entry(3); \
290	i2c_int_entry(4); \
291	i2c_int_entry(5); \
292	i2c_int_entry(6); \
293	dp_sink_int_entry(1); \
294	dp_sink_int_entry(2); \
295	dp_sink_int_entry(3); \
296	dp_sink_int_entry(4); \
297	dp_sink_int_entry(5); \
298	dp_sink_int_entry(6); \
299	dummy_irq_entry(DC_IRQ_SOURCE_TIMER); \
300	pflip_int_entry(0); \
301	pflip_int_entry(1); \
302	pflip_int_entry(2); \
303	pflip_int_entry(3); \
304	dummy_irq_entry(DC_IRQ_SOURCE_PFLIP5); \
305	dummy_irq_entry(DC_IRQ_SOURCE_PFLIP6); \
306	dummy_irq_entry(DC_IRQ_SOURCE_PFLIP_UNDERLAY0); \
307	gpio_pad_int_entry(0); \
308	gpio_pad_int_entry(1); \
309	gpio_pad_int_entry(2); \
310	gpio_pad_int_entry(3); \
311	gpio_pad_int_entry(4); \
312	gpio_pad_int_entry(5); \
313	gpio_pad_int_entry(6); \
314	gpio_pad_int_entry(7); \
315	gpio_pad_int_entry(8); \
316	gpio_pad_int_entry(9); \
317	gpio_pad_int_entry(10); \
318	gpio_pad_int_entry(11); \
319	gpio_pad_int_entry(12); \
320	gpio_pad_int_entry(13); \
321	gpio_pad_int_entry(14); \
322	gpio_pad_int_entry(15); \
323	gpio_pad_int_entry(16); \
324	gpio_pad_int_entry(17); \
325	gpio_pad_int_entry(18); \
326	gpio_pad_int_entry(19); \
327	gpio_pad_int_entry(20); \
328	gpio_pad_int_entry(21); \
329	gpio_pad_int_entry(22); \
330	gpio_pad_int_entry(23); \
331	gpio_pad_int_entry(24); \
332	gpio_pad_int_entry(25); \
333	gpio_pad_int_entry(26); \
334	gpio_pad_int_entry(27); \
335	gpio_pad_int_entry(28); \
336	gpio_pad_int_entry(29); \
337	gpio_pad_int_entry(30); \
338	dc_underflow_int_entry(1); \
339	dc_underflow_int_entry(2); \
340	dc_underflow_int_entry(3); \
341	dc_underflow_int_entry(4); \
342	dc_underflow_int_entry(5); \
343	dc_underflow_int_entry(6); \
344	dummy_irq_entry(DC_IRQ_SOURCE_DMCU_SCP); \
345	dummy_irq_entry(DC_IRQ_SOURCE_VBIOS_SW); \
346
347#define dcn35_irq_init_part_2() \
348	vupdate_no_lock_int_entry(0); \
349	vupdate_no_lock_int_entry(1); \
350	vupdate_no_lock_int_entry(2); \
351	vupdate_no_lock_int_entry(3); \
352	vblank_int_entry(0); \
353	vblank_int_entry(1); \
354	vblank_int_entry(2); \
355	vblank_int_entry(3); \
356	vline0_int_entry(0); \
357	vline0_int_entry(1); \
358	vline0_int_entry(2); \
359	vline0_int_entry(3); \
360	dummy_irq_entry(DC_IRQ_SOURCE_DC5_VLINE1); \
361	dummy_irq_entry(DC_IRQ_SOURCE_DC6_VLINE1); \
362	dmub_outbox_int_entry()
363
364#define dcn35_irq_init() \
365	dcn35_irq_init_part_1(); \
366	dcn35_irq_init_part_2(); \
367
368static struct irq_source_info irq_source_info_dcn35[DAL_IRQ_SOURCES_NUMBER] = {0};
369
370static struct irq_service_funcs irq_service_funcs_dcn35 = {
371		.to_dal_irq_source = to_dal_irq_source_dcn35
372};
373
374static void dcn35_irq_construct(
375	struct irq_service *irq_service,
376	struct irq_service_init_data *init_data)
377{
378	struct dc_context *ctx = init_data->ctx;
379
380#define REG_STRUCT irq_source_info_dcn35
381	dcn35_irq_init();
382
383	dal_irq_service_construct(irq_service, init_data);
384
385	irq_service->info = irq_source_info_dcn35;
386	irq_service->funcs = &irq_service_funcs_dcn35;
387}
388
389struct irq_service *dal_irq_service_dcn35_create(
390	struct irq_service_init_data *init_data)
391{
392	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
393						  GFP_KERNEL);
394
395	if (!irq_service)
396		return NULL;
397
398	dcn35_irq_construct(irq_service, init_data);
399	return irq_service;
400}