irq_service_dcn32.c

  1/*
  2 * Copyright 2022 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#include "dm_services.h"
 27#include "include/logger_interface.h"
 28#include "../dce110/irq_service_dce110.h"
 29
 30#include "dcn/dcn_3_2_0_offset.h"
 31#include "dcn/dcn_3_2_0_sh_mask.h"
 32
 33#include "irq_service_dcn32.h"
 34
 35#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
 36
 37#define DCN_BASE__INST0_SEG2                       0x000034C0
 38
 39static enum dc_irq_source to_dal_irq_source_dcn32(
 40		struct irq_service *irq_service,
 41		uint32_t src_id,
 42		uint32_t ext_id)
 43{
 44	switch (src_id) {
 45	case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
 46		return DC_IRQ_SOURCE_VBLANK1;
 47	case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
 48		return DC_IRQ_SOURCE_VBLANK2;
 49	case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
 50		return DC_IRQ_SOURCE_VBLANK3;
 51	case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
 52		return DC_IRQ_SOURCE_VBLANK4;
 53	case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
 54		return DC_IRQ_SOURCE_VBLANK5;
 55	case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
 56		return DC_IRQ_SOURCE_VBLANK6;
 57	case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
 58		return DC_IRQ_SOURCE_DC1_VLINE0;
 59	case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
 60		return DC_IRQ_SOURCE_DC2_VLINE0;
 61	case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
 62		return DC_IRQ_SOURCE_DC3_VLINE0;
 63	case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
 64		return DC_IRQ_SOURCE_DC4_VLINE0;
 65	case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
 66		return DC_IRQ_SOURCE_DC5_VLINE0;
 67	case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
 68		return DC_IRQ_SOURCE_DC6_VLINE0;
 69	case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
 70		return DC_IRQ_SOURCE_PFLIP1;
 71	case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
 72		return DC_IRQ_SOURCE_PFLIP2;
 73	case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
 74		return DC_IRQ_SOURCE_PFLIP3;
 75	case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
 76		return DC_IRQ_SOURCE_PFLIP4;
 77	case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
 78		return DC_IRQ_SOURCE_PFLIP5;
 79	case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
 80		return DC_IRQ_SOURCE_PFLIP6;
 81	case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 82		return DC_IRQ_SOURCE_VUPDATE1;
 83	case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 84		return DC_IRQ_SOURCE_VUPDATE2;
 85	case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 86		return DC_IRQ_SOURCE_VUPDATE3;
 87	case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 88		return DC_IRQ_SOURCE_VUPDATE4;
 89	case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 90		return DC_IRQ_SOURCE_VUPDATE5;
 91	case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 92		return DC_IRQ_SOURCE_VUPDATE6;
 93	case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
 94		return DC_IRQ_SOURCE_DMCUB_OUTBOX;
 95	case DCN_1_0__SRCID__DC_HPD1_INT:
 96		/* generic src_id for all HPD and HPDRX interrupts */
 97		switch (ext_id) {
 98		case DCN_1_0__CTXID__DC_HPD1_INT:
 99			return DC_IRQ_SOURCE_HPD1;
100		case DCN_1_0__CTXID__DC_HPD2_INT:
101			return DC_IRQ_SOURCE_HPD2;
102		case DCN_1_0__CTXID__DC_HPD3_INT:
103			return DC_IRQ_SOURCE_HPD3;
104		case DCN_1_0__CTXID__DC_HPD4_INT:
105			return DC_IRQ_SOURCE_HPD4;
106		case DCN_1_0__CTXID__DC_HPD5_INT:
107			return DC_IRQ_SOURCE_HPD5;
108		case DCN_1_0__CTXID__DC_HPD6_INT:
109			return DC_IRQ_SOURCE_HPD6;
110		case DCN_1_0__CTXID__DC_HPD1_RX_INT:
111			return DC_IRQ_SOURCE_HPD1RX;
112		case DCN_1_0__CTXID__DC_HPD2_RX_INT:
113			return DC_IRQ_SOURCE_HPD2RX;
114		case DCN_1_0__CTXID__DC_HPD3_RX_INT:
115			return DC_IRQ_SOURCE_HPD3RX;
116		case DCN_1_0__CTXID__DC_HPD4_RX_INT:
117			return DC_IRQ_SOURCE_HPD4RX;
118		case DCN_1_0__CTXID__DC_HPD5_RX_INT:
119			return DC_IRQ_SOURCE_HPD5RX;
120		case DCN_1_0__CTXID__DC_HPD6_RX_INT:
121			return DC_IRQ_SOURCE_HPD6RX;
122		default:
123			return DC_IRQ_SOURCE_INVALID;
124		}
125		break;
126
127	default:
128		return DC_IRQ_SOURCE_INVALID;
129	}
130}
131
132static struct irq_source_info_funcs hpd_irq_info_funcs  = {
133	.set = NULL,
134	.ack = hpd0_ack
135};
136
137static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
138	.set = NULL,
139	.ack = NULL
140};
141
142static struct irq_source_info_funcs pflip_irq_info_funcs = {
143	.set = NULL,
144	.ack = NULL
145};
146
147static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
148	.set = NULL,
149	.ack = NULL
150};
151
152static struct irq_source_info_funcs vblank_irq_info_funcs = {
153	.set = NULL,
154	.ack = NULL
155};
156
157static struct irq_source_info_funcs outbox_irq_info_funcs = {
158	.set = NULL,
159	.ack = NULL
160};
161
162static struct irq_source_info_funcs vline0_irq_info_funcs = {
163	.set = NULL,
164	.ack = NULL
165};
166
167static struct irq_source_info_funcs vline1_irq_info_funcs = {
168	.set = NULL,
169	.ack = NULL
170};
171
172static struct irq_source_info_funcs vline2_irq_info_funcs = {
173	.set = NULL,
174	.ack = NULL
175};
176
177#undef BASE_INNER
178#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
179
180/* compile time expand base address. */
181#define BASE(seg) \
182	BASE_INNER(seg)
183
184#define SRI(reg_name, block, id)\
185	BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
186			reg ## block ## id ## _ ## reg_name
187
188#define SRI_DMUB(reg_name)\
189	BASE(reg ## reg_name ## _BASE_IDX) + \
190			reg ## reg_name
191
192#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
193	.enable_reg = SRI(reg1, block, reg_num),\
194	.enable_mask = \
195		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
196	.enable_value = {\
197		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
198		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
199	},\
200	.ack_reg = SRI(reg2, block, reg_num),\
201	.ack_mask = \
202		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
203	.ack_value = \
204		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
205
206#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
207	.enable_reg = SRI_DMUB(reg1),\
208	.enable_mask = \
209		reg1 ## __ ## mask1 ## _MASK,\
210	.enable_value = {\
211		reg1 ## __ ## mask1 ## _MASK,\
212		~reg1 ## __ ## mask1 ## _MASK \
213	},\
214	.ack_reg = SRI_DMUB(reg2),\
215	.ack_mask = \
216		reg2 ## __ ## mask2 ## _MASK,\
217	.ack_value = \
218		reg2 ## __ ## mask2 ## _MASK \
219
220#define hpd_int_entry(reg_num)\
221	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
222		IRQ_REG_ENTRY(HPD, reg_num,\
223			DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
224			DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
225		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
226		.funcs = &hpd_irq_info_funcs\
227	}
228
229#define hpd_rx_int_entry(reg_num)\
230	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
231		IRQ_REG_ENTRY(HPD, reg_num,\
232			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
233			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
234		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
235		.funcs = &hpd_rx_irq_info_funcs\
236	}
237#define pflip_int_entry(reg_num)\
238	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
239		IRQ_REG_ENTRY(HUBPREQ, reg_num,\
240			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
241			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
242		.funcs = &pflip_irq_info_funcs\
243	}
244
245#define vblank_int_entry(reg_num)\
246	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
247		IRQ_REG_ENTRY(OTG, reg_num,\
248			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
249			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
250		.funcs = &vblank_irq_info_funcs\
251	}
252/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
253 * of DCE's DC_IRQ_SOURCE_VUPDATEx.
254 */
255#define vupdate_no_lock_int_entry(reg_num)\
256	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
257		IRQ_REG_ENTRY(OTG, reg_num,\
258			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
259			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
260		.funcs = &vupdate_no_lock_irq_info_funcs\
261	}
262
263#define vline0_int_entry(reg_num)\
264	[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
265		IRQ_REG_ENTRY(OTG, reg_num,\
266			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
267			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
268		.funcs = &vline0_irq_info_funcs\
269	}
270#define vline1_int_entry(reg_num)\
271	[DC_IRQ_SOURCE_DC1_VLINE1 + reg_num] = {\
272		IRQ_REG_ENTRY(OTG, reg_num,\
273			OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE,\
274			OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_CLEAR),\
275		.funcs = &vline1_irq_info_funcs\
276	}
277#define vline2_int_entry(reg_num)\
278	[DC_IRQ_SOURCE_DC1_VLINE2 + reg_num] = {\
279		IRQ_REG_ENTRY(OTG, reg_num,\
280			OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE,\
281			OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_CLEAR),\
282		.funcs = &vline2_irq_info_funcs\
283	}
284#define dmub_outbox_int_entry()\
285	[DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
286		IRQ_REG_ENTRY_DMUB(\
287			DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
288			DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
289		.funcs = &outbox_irq_info_funcs\
290	}
291
292#define dummy_irq_entry() \
293	{\
294		.funcs = &dummy_irq_info_funcs\
295	}
296
297#define i2c_int_entry(reg_num) \
298	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
299
300#define dp_sink_int_entry(reg_num) \
301	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
302
303#define gpio_pad_int_entry(reg_num) \
304	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
305
306#define dc_underflow_int_entry(reg_num) \
307	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
308
309static struct irq_source_info_funcs dummy_irq_info_funcs = {
310	.set = dal_irq_service_dummy_set,
311	.ack = dal_irq_service_dummy_ack
312};
313
314static const struct irq_source_info
315irq_source_info_dcn32[DAL_IRQ_SOURCES_NUMBER] = {
316	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
317	hpd_int_entry(0),
318	hpd_int_entry(1),
319	hpd_int_entry(2),
320	hpd_int_entry(3),
321	hpd_int_entry(4),
322	hpd_rx_int_entry(0),
323	hpd_rx_int_entry(1),
324	hpd_rx_int_entry(2),
325	hpd_rx_int_entry(3),
326	hpd_rx_int_entry(4),
327	i2c_int_entry(1),
328	i2c_int_entry(2),
329	i2c_int_entry(3),
330	i2c_int_entry(4),
331	i2c_int_entry(5),
332	i2c_int_entry(6),
333	dp_sink_int_entry(1),
334	dp_sink_int_entry(2),
335	dp_sink_int_entry(3),
336	dp_sink_int_entry(4),
337	dp_sink_int_entry(5),
338	dp_sink_int_entry(6),
339	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
340	pflip_int_entry(0),
341	pflip_int_entry(1),
342	pflip_int_entry(2),
343	pflip_int_entry(3),
344	[DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
345	[DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
346	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
347	gpio_pad_int_entry(0),
348	gpio_pad_int_entry(1),
349	gpio_pad_int_entry(2),
350	gpio_pad_int_entry(3),
351	gpio_pad_int_entry(4),
352	gpio_pad_int_entry(5),
353	gpio_pad_int_entry(6),
354	gpio_pad_int_entry(7),
355	gpio_pad_int_entry(8),
356	gpio_pad_int_entry(9),
357	gpio_pad_int_entry(10),
358	gpio_pad_int_entry(11),
359	gpio_pad_int_entry(12),
360	gpio_pad_int_entry(13),
361	gpio_pad_int_entry(14),
362	gpio_pad_int_entry(15),
363	gpio_pad_int_entry(16),
364	gpio_pad_int_entry(17),
365	gpio_pad_int_entry(18),
366	gpio_pad_int_entry(19),
367	gpio_pad_int_entry(20),
368	gpio_pad_int_entry(21),
369	gpio_pad_int_entry(22),
370	gpio_pad_int_entry(23),
371	gpio_pad_int_entry(24),
372	gpio_pad_int_entry(25),
373	gpio_pad_int_entry(26),
374	gpio_pad_int_entry(27),
375	gpio_pad_int_entry(28),
376	gpio_pad_int_entry(29),
377	gpio_pad_int_entry(30),
378	dc_underflow_int_entry(1),
379	dc_underflow_int_entry(2),
380	dc_underflow_int_entry(3),
381	dc_underflow_int_entry(4),
382	dc_underflow_int_entry(5),
383	dc_underflow_int_entry(6),
384	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
385	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
386	vblank_int_entry(0),
387	vblank_int_entry(1),
388	vblank_int_entry(2),
389	vblank_int_entry(3),
390	[DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),
391	[DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),
392	dmub_outbox_int_entry(),
393	vupdate_no_lock_int_entry(0),
394	vupdate_no_lock_int_entry(1),
395	vupdate_no_lock_int_entry(2),
396	vupdate_no_lock_int_entry(3),
397	vline0_int_entry(0),
398	vline0_int_entry(1),
399	vline0_int_entry(2),
400	vline0_int_entry(3),
401	vline1_int_entry(0),
402	vline1_int_entry(1),
403	vline1_int_entry(2),
404	vline1_int_entry(3),
405	vline2_int_entry(0),
406	vline2_int_entry(1),
407	vline2_int_entry(2),
408	vline2_int_entry(3)
409};
410
411static const struct irq_service_funcs irq_service_funcs_dcn32 = {
412		.to_dal_irq_source = to_dal_irq_source_dcn32
413};
414
415static void dcn32_irq_construct(
416	struct irq_service *irq_service,
417	struct irq_service_init_data *init_data)
418{
419	dal_irq_service_construct(irq_service, init_data);
420
421	irq_service->info = irq_source_info_dcn32;
422	irq_service->funcs = &irq_service_funcs_dcn32;
423}
424
425struct irq_service *dal_irq_service_dcn32_create(
426	struct irq_service_init_data *init_data)
427{
428	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
429						  GFP_KERNEL);
430
431	if (!irq_service)
432		return NULL;
433
434	dcn32_irq_construct(irq_service, init_data);
435	return irq_service;
436}