irq_service_dcn314.c

  1// SPDX-License-Identifier: MIT
  2/*
  3 * Copyright 2022 Advanced Micro Devices, Inc.
  4 *
  5 * Permission is hereby granted, free of charge, to any person obtaining a
  6 * copy of this software and associated documentation files (the "Software"),
  7 * to deal in the Software without restriction, including without limitation
  8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9 * and/or sell copies of the Software, and to permit persons to whom the
 10 * Software is furnished to do so, subject to the following conditions:
 11 *
 12 * The above copyright notice and this permission notice shall be included in
 13 * all copies or substantial portions of the Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 21 * OTHER DEALINGS IN THE SOFTWARE.
 22 *
 23 * Authors: AMD
 24 *
 25 */
 26
 27#include "dm_services.h"
 28#include "include/logger_interface.h"
 29#include "../dce110/irq_service_dce110.h"
 30
 31
 32#include "dcn/dcn_3_1_4_offset.h"
 33#include "dcn/dcn_3_1_4_sh_mask.h"
 34
 35#include "irq_service_dcn314.h"
 36
 37#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
 38
 39#define DCN_BASE__INST0_SEG2                       0x000034C0
 40
 41static enum dc_irq_source to_dal_irq_source_dcn314(struct irq_service *irq_service,
 42						   uint32_t src_id,
 43						   uint32_t ext_id)
 44{
 45	switch (src_id) {
 46	case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
 47		return DC_IRQ_SOURCE_VBLANK1;
 48	case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
 49		return DC_IRQ_SOURCE_VBLANK2;
 50	case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
 51		return DC_IRQ_SOURCE_VBLANK3;
 52	case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
 53		return DC_IRQ_SOURCE_VBLANK4;
 54	case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
 55		return DC_IRQ_SOURCE_VBLANK5;
 56	case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
 57		return DC_IRQ_SOURCE_VBLANK6;
 58	case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
 59		return DC_IRQ_SOURCE_DC1_VLINE0;
 60	case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
 61		return DC_IRQ_SOURCE_DC2_VLINE0;
 62	case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
 63		return DC_IRQ_SOURCE_DC3_VLINE0;
 64	case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
 65		return DC_IRQ_SOURCE_DC4_VLINE0;
 66	case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
 67		return DC_IRQ_SOURCE_DC5_VLINE0;
 68	case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
 69		return DC_IRQ_SOURCE_DC6_VLINE0;
 70	case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
 71		return DC_IRQ_SOURCE_PFLIP1;
 72	case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
 73		return DC_IRQ_SOURCE_PFLIP2;
 74	case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
 75		return DC_IRQ_SOURCE_PFLIP3;
 76	case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
 77		return DC_IRQ_SOURCE_PFLIP4;
 78	case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
 79		return DC_IRQ_SOURCE_PFLIP5;
 80	case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
 81		return DC_IRQ_SOURCE_PFLIP6;
 82	case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 83		return DC_IRQ_SOURCE_VUPDATE1;
 84	case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 85		return DC_IRQ_SOURCE_VUPDATE2;
 86	case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 87		return DC_IRQ_SOURCE_VUPDATE3;
 88	case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 89		return DC_IRQ_SOURCE_VUPDATE4;
 90	case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 91		return DC_IRQ_SOURCE_VUPDATE5;
 92	case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 93		return DC_IRQ_SOURCE_VUPDATE6;
 94	case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
 95		return DC_IRQ_SOURCE_DMCUB_OUTBOX;
 96	case DCN_1_0__SRCID__DC_HPD1_INT:
 97		/* generic src_id for all HPD and HPDRX interrupts */
 98		switch (ext_id) {
 99		case DCN_1_0__CTXID__DC_HPD1_INT:
100			return DC_IRQ_SOURCE_HPD1;
101		case DCN_1_0__CTXID__DC_HPD2_INT:
102			return DC_IRQ_SOURCE_HPD2;
103		case DCN_1_0__CTXID__DC_HPD3_INT:
104			return DC_IRQ_SOURCE_HPD3;
105		case DCN_1_0__CTXID__DC_HPD4_INT:
106			return DC_IRQ_SOURCE_HPD4;
107		case DCN_1_0__CTXID__DC_HPD5_INT:
108			return DC_IRQ_SOURCE_HPD5;
109		case DCN_1_0__CTXID__DC_HPD6_INT:
110			return DC_IRQ_SOURCE_HPD6;
111		case DCN_1_0__CTXID__DC_HPD1_RX_INT:
112			return DC_IRQ_SOURCE_HPD1RX;
113		case DCN_1_0__CTXID__DC_HPD2_RX_INT:
114			return DC_IRQ_SOURCE_HPD2RX;
115		case DCN_1_0__CTXID__DC_HPD3_RX_INT:
116			return DC_IRQ_SOURCE_HPD3RX;
117		case DCN_1_0__CTXID__DC_HPD4_RX_INT:
118			return DC_IRQ_SOURCE_HPD4RX;
119		case DCN_1_0__CTXID__DC_HPD5_RX_INT:
120			return DC_IRQ_SOURCE_HPD5RX;
121		case DCN_1_0__CTXID__DC_HPD6_RX_INT:
122			return DC_IRQ_SOURCE_HPD6RX;
123		default:
124			return DC_IRQ_SOURCE_INVALID;
125		}
126		break;
127
128	default:
129		return DC_IRQ_SOURCE_INVALID;
130	}
131}
132
133static struct irq_source_info_funcs hpd_irq_info_funcs  = {
134	.set = NULL,
135	.ack = hpd0_ack
136};
137
138static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
139	.set = NULL,
140	.ack = NULL
141};
142
143static struct irq_source_info_funcs pflip_irq_info_funcs = {
144	.set = NULL,
145	.ack = NULL
146};
147
148static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
149	.set = NULL,
150	.ack = NULL
151};
152
153static struct irq_source_info_funcs vblank_irq_info_funcs = {
154	.set = NULL,
155	.ack = NULL
156};
157
158static struct irq_source_info_funcs outbox_irq_info_funcs = {
159	.set = NULL,
160	.ack = NULL
161};
162
163static struct irq_source_info_funcs vline0_irq_info_funcs = {
164	.set = NULL,
165	.ack = NULL
166};
167
168#undef BASE_INNER
169#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
170
171/* compile time expand base address. */
172#define BASE(seg) \
173	BASE_INNER(seg)
174
175#define SRI(reg_name, block, id)\
176	(BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
177			reg ## block ## id ## _ ## reg_name)
178
179#define SRI_DMUB(reg_name)\
180	(BASE(reg ## reg_name ## _BASE_IDX) + \
181			reg ## reg_name)
182
183#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
184	.enable_reg = SRI(reg1, block, reg_num),\
185	.enable_mask = \
186		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
187	.enable_value = {\
188		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
189		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
190	},\
191	.ack_reg = SRI(reg2, block, reg_num),\
192	.ack_mask = \
193		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
194	.ack_value = \
195		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
196
197#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
198	.enable_reg = SRI_DMUB(reg1),\
199	.enable_mask = \
200		reg1 ## __ ## mask1 ## _MASK,\
201	.enable_value = {\
202		reg1 ## __ ## mask1 ## _MASK,\
203		~reg1 ## __ ## mask1 ## _MASK \
204	},\
205	.ack_reg = SRI_DMUB(reg2),\
206	.ack_mask = \
207		reg2 ## __ ## mask2 ## _MASK,\
208	.ack_value = \
209		reg2 ## __ ## mask2 ## _MASK \
210
211#define hpd_int_entry(reg_num)\
212	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
213		IRQ_REG_ENTRY(HPD, reg_num,\
214			DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
215			DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
216		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
217		.funcs = &hpd_irq_info_funcs\
218	}
219
220#define hpd_rx_int_entry(reg_num)\
221	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
222		IRQ_REG_ENTRY(HPD, reg_num,\
223			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
224			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
225		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
226		.funcs = &hpd_rx_irq_info_funcs\
227	}
228#define pflip_int_entry(reg_num)\
229	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
230		IRQ_REG_ENTRY(HUBPREQ, reg_num,\
231			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
232			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
233		.funcs = &pflip_irq_info_funcs\
234	}
235
236/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
237 * of DCE's DC_IRQ_SOURCE_VUPDATEx.
238 */
239#define vupdate_no_lock_int_entry(reg_num)\
240	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
241		IRQ_REG_ENTRY(OTG, reg_num,\
242			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
243			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
244		.funcs = &vupdate_no_lock_irq_info_funcs\
245	}
246
247#define vblank_int_entry(reg_num)\
248	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
249		IRQ_REG_ENTRY(OTG, reg_num,\
250			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
251			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
252		.funcs = &vblank_irq_info_funcs\
253	}
254
255#define vline0_int_entry(reg_num)\
256	[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
257		IRQ_REG_ENTRY(OTG, reg_num,\
258			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
259			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
260		.funcs = &vline0_irq_info_funcs\
261	}
262#define dmub_outbox_int_entry()\
263	[DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
264		IRQ_REG_ENTRY_DMUB(\
265			DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
266			DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
267		.funcs = &outbox_irq_info_funcs\
268	}
269
270#define dummy_irq_entry() \
271	{\
272		.funcs = &dummy_irq_info_funcs\
273	}
274
275#define i2c_int_entry(reg_num) \
276	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
277
278#define dp_sink_int_entry(reg_num) \
279	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
280
281#define gpio_pad_int_entry(reg_num) \
282	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
283
284#define dc_underflow_int_entry(reg_num) \
285	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
286
287static struct irq_source_info_funcs dummy_irq_info_funcs = {
288	.set = dal_irq_service_dummy_set,
289	.ack = dal_irq_service_dummy_ack
290};
291
292static const struct irq_source_info
293irq_source_info_dcn314[DAL_IRQ_SOURCES_NUMBER] = {
294	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
295	hpd_int_entry(0),
296	hpd_int_entry(1),
297	hpd_int_entry(2),
298	hpd_int_entry(3),
299	hpd_int_entry(4),
300	hpd_rx_int_entry(0),
301	hpd_rx_int_entry(1),
302	hpd_rx_int_entry(2),
303	hpd_rx_int_entry(3),
304	hpd_rx_int_entry(4),
305	i2c_int_entry(1),
306	i2c_int_entry(2),
307	i2c_int_entry(3),
308	i2c_int_entry(4),
309	i2c_int_entry(5),
310	i2c_int_entry(6),
311	dp_sink_int_entry(1),
312	dp_sink_int_entry(2),
313	dp_sink_int_entry(3),
314	dp_sink_int_entry(4),
315	dp_sink_int_entry(5),
316	dp_sink_int_entry(6),
317	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
318	pflip_int_entry(0),
319	pflip_int_entry(1),
320	pflip_int_entry(2),
321	pflip_int_entry(3),
322	[DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
323	[DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
324	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
325	gpio_pad_int_entry(0),
326	gpio_pad_int_entry(1),
327	gpio_pad_int_entry(2),
328	gpio_pad_int_entry(3),
329	gpio_pad_int_entry(4),
330	gpio_pad_int_entry(5),
331	gpio_pad_int_entry(6),
332	gpio_pad_int_entry(7),
333	gpio_pad_int_entry(8),
334	gpio_pad_int_entry(9),
335	gpio_pad_int_entry(10),
336	gpio_pad_int_entry(11),
337	gpio_pad_int_entry(12),
338	gpio_pad_int_entry(13),
339	gpio_pad_int_entry(14),
340	gpio_pad_int_entry(15),
341	gpio_pad_int_entry(16),
342	gpio_pad_int_entry(17),
343	gpio_pad_int_entry(18),
344	gpio_pad_int_entry(19),
345	gpio_pad_int_entry(20),
346	gpio_pad_int_entry(21),
347	gpio_pad_int_entry(22),
348	gpio_pad_int_entry(23),
349	gpio_pad_int_entry(24),
350	gpio_pad_int_entry(25),
351	gpio_pad_int_entry(26),
352	gpio_pad_int_entry(27),
353	gpio_pad_int_entry(28),
354	gpio_pad_int_entry(29),
355	gpio_pad_int_entry(30),
356	dc_underflow_int_entry(1),
357	dc_underflow_int_entry(2),
358	dc_underflow_int_entry(3),
359	dc_underflow_int_entry(4),
360	dc_underflow_int_entry(5),
361	dc_underflow_int_entry(6),
362	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
363	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
364	vupdate_no_lock_int_entry(0),
365	vupdate_no_lock_int_entry(1),
366	vupdate_no_lock_int_entry(2),
367	vupdate_no_lock_int_entry(3),
368	vblank_int_entry(0),
369	vblank_int_entry(1),
370	vblank_int_entry(2),
371	vblank_int_entry(3),
372	vline0_int_entry(0),
373	vline0_int_entry(1),
374	vline0_int_entry(2),
375	vline0_int_entry(3),
376	[DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),
377	[DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),
378	dmub_outbox_int_entry(),
379};
380
381static const struct irq_service_funcs irq_service_funcs_dcn314 = {
382		.to_dal_irq_source = to_dal_irq_source_dcn314
383};
384
385static void dcn314_irq_construct(
386	struct irq_service *irq_service,
387	struct irq_service_init_data *init_data)
388{
389	dal_irq_service_construct(irq_service, init_data);
390
391	irq_service->info = irq_source_info_dcn314;
392	irq_service->funcs = &irq_service_funcs_dcn314;
393}
394
395struct irq_service *dal_irq_service_dcn314_create(
396	struct irq_service_init_data *init_data)
397{
398	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
399						  GFP_KERNEL);
400
401	if (!irq_service)
402		return NULL;
403
404	dcn314_irq_construct(irq_service, init_data);
405	return irq_service;
406}