irq_service_dcn31.c

  1/*
  2 * Copyright 2020 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#include "dm_services.h"
 27#include "include/logger_interface.h"
 28#include "../dce110/irq_service_dce110.h"
 29
 30
 31#include "yellow_carp_offset.h"
 32#include "dcn/dcn_3_1_2_offset.h"
 33#include "dcn/dcn_3_1_2_sh_mask.h"
 34
 35#include "irq_service_dcn31.h"
 36
 37#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
 38
 39static enum dc_irq_source to_dal_irq_source_dcn31(struct irq_service *irq_service,
 40						  uint32_t src_id,
 41						  uint32_t ext_id)
 42{
 43	switch (src_id) {
 44	case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
 45		return DC_IRQ_SOURCE_VBLANK1;
 46	case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
 47		return DC_IRQ_SOURCE_VBLANK2;
 48	case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
 49		return DC_IRQ_SOURCE_VBLANK3;
 50	case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
 51		return DC_IRQ_SOURCE_VBLANK4;
 52	case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
 53		return DC_IRQ_SOURCE_VBLANK5;
 54	case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
 55		return DC_IRQ_SOURCE_VBLANK6;
 56	case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
 57		return DC_IRQ_SOURCE_DC1_VLINE0;
 58	case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
 59		return DC_IRQ_SOURCE_DC2_VLINE0;
 60	case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
 61		return DC_IRQ_SOURCE_DC3_VLINE0;
 62	case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
 63		return DC_IRQ_SOURCE_DC4_VLINE0;
 64	case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
 65		return DC_IRQ_SOURCE_DC5_VLINE0;
 66	case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
 67		return DC_IRQ_SOURCE_DC6_VLINE0;
 68	case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
 69		return DC_IRQ_SOURCE_PFLIP1;
 70	case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
 71		return DC_IRQ_SOURCE_PFLIP2;
 72	case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
 73		return DC_IRQ_SOURCE_PFLIP3;
 74	case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
 75		return DC_IRQ_SOURCE_PFLIP4;
 76	case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
 77		return DC_IRQ_SOURCE_PFLIP5;
 78	case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
 79		return DC_IRQ_SOURCE_PFLIP6;
 80	case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 81		return DC_IRQ_SOURCE_VUPDATE1;
 82	case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 83		return DC_IRQ_SOURCE_VUPDATE2;
 84	case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 85		return DC_IRQ_SOURCE_VUPDATE3;
 86	case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 87		return DC_IRQ_SOURCE_VUPDATE4;
 88	case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 89		return DC_IRQ_SOURCE_VUPDATE5;
 90	case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 91		return DC_IRQ_SOURCE_VUPDATE6;
 92	case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
 93		return DC_IRQ_SOURCE_DMCUB_OUTBOX;
 94	case DCN_1_0__SRCID__DC_HPD1_INT:
 95		/* generic src_id for all HPD and HPDRX interrupts */
 96		switch (ext_id) {
 97		case DCN_1_0__CTXID__DC_HPD1_INT:
 98			return DC_IRQ_SOURCE_HPD1;
 99		case DCN_1_0__CTXID__DC_HPD2_INT:
100			return DC_IRQ_SOURCE_HPD2;
101		case DCN_1_0__CTXID__DC_HPD3_INT:
102			return DC_IRQ_SOURCE_HPD3;
103		case DCN_1_0__CTXID__DC_HPD4_INT:
104			return DC_IRQ_SOURCE_HPD4;
105		case DCN_1_0__CTXID__DC_HPD5_INT:
106			return DC_IRQ_SOURCE_HPD5;
107		case DCN_1_0__CTXID__DC_HPD6_INT:
108			return DC_IRQ_SOURCE_HPD6;
109		case DCN_1_0__CTXID__DC_HPD1_RX_INT:
110			return DC_IRQ_SOURCE_HPD1RX;
111		case DCN_1_0__CTXID__DC_HPD2_RX_INT:
112			return DC_IRQ_SOURCE_HPD2RX;
113		case DCN_1_0__CTXID__DC_HPD3_RX_INT:
114			return DC_IRQ_SOURCE_HPD3RX;
115		case DCN_1_0__CTXID__DC_HPD4_RX_INT:
116			return DC_IRQ_SOURCE_HPD4RX;
117		case DCN_1_0__CTXID__DC_HPD5_RX_INT:
118			return DC_IRQ_SOURCE_HPD5RX;
119		case DCN_1_0__CTXID__DC_HPD6_RX_INT:
120			return DC_IRQ_SOURCE_HPD6RX;
121		default:
122			return DC_IRQ_SOURCE_INVALID;
123		}
124		break;
125
126	default:
127		return DC_IRQ_SOURCE_INVALID;
128	}
129}
130
131static struct irq_source_info_funcs hpd_irq_info_funcs  = {
132	.set = NULL,
133	.ack = hpd0_ack
134};
135
136static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
137	.set = NULL,
138	.ack = NULL
139};
140
141static struct irq_source_info_funcs pflip_irq_info_funcs = {
142	.set = NULL,
143	.ack = NULL
144};
145
146static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
147	.set = NULL,
148	.ack = NULL
149};
150
151static struct irq_source_info_funcs vblank_irq_info_funcs = {
152	.set = NULL,
153	.ack = NULL
154};
155
156static struct irq_source_info_funcs outbox_irq_info_funcs = {
157	.set = NULL,
158	.ack = NULL
159};
160
161static struct irq_source_info_funcs vline0_irq_info_funcs = {
162	.set = NULL,
163	.ack = NULL
164};
165
166#undef BASE_INNER
167#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
168
169/* compile time expand base address. */
170#define BASE(seg) \
171	BASE_INNER(seg)
172
173#define SRI(reg_name, block, id)\
174	BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
175			reg ## block ## id ## _ ## reg_name
176
177#define SRI_DMUB(reg_name)\
178	BASE(reg ## reg_name ## _BASE_IDX) + \
179			reg ## reg_name
180
181#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
182	.enable_reg = SRI(reg1, block, reg_num),\
183	.enable_mask = \
184		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
185	.enable_value = {\
186		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
187		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
188	},\
189	.ack_reg = SRI(reg2, block, reg_num),\
190	.ack_mask = \
191		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
192	.ack_value = \
193		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
194
195#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
196	.enable_reg = SRI_DMUB(reg1),\
197	.enable_mask = \
198		reg1 ## __ ## mask1 ## _MASK,\
199	.enable_value = {\
200		reg1 ## __ ## mask1 ## _MASK,\
201		~reg1 ## __ ## mask1 ## _MASK \
202	},\
203	.ack_reg = SRI_DMUB(reg2),\
204	.ack_mask = \
205		reg2 ## __ ## mask2 ## _MASK,\
206	.ack_value = \
207		reg2 ## __ ## mask2 ## _MASK \
208
209#define hpd_int_entry(reg_num)\
210	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
211		IRQ_REG_ENTRY(HPD, reg_num,\
212			DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
213			DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
214		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
215		.funcs = &hpd_irq_info_funcs\
216	}
217
218#define hpd_rx_int_entry(reg_num)\
219	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
220		IRQ_REG_ENTRY(HPD, reg_num,\
221			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
222			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
223		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
224		.funcs = &hpd_rx_irq_info_funcs\
225	}
226#define pflip_int_entry(reg_num)\
227	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
228		IRQ_REG_ENTRY(HUBPREQ, reg_num,\
229			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
230			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
231		.funcs = &pflip_irq_info_funcs\
232	}
233
234/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
235 * of DCE's DC_IRQ_SOURCE_VUPDATEx.
236 */
237#define vupdate_no_lock_int_entry(reg_num)\
238	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
239		IRQ_REG_ENTRY(OTG, reg_num,\
240			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
241			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
242		.funcs = &vupdate_no_lock_irq_info_funcs\
243	}
244
245#define vblank_int_entry(reg_num)\
246	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
247		IRQ_REG_ENTRY(OTG, reg_num,\
248			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
249			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
250		.funcs = &vblank_irq_info_funcs\
251	}
252
253#define vline0_int_entry(reg_num)\
254	[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
255		IRQ_REG_ENTRY(OTG, reg_num,\
256			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
257			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
258		.funcs = &vline0_irq_info_funcs\
259	}
260#define dmub_outbox_int_entry()\
261	[DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
262		IRQ_REG_ENTRY_DMUB(\
263			DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
264			DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
265		.funcs = &outbox_irq_info_funcs\
266	}
267
268#define dummy_irq_entry() \
269	{\
270		.funcs = &dummy_irq_info_funcs\
271	}
272
273#define i2c_int_entry(reg_num) \
274	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
275
276#define dp_sink_int_entry(reg_num) \
277	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
278
279#define gpio_pad_int_entry(reg_num) \
280	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
281
282#define dc_underflow_int_entry(reg_num) \
283	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
284
285static struct irq_source_info_funcs dummy_irq_info_funcs = {
286	.set = dal_irq_service_dummy_set,
287	.ack = dal_irq_service_dummy_ack
288};
289
290static const struct irq_source_info
291irq_source_info_dcn31[DAL_IRQ_SOURCES_NUMBER] = {
292	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
293	hpd_int_entry(0),
294	hpd_int_entry(1),
295	hpd_int_entry(2),
296	hpd_int_entry(3),
297	hpd_int_entry(4),
298	hpd_rx_int_entry(0),
299	hpd_rx_int_entry(1),
300	hpd_rx_int_entry(2),
301	hpd_rx_int_entry(3),
302	hpd_rx_int_entry(4),
303	i2c_int_entry(1),
304	i2c_int_entry(2),
305	i2c_int_entry(3),
306	i2c_int_entry(4),
307	i2c_int_entry(5),
308	i2c_int_entry(6),
309	dp_sink_int_entry(1),
310	dp_sink_int_entry(2),
311	dp_sink_int_entry(3),
312	dp_sink_int_entry(4),
313	dp_sink_int_entry(5),
314	dp_sink_int_entry(6),
315	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
316	pflip_int_entry(0),
317	pflip_int_entry(1),
318	pflip_int_entry(2),
319	pflip_int_entry(3),
320	[DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
321	[DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
322	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
323	gpio_pad_int_entry(0),
324	gpio_pad_int_entry(1),
325	gpio_pad_int_entry(2),
326	gpio_pad_int_entry(3),
327	gpio_pad_int_entry(4),
328	gpio_pad_int_entry(5),
329	gpio_pad_int_entry(6),
330	gpio_pad_int_entry(7),
331	gpio_pad_int_entry(8),
332	gpio_pad_int_entry(9),
333	gpio_pad_int_entry(10),
334	gpio_pad_int_entry(11),
335	gpio_pad_int_entry(12),
336	gpio_pad_int_entry(13),
337	gpio_pad_int_entry(14),
338	gpio_pad_int_entry(15),
339	gpio_pad_int_entry(16),
340	gpio_pad_int_entry(17),
341	gpio_pad_int_entry(18),
342	gpio_pad_int_entry(19),
343	gpio_pad_int_entry(20),
344	gpio_pad_int_entry(21),
345	gpio_pad_int_entry(22),
346	gpio_pad_int_entry(23),
347	gpio_pad_int_entry(24),
348	gpio_pad_int_entry(25),
349	gpio_pad_int_entry(26),
350	gpio_pad_int_entry(27),
351	gpio_pad_int_entry(28),
352	gpio_pad_int_entry(29),
353	gpio_pad_int_entry(30),
354	dc_underflow_int_entry(1),
355	dc_underflow_int_entry(2),
356	dc_underflow_int_entry(3),
357	dc_underflow_int_entry(4),
358	dc_underflow_int_entry(5),
359	dc_underflow_int_entry(6),
360	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
361	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
362	vupdate_no_lock_int_entry(0),
363	vupdate_no_lock_int_entry(1),
364	vupdate_no_lock_int_entry(2),
365	vupdate_no_lock_int_entry(3),
366	vblank_int_entry(0),
367	vblank_int_entry(1),
368	vblank_int_entry(2),
369	vblank_int_entry(3),
370	vline0_int_entry(0),
371	vline0_int_entry(1),
372	vline0_int_entry(2),
373	vline0_int_entry(3),
374	[DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),
375	[DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),
376	dmub_outbox_int_entry(),
377};
378
379static const struct irq_service_funcs irq_service_funcs_dcn31 = {
380		.to_dal_irq_source = to_dal_irq_source_dcn31
381};
382
383static void dcn31_irq_construct(
384	struct irq_service *irq_service,
385	struct irq_service_init_data *init_data)
386{
387	dal_irq_service_construct(irq_service, init_data);
388
389	irq_service->info = irq_source_info_dcn31;
390	irq_service->funcs = &irq_service_funcs_dcn31;
391}
392
393struct irq_service *dal_irq_service_dcn31_create(
394	struct irq_service_init_data *init_data)
395{
396	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
397						  GFP_KERNEL);
398
399	if (!irq_service)
400		return NULL;
401
402	dcn31_irq_construct(irq_service, init_data);
403	return irq_service;
404}