irq_service_dcn303.c

  1// SPDX-License-Identifier: MIT
  2/*
  3 * Copyright (C) 2021 Advanced Micro Devices, Inc.
  4 *
  5 * Permission is hereby granted, free of charge, to any person obtaining a
  6 * copy of this software and associated documentation files (the "Software"),
  7 * to deal in the Software without restriction, including without limitation
  8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9 * and/or sell copies of the Software, and to permit persons to whom the
 10 * Software is furnished to do so, subject to the following conditions:
 11 *
 12 * The above copyright notice and this permission notice shall be included in
 13 * all copies or substantial portions of the Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 21 * OTHER DEALINGS IN THE SOFTWARE.
 22 *
 23 * Authors: AMD
 24 *
 25 */
 26
 27#include "dm_services.h"
 28#include "irq_service_dcn303.h"
 29#include "../dce110/irq_service_dce110.h"
 30
 31#include "sienna_cichlid_ip_offset.h"
 32#include "dcn/dcn_3_0_3_offset.h"
 33#include "dcn/dcn_3_0_3_sh_mask.h"
 34
 35#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
 36
 37static enum dc_irq_source to_dal_irq_source_dcn303(struct irq_service *irq_service,
 38						   uint32_t src_id,
 39						   uint32_t ext_id)
 40{
 41	switch (src_id) {
 42	case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
 43		return DC_IRQ_SOURCE_VBLANK1;
 44	case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
 45		return DC_IRQ_SOURCE_VBLANK2;
 46	case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
 47		return DC_IRQ_SOURCE_DC1_VLINE0;
 48	case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
 49		return DC_IRQ_SOURCE_DC2_VLINE0;
 50	case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
 51		return DC_IRQ_SOURCE_PFLIP1;
 52	case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
 53		return DC_IRQ_SOURCE_PFLIP2;
 54	case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 55		return DC_IRQ_SOURCE_VUPDATE1;
 56	case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 57		return DC_IRQ_SOURCE_VUPDATE2;
 58
 59	case DCN_1_0__SRCID__DC_HPD1_INT:
 60		/* generic src_id for all HPD and HPDRX interrupts */
 61		switch (ext_id) {
 62		case DCN_1_0__CTXID__DC_HPD1_INT:
 63			return DC_IRQ_SOURCE_HPD1;
 64		case DCN_1_0__CTXID__DC_HPD2_INT:
 65			return DC_IRQ_SOURCE_HPD2;
 66		case DCN_1_0__CTXID__DC_HPD1_RX_INT:
 67			return DC_IRQ_SOURCE_HPD1RX;
 68		case DCN_1_0__CTXID__DC_HPD2_RX_INT:
 69			return DC_IRQ_SOURCE_HPD2RX;
 70		default:
 71			return DC_IRQ_SOURCE_INVALID;
 72		}
 73		break;
 74
 75	default:
 76		return DC_IRQ_SOURCE_INVALID;
 77	}
 78}
 79
 80static struct irq_source_info_funcs hpd_irq_info_funcs  = {
 81		.set = NULL,
 82		.ack = hpd0_ack
 83};
 84
 85static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
 86		.set = NULL,
 87		.ack = NULL
 88};
 89
 90static struct irq_source_info_funcs pflip_irq_info_funcs = {
 91		.set = NULL,
 92		.ack = NULL
 93};
 94
 95static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
 96	.set = NULL,
 97	.ack = NULL
 98};
 99
100static struct irq_source_info_funcs vblank_irq_info_funcs = {
101		.set = NULL,
102		.ack = NULL
103};
104
105static struct irq_source_info_funcs vline0_irq_info_funcs = {
106	.set = NULL,
107	.ack = NULL
108};
109
110#undef BASE_INNER
111#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
112
113/* compile time expand base address. */
114#define BASE(seg) BASE_INNER(seg)
115
116#define SRI(reg_name, block, id)\
117		BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
118		mm ## block ## id ## _ ## reg_name
119
120
121#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
122		.enable_reg = SRI(reg1, block, reg_num),\
123		.enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
124		.enable_value = {\
125				block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
126				~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
127		},\
128		.ack_reg = SRI(reg2, block, reg_num),\
129		.ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
130		.ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
131
132
133
134#define hpd_int_entry(reg_num)\
135		[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
136				IRQ_REG_ENTRY(HPD, reg_num,\
137						DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
138						DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
139						.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
140						.funcs = &hpd_irq_info_funcs\
141}
142
143#define hpd_rx_int_entry(reg_num)\
144		[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
145				IRQ_REG_ENTRY(HPD, reg_num,\
146						DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
147						DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
148						.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
149						.funcs = &hpd_rx_irq_info_funcs\
150}
151#define pflip_int_entry(reg_num)\
152		[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
153				IRQ_REG_ENTRY(HUBPREQ, reg_num,\
154						DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
155						DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
156						.funcs = &pflip_irq_info_funcs\
157}
158
159/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
160 * of DCE's DC_IRQ_SOURCE_VUPDATEx.
161 */
162#define vupdate_no_lock_int_entry(reg_num)\
163	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
164		IRQ_REG_ENTRY(OTG, reg_num,\
165			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
166			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
167		.funcs = &vupdate_no_lock_irq_info_funcs\
168	}
169
170#define vblank_int_entry(reg_num)\
171	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
172		IRQ_REG_ENTRY(OTG, reg_num,\
173			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
174			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
175		.funcs = &vblank_irq_info_funcs\
176	}
177
178#define vline0_int_entry(reg_num)\
179	[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
180		IRQ_REG_ENTRY(OTG, reg_num,\
181			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
182			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
183		.funcs = &vline0_irq_info_funcs\
184	}
185
186#define dummy_irq_entry() { .funcs = &dummy_irq_info_funcs }
187
188#define i2c_int_entry(reg_num) \
189		[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
190
191#define dp_sink_int_entry(reg_num) \
192		[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
193
194#define gpio_pad_int_entry(reg_num) \
195		[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
196
197#define dc_underflow_int_entry(reg_num) \
198		[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
199
200static struct irq_source_info_funcs dummy_irq_info_funcs = {
201		.set = dal_irq_service_dummy_set,
202		.ack = dal_irq_service_dummy_ack
203};
204
205static const struct irq_source_info irq_source_info_dcn303[DAL_IRQ_SOURCES_NUMBER] = {
206		[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
207		hpd_int_entry(0),
208		hpd_int_entry(1),
209		hpd_rx_int_entry(0),
210		hpd_rx_int_entry(1),
211		i2c_int_entry(1),
212		i2c_int_entry(2),
213		dp_sink_int_entry(1),
214		dp_sink_int_entry(2),
215		[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
216		pflip_int_entry(0),
217		pflip_int_entry(1),
218		[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
219		gpio_pad_int_entry(0),
220		gpio_pad_int_entry(1),
221		gpio_pad_int_entry(2),
222		gpio_pad_int_entry(3),
223		gpio_pad_int_entry(4),
224		gpio_pad_int_entry(5),
225		gpio_pad_int_entry(6),
226		gpio_pad_int_entry(7),
227		gpio_pad_int_entry(8),
228		gpio_pad_int_entry(9),
229		gpio_pad_int_entry(10),
230		gpio_pad_int_entry(11),
231		gpio_pad_int_entry(12),
232		gpio_pad_int_entry(13),
233		gpio_pad_int_entry(14),
234		gpio_pad_int_entry(15),
235		gpio_pad_int_entry(16),
236		gpio_pad_int_entry(17),
237		gpio_pad_int_entry(18),
238		gpio_pad_int_entry(19),
239		gpio_pad_int_entry(20),
240		gpio_pad_int_entry(21),
241		gpio_pad_int_entry(22),
242		gpio_pad_int_entry(23),
243		gpio_pad_int_entry(24),
244		gpio_pad_int_entry(25),
245		gpio_pad_int_entry(26),
246		gpio_pad_int_entry(27),
247		gpio_pad_int_entry(28),
248		gpio_pad_int_entry(29),
249		gpio_pad_int_entry(30),
250		dc_underflow_int_entry(1),
251		dc_underflow_int_entry(2),
252		[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
253		[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
254		vupdate_no_lock_int_entry(0),
255		vupdate_no_lock_int_entry(1),
256		vblank_int_entry(0),
257		vblank_int_entry(1),
258		vline0_int_entry(0),
259		vline0_int_entry(1),
260};
261
262static const struct irq_service_funcs irq_service_funcs_dcn303 = {
263		.to_dal_irq_source = to_dal_irq_source_dcn303
264};
265
266static void dcn303_irq_construct(struct irq_service *irq_service, struct irq_service_init_data *init_data)
267{
268	dal_irq_service_construct(irq_service, init_data);
269
270	irq_service->info = irq_source_info_dcn303;
271	irq_service->funcs = &irq_service_funcs_dcn303;
272}
273
274struct irq_service *dal_irq_service_dcn303_create(struct irq_service_init_data *init_data)
275{
276	struct irq_service *irq_service = kzalloc(sizeof(*irq_service), GFP_KERNEL);
277
278	if (!irq_service)
279		return NULL;
280
281	dcn303_irq_construct(irq_service, init_data);
282	return irq_service;
283}