irq_service_dcn302.c

  1/*
  2 * Copyright 2020 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#include "dm_services.h"
 27
 28#include "irq_service_dcn302.h"
 29
 30#include "../dce110/irq_service_dce110.h"
 31
 32#include "dimgrey_cavefish_ip_offset.h"
 33#include "dcn/dcn_3_0_0_offset.h"
 34#include "dcn/dcn_3_0_0_sh_mask.h"
 35
 36#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
 37
 38static enum dc_irq_source to_dal_irq_source_dcn302(struct irq_service *irq_service, uint32_t src_id, uint32_t ext_id)
 39{
 40	switch (src_id) {
 41	case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
 42		return DC_IRQ_SOURCE_VBLANK1;
 43	case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
 44		return DC_IRQ_SOURCE_VBLANK2;
 45	case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
 46		return DC_IRQ_SOURCE_VBLANK3;
 47	case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
 48		return DC_IRQ_SOURCE_VBLANK4;
 49	case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
 50		return DC_IRQ_SOURCE_VBLANK5;
 51	case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
 52		return DC_IRQ_SOURCE_VBLANK6;
 53	case DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT:
 54		return DC_IRQ_SOURCE_DMCUB_OUTBOX0;
 55	case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
 56		return DC_IRQ_SOURCE_DC1_VLINE0;
 57	case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
 58		return DC_IRQ_SOURCE_DC2_VLINE0;
 59	case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
 60		return DC_IRQ_SOURCE_DC3_VLINE0;
 61	case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
 62		return DC_IRQ_SOURCE_DC4_VLINE0;
 63	case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
 64		return DC_IRQ_SOURCE_DC5_VLINE0;
 65	case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
 66		return DC_IRQ_SOURCE_DC6_VLINE0;
 67	case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
 68		return DC_IRQ_SOURCE_PFLIP1;
 69	case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
 70		return DC_IRQ_SOURCE_PFLIP2;
 71	case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
 72		return DC_IRQ_SOURCE_PFLIP3;
 73	case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
 74		return DC_IRQ_SOURCE_PFLIP4;
 75	case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
 76		return DC_IRQ_SOURCE_PFLIP5;
 77	case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
 78		return DC_IRQ_SOURCE_PFLIP6;
 79	case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 80		return DC_IRQ_SOURCE_VUPDATE1;
 81	case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 82		return DC_IRQ_SOURCE_VUPDATE2;
 83	case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 84		return DC_IRQ_SOURCE_VUPDATE3;
 85	case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 86		return DC_IRQ_SOURCE_VUPDATE4;
 87	case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 88		return DC_IRQ_SOURCE_VUPDATE5;
 89	case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 90		return DC_IRQ_SOURCE_VUPDATE6;
 91
 92	case DCN_1_0__SRCID__DC_HPD1_INT:
 93		/* generic src_id for all HPD and HPDRX interrupts */
 94		switch (ext_id) {
 95		case DCN_1_0__CTXID__DC_HPD1_INT:
 96			return DC_IRQ_SOURCE_HPD1;
 97		case DCN_1_0__CTXID__DC_HPD2_INT:
 98			return DC_IRQ_SOURCE_HPD2;
 99		case DCN_1_0__CTXID__DC_HPD3_INT:
100			return DC_IRQ_SOURCE_HPD3;
101		case DCN_1_0__CTXID__DC_HPD4_INT:
102			return DC_IRQ_SOURCE_HPD4;
103		case DCN_1_0__CTXID__DC_HPD5_INT:
104			return DC_IRQ_SOURCE_HPD5;
105		case DCN_1_0__CTXID__DC_HPD6_INT:
106			return DC_IRQ_SOURCE_HPD6;
107		case DCN_1_0__CTXID__DC_HPD1_RX_INT:
108			return DC_IRQ_SOURCE_HPD1RX;
109		case DCN_1_0__CTXID__DC_HPD2_RX_INT:
110			return DC_IRQ_SOURCE_HPD2RX;
111		case DCN_1_0__CTXID__DC_HPD3_RX_INT:
112			return DC_IRQ_SOURCE_HPD3RX;
113		case DCN_1_0__CTXID__DC_HPD4_RX_INT:
114			return DC_IRQ_SOURCE_HPD4RX;
115		case DCN_1_0__CTXID__DC_HPD5_RX_INT:
116			return DC_IRQ_SOURCE_HPD5RX;
117		case DCN_1_0__CTXID__DC_HPD6_RX_INT:
118			return DC_IRQ_SOURCE_HPD6RX;
119		default:
120			return DC_IRQ_SOURCE_INVALID;
121		}
122		break;
123
124	default:
125		return DC_IRQ_SOURCE_INVALID;
126	}
127}
128
129static struct irq_source_info_funcs hpd_irq_info_funcs  = {
130		.set = NULL,
131		.ack = hpd0_ack
132};
133
134static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
135		.set = NULL,
136		.ack = NULL
137};
138
139static struct irq_source_info_funcs pflip_irq_info_funcs = {
140		.set = NULL,
141		.ack = NULL
142};
143
144static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
145	.set = NULL,
146	.ack = NULL
147};
148
149static struct irq_source_info_funcs vblank_irq_info_funcs = {
150		.set = NULL,
151		.ack = NULL
152};
153
154static struct irq_source_info_funcs dmub_trace_irq_info_funcs = {
155	.set = NULL,
156	.ack = NULL
157};
158
159static struct irq_source_info_funcs vline0_irq_info_funcs = {
160	.set = NULL,
161	.ack = NULL
162};
163
164#undef BASE_INNER
165#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
166
167/* compile time expand base address. */
168#define BASE(seg) BASE_INNER(seg)
169
170#define SRI(reg_name, block, id)\
171		BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
172		mm ## block ## id ## _ ## reg_name
173
174#define SRI_DMUB(reg_name)\
175		BASE(mm ## reg_name ## _BASE_IDX) + \
176			mm ## reg_name
177
178#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
179		.enable_reg = SRI(reg1, block, reg_num),\
180		.enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
181		.enable_value = {\
182				block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
183				~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
184		},\
185		.ack_reg = SRI(reg2, block, reg_num),\
186		.ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
187		.ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
188
189#define dmub_trace_int_entry()\
190	[DC_IRQ_SOURCE_DMCUB_OUTBOX0] = {\
191		IRQ_REG_ENTRY_DMUB(DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX0_READY_INT_EN,\
192			DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX0_READY_INT_ACK),\
193		.funcs = &dmub_trace_irq_info_funcs\
194	}
195
196#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
197	.enable_reg = SRI_DMUB(reg1),\
198	.enable_mask = \
199		reg1 ## __ ## mask1 ## _MASK,\
200	.enable_value = {\
201		reg1 ## __ ## mask1 ## _MASK,\
202		~reg1 ## __ ## mask1 ## _MASK \
203	},\
204	.ack_reg = SRI_DMUB(reg2),\
205	.ack_mask = \
206		reg2 ## __ ## mask2 ## _MASK,\
207	.ack_value = \
208		reg2 ## __ ## mask2 ## _MASK \
209
210#define hpd_int_entry(reg_num)\
211		[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
212				IRQ_REG_ENTRY(HPD, reg_num,\
213						DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
214						DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
215						.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
216						.funcs = &hpd_irq_info_funcs\
217}
218
219#define hpd_rx_int_entry(reg_num)\
220		[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
221				IRQ_REG_ENTRY(HPD, reg_num,\
222						DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
223						DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
224						.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
225						.funcs = &hpd_rx_irq_info_funcs\
226}
227#define pflip_int_entry(reg_num)\
228		[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
229				IRQ_REG_ENTRY(HUBPREQ, reg_num,\
230						DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
231						DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
232						.funcs = &pflip_irq_info_funcs\
233}
234
235/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
236 * of DCE's DC_IRQ_SOURCE_VUPDATEx.
237 */
238#define vupdate_no_lock_int_entry(reg_num)\
239	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
240		IRQ_REG_ENTRY(OTG, reg_num,\
241			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
242			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
243		.funcs = &vupdate_no_lock_irq_info_funcs\
244	}
245
246#define vblank_int_entry(reg_num)\
247	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
248		IRQ_REG_ENTRY(OTG, reg_num,\
249			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
250			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
251		.funcs = &vblank_irq_info_funcs\
252	}
253
254#define vline0_int_entry(reg_num)\
255	[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
256		IRQ_REG_ENTRY(OTG, reg_num,\
257			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
258			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
259		.funcs = &vline0_irq_info_funcs\
260	}
261
262#define dummy_irq_entry() { .funcs = &dummy_irq_info_funcs }
263
264#define i2c_int_entry(reg_num) \
265		[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
266
267#define dp_sink_int_entry(reg_num) \
268		[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
269
270#define gpio_pad_int_entry(reg_num) \
271		[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
272
273#define dc_underflow_int_entry(reg_num) \
274		[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
275
276static struct irq_source_info_funcs dummy_irq_info_funcs = {
277		.set = dal_irq_service_dummy_set,
278		.ack = dal_irq_service_dummy_ack
279};
280
281static const struct irq_source_info irq_source_info_dcn302[DAL_IRQ_SOURCES_NUMBER] = {
282		[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
283		hpd_int_entry(0),
284		hpd_int_entry(1),
285		hpd_int_entry(2),
286		hpd_int_entry(3),
287		hpd_int_entry(4),
288		hpd_rx_int_entry(0),
289		hpd_rx_int_entry(1),
290		hpd_rx_int_entry(2),
291		hpd_rx_int_entry(3),
292		hpd_rx_int_entry(4),
293		i2c_int_entry(1),
294		i2c_int_entry(2),
295		i2c_int_entry(3),
296		i2c_int_entry(4),
297		i2c_int_entry(5),
298		dp_sink_int_entry(1),
299		dp_sink_int_entry(2),
300		dp_sink_int_entry(3),
301		dp_sink_int_entry(4),
302		dp_sink_int_entry(5),
303		[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
304		pflip_int_entry(0),
305		pflip_int_entry(1),
306		pflip_int_entry(2),
307		pflip_int_entry(3),
308		pflip_int_entry(4),
309		[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
310		gpio_pad_int_entry(0),
311		gpio_pad_int_entry(1),
312		gpio_pad_int_entry(2),
313		gpio_pad_int_entry(3),
314		gpio_pad_int_entry(4),
315		gpio_pad_int_entry(5),
316		gpio_pad_int_entry(6),
317		gpio_pad_int_entry(7),
318		gpio_pad_int_entry(8),
319		gpio_pad_int_entry(9),
320		gpio_pad_int_entry(10),
321		gpio_pad_int_entry(11),
322		gpio_pad_int_entry(12),
323		gpio_pad_int_entry(13),
324		gpio_pad_int_entry(14),
325		gpio_pad_int_entry(15),
326		gpio_pad_int_entry(16),
327		gpio_pad_int_entry(17),
328		gpio_pad_int_entry(18),
329		gpio_pad_int_entry(19),
330		gpio_pad_int_entry(20),
331		gpio_pad_int_entry(21),
332		gpio_pad_int_entry(22),
333		gpio_pad_int_entry(23),
334		gpio_pad_int_entry(24),
335		gpio_pad_int_entry(25),
336		gpio_pad_int_entry(26),
337		gpio_pad_int_entry(27),
338		gpio_pad_int_entry(28),
339		gpio_pad_int_entry(29),
340		gpio_pad_int_entry(30),
341		dc_underflow_int_entry(1),
342		dc_underflow_int_entry(2),
343		dc_underflow_int_entry(3),
344		dc_underflow_int_entry(4),
345		dc_underflow_int_entry(5),
346		[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
347		[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
348		vupdate_no_lock_int_entry(0),
349		vupdate_no_lock_int_entry(1),
350		vupdate_no_lock_int_entry(2),
351		vupdate_no_lock_int_entry(3),
352		vupdate_no_lock_int_entry(4),
353		vblank_int_entry(0),
354		vblank_int_entry(1),
355		vblank_int_entry(2),
356		vblank_int_entry(3),
357		vblank_int_entry(4),
358		vline0_int_entry(0),
359		vline0_int_entry(1),
360		vline0_int_entry(2),
361		vline0_int_entry(3),
362		vline0_int_entry(4),
363		dmub_trace_int_entry(),
364};
365
366static const struct irq_service_funcs irq_service_funcs_dcn302 = {
367		.to_dal_irq_source = to_dal_irq_source_dcn302
368};
369
370static void dcn302_irq_construct(struct irq_service *irq_service, struct irq_service_init_data *init_data)
371{
372	dal_irq_service_construct(irq_service, init_data);
373
374	irq_service->info = irq_source_info_dcn302;
375	irq_service->funcs = &irq_service_funcs_dcn302;
376}
377
378struct irq_service *dal_irq_service_dcn302_create(struct irq_service_init_data *init_data)
379{
380	struct irq_service *irq_service = kzalloc(sizeof(*irq_service), GFP_KERNEL);
381
382	if (!irq_service)
383		return NULL;
384
385	dcn302_irq_construct(irq_service, init_data);
386	return irq_service;
387}