irq_service_dcn30.c

  1/*
  2 * Copyright 2020 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 19 * OTHER DEALINGS IN THE SOFTWARE.
 20 *
 21 * Authors: AMD
 22 *
 23 */
 24
 25#include "dm_services.h"
 26
 27#include "include/logger_interface.h"
 28
 29#include "../dce110/irq_service_dce110.h"
 30
 31
 32#include "sienna_cichlid_ip_offset.h"
 33#include "dcn/dcn_3_0_0_offset.h"
 34#include "dcn/dcn_3_0_0_sh_mask.h"
 35
 36#include "nbio/nbio_7_4_offset.h"
 37
 38#include "dpcs/dpcs_3_0_0_offset.h"
 39#include "dpcs/dpcs_3_0_0_sh_mask.h"
 40
 41#include "mmhub/mmhub_2_0_0_offset.h"
 42#include "mmhub/mmhub_2_0_0_sh_mask.h"
 43
 44#include "irq_service_dcn30.h"
 45
 46#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
 47
 48static enum dc_irq_source to_dal_irq_source_dcn30(
 49		struct irq_service *irq_service,
 50		uint32_t src_id,
 51		uint32_t ext_id)
 52{
 53	switch (src_id) {
 54	case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
 55		return DC_IRQ_SOURCE_VBLANK1;
 56	case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
 57		return DC_IRQ_SOURCE_VBLANK2;
 58	case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
 59		return DC_IRQ_SOURCE_VBLANK3;
 60	case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
 61		return DC_IRQ_SOURCE_VBLANK4;
 62	case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
 63		return DC_IRQ_SOURCE_VBLANK5;
 64	case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
 65		return DC_IRQ_SOURCE_VBLANK6;
 66	case DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT:
 67		return DC_IRQ_SOURCE_DMCUB_OUTBOX0;
 68	case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
 69		return DC_IRQ_SOURCE_DC1_VLINE0;
 70	case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
 71		return DC_IRQ_SOURCE_DC2_VLINE0;
 72	case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
 73		return DC_IRQ_SOURCE_DC3_VLINE0;
 74	case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
 75		return DC_IRQ_SOURCE_DC4_VLINE0;
 76	case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
 77		return DC_IRQ_SOURCE_DC5_VLINE0;
 78	case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
 79		return DC_IRQ_SOURCE_DC6_VLINE0;
 80	case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
 81		return DC_IRQ_SOURCE_PFLIP1;
 82	case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
 83		return DC_IRQ_SOURCE_PFLIP2;
 84	case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
 85		return DC_IRQ_SOURCE_PFLIP3;
 86	case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
 87		return DC_IRQ_SOURCE_PFLIP4;
 88	case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
 89		return DC_IRQ_SOURCE_PFLIP5;
 90	case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
 91		return DC_IRQ_SOURCE_PFLIP6;
 92	case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 93		return DC_IRQ_SOURCE_VUPDATE1;
 94	case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 95		return DC_IRQ_SOURCE_VUPDATE2;
 96	case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 97		return DC_IRQ_SOURCE_VUPDATE3;
 98	case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 99		return DC_IRQ_SOURCE_VUPDATE4;
100	case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
101		return DC_IRQ_SOURCE_VUPDATE5;
102	case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
103		return DC_IRQ_SOURCE_VUPDATE6;
104
105	case DCN_1_0__SRCID__DC_HPD1_INT:
106		/* generic src_id for all HPD and HPDRX interrupts */
107		switch (ext_id) {
108		case DCN_1_0__CTXID__DC_HPD1_INT:
109			return DC_IRQ_SOURCE_HPD1;
110		case DCN_1_0__CTXID__DC_HPD2_INT:
111			return DC_IRQ_SOURCE_HPD2;
112		case DCN_1_0__CTXID__DC_HPD3_INT:
113			return DC_IRQ_SOURCE_HPD3;
114		case DCN_1_0__CTXID__DC_HPD4_INT:
115			return DC_IRQ_SOURCE_HPD4;
116		case DCN_1_0__CTXID__DC_HPD5_INT:
117			return DC_IRQ_SOURCE_HPD5;
118		case DCN_1_0__CTXID__DC_HPD6_INT:
119			return DC_IRQ_SOURCE_HPD6;
120		case DCN_1_0__CTXID__DC_HPD1_RX_INT:
121			return DC_IRQ_SOURCE_HPD1RX;
122		case DCN_1_0__CTXID__DC_HPD2_RX_INT:
123			return DC_IRQ_SOURCE_HPD2RX;
124		case DCN_1_0__CTXID__DC_HPD3_RX_INT:
125			return DC_IRQ_SOURCE_HPD3RX;
126		case DCN_1_0__CTXID__DC_HPD4_RX_INT:
127			return DC_IRQ_SOURCE_HPD4RX;
128		case DCN_1_0__CTXID__DC_HPD5_RX_INT:
129			return DC_IRQ_SOURCE_HPD5RX;
130		case DCN_1_0__CTXID__DC_HPD6_RX_INT:
131			return DC_IRQ_SOURCE_HPD6RX;
132		default:
133			return DC_IRQ_SOURCE_INVALID;
134		}
135		break;
136
137	default:
138		return DC_IRQ_SOURCE_INVALID;
139	}
140}
141
142static struct irq_source_info_funcs hpd_irq_info_funcs  = {
143	.set = NULL,
144	.ack = hpd0_ack
145};
146
147static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
148	.set = NULL,
149	.ack = NULL
150};
151
152static struct irq_source_info_funcs pflip_irq_info_funcs = {
153	.set = NULL,
154	.ack = NULL
155};
156
157static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
158	.set = NULL,
159	.ack = NULL
160};
161
162static struct irq_source_info_funcs vblank_irq_info_funcs = {
163	.set = NULL,
164	.ack = NULL
165};
166
167static struct irq_source_info_funcs dmub_trace_irq_info_funcs = {
168	.set = NULL,
169	.ack = NULL
170};
171
172static struct irq_source_info_funcs vline0_irq_info_funcs = {
173	.set = NULL,
174	.ack = NULL
175};
176
177#undef BASE_INNER
178#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
179
180/* compile time expand base address. */
181#define BASE(seg) \
182	BASE_INNER(seg)
183
184
185#define SRI(reg_name, block, id)\
186	BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
187			mm ## block ## id ## _ ## reg_name
188
189#define SRI_DMUB(reg_name)\
190	BASE(mm ## reg_name ## _BASE_IDX) + \
191			mm ## reg_name
192
193#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
194	.enable_reg = SRI(reg1, block, reg_num),\
195	.enable_mask = \
196		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
197	.enable_value = {\
198		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
199		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
200	},\
201	.ack_reg = SRI(reg2, block, reg_num),\
202	.ack_mask = \
203		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
204	.ack_value = \
205		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
206
207#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
208	.enable_reg = SRI_DMUB(reg1),\
209	.enable_mask = \
210		reg1 ## __ ## mask1 ## _MASK,\
211	.enable_value = {\
212		reg1 ## __ ## mask1 ## _MASK,\
213		~reg1 ## __ ## mask1 ## _MASK \
214	},\
215	.ack_reg = SRI_DMUB(reg2),\
216	.ack_mask = \
217		reg2 ## __ ## mask2 ## _MASK,\
218	.ack_value = \
219		reg2 ## __ ## mask2 ## _MASK \
220
221#define hpd_int_entry(reg_num)\
222	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
223		IRQ_REG_ENTRY(HPD, reg_num,\
224			DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
225			DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
226		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
227		.funcs = &hpd_irq_info_funcs\
228	}
229
230#define hpd_rx_int_entry(reg_num)\
231	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
232		IRQ_REG_ENTRY(HPD, reg_num,\
233			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
234			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
235		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
236		.funcs = &hpd_rx_irq_info_funcs\
237	}
238#define pflip_int_entry(reg_num)\
239	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
240		IRQ_REG_ENTRY(HUBPREQ, reg_num,\
241			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
242			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
243		.funcs = &pflip_irq_info_funcs\
244	}
245
246/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
247 * of DCE's DC_IRQ_SOURCE_VUPDATEx.
248 */
249#define vupdate_no_lock_int_entry(reg_num)\
250	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
251		IRQ_REG_ENTRY(OTG, reg_num,\
252			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
253			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
254		.funcs = &vupdate_no_lock_irq_info_funcs\
255	}
256
257#define vblank_int_entry(reg_num)\
258	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
259		IRQ_REG_ENTRY(OTG, reg_num,\
260			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
261			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
262		.funcs = &vblank_irq_info_funcs\
263	}
264
265#define dmub_trace_int_entry()\
266	[DC_IRQ_SOURCE_DMCUB_OUTBOX0] = {\
267		IRQ_REG_ENTRY_DMUB(DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX0_READY_INT_EN,\
268			DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX0_READY_INT_ACK),\
269		.funcs = &dmub_trace_irq_info_funcs\
270	}
271
272#define vline0_int_entry(reg_num)\
273	[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
274		IRQ_REG_ENTRY(OTG, reg_num,\
275			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
276			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
277		.funcs = &vline0_irq_info_funcs\
278	}
279
280#define dummy_irq_entry() \
281	{\
282		.funcs = &dummy_irq_info_funcs\
283	}
284
285#define i2c_int_entry(reg_num) \
286	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
287
288#define dp_sink_int_entry(reg_num) \
289	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
290
291#define gpio_pad_int_entry(reg_num) \
292	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
293
294#define dc_underflow_int_entry(reg_num) \
295	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
296
297static struct irq_source_info_funcs dummy_irq_info_funcs = {
298	.set = dal_irq_service_dummy_set,
299	.ack = dal_irq_service_dummy_ack
300};
301
302static const struct irq_source_info
303irq_source_info_dcn30[DAL_IRQ_SOURCES_NUMBER] = {
304	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
305	hpd_int_entry(0),
306	hpd_int_entry(1),
307	hpd_int_entry(2),
308	hpd_int_entry(3),
309	hpd_int_entry(4),
310	hpd_int_entry(5),
311	hpd_rx_int_entry(0),
312	hpd_rx_int_entry(1),
313	hpd_rx_int_entry(2),
314	hpd_rx_int_entry(3),
315	hpd_rx_int_entry(4),
316	hpd_rx_int_entry(5),
317	i2c_int_entry(1),
318	i2c_int_entry(2),
319	i2c_int_entry(3),
320	i2c_int_entry(4),
321	i2c_int_entry(5),
322	i2c_int_entry(6),
323	dp_sink_int_entry(1),
324	dp_sink_int_entry(2),
325	dp_sink_int_entry(3),
326	dp_sink_int_entry(4),
327	dp_sink_int_entry(5),
328	dp_sink_int_entry(6),
329	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
330	pflip_int_entry(0),
331	pflip_int_entry(1),
332	pflip_int_entry(2),
333	pflip_int_entry(3),
334	pflip_int_entry(4),
335	pflip_int_entry(5),
336	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
337	gpio_pad_int_entry(0),
338	gpio_pad_int_entry(1),
339	gpio_pad_int_entry(2),
340	gpio_pad_int_entry(3),
341	gpio_pad_int_entry(4),
342	gpio_pad_int_entry(5),
343	gpio_pad_int_entry(6),
344	gpio_pad_int_entry(7),
345	gpio_pad_int_entry(8),
346	gpio_pad_int_entry(9),
347	gpio_pad_int_entry(10),
348	gpio_pad_int_entry(11),
349	gpio_pad_int_entry(12),
350	gpio_pad_int_entry(13),
351	gpio_pad_int_entry(14),
352	gpio_pad_int_entry(15),
353	gpio_pad_int_entry(16),
354	gpio_pad_int_entry(17),
355	gpio_pad_int_entry(18),
356	gpio_pad_int_entry(19),
357	gpio_pad_int_entry(20),
358	gpio_pad_int_entry(21),
359	gpio_pad_int_entry(22),
360	gpio_pad_int_entry(23),
361	gpio_pad_int_entry(24),
362	gpio_pad_int_entry(25),
363	gpio_pad_int_entry(26),
364	gpio_pad_int_entry(27),
365	gpio_pad_int_entry(28),
366	gpio_pad_int_entry(29),
367	gpio_pad_int_entry(30),
368	dc_underflow_int_entry(1),
369	dc_underflow_int_entry(2),
370	dc_underflow_int_entry(3),
371	dc_underflow_int_entry(4),
372	dc_underflow_int_entry(5),
373	dc_underflow_int_entry(6),
374	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
375	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
376	vupdate_no_lock_int_entry(0),
377	vupdate_no_lock_int_entry(1),
378	vupdate_no_lock_int_entry(2),
379	vupdate_no_lock_int_entry(3),
380	vupdate_no_lock_int_entry(4),
381	vupdate_no_lock_int_entry(5),
382	vblank_int_entry(0),
383	vblank_int_entry(1),
384	vblank_int_entry(2),
385	vblank_int_entry(3),
386	vblank_int_entry(4),
387	vblank_int_entry(5),
388	vline0_int_entry(0),
389	vline0_int_entry(1),
390	vline0_int_entry(2),
391	vline0_int_entry(3),
392	vline0_int_entry(4),
393	vline0_int_entry(5),
394	dmub_trace_int_entry(),
395};
396
397static const struct irq_service_funcs irq_service_funcs_dcn30 = {
398		.to_dal_irq_source = to_dal_irq_source_dcn30
399};
400
401static void dcn30_irq_construct(
402	struct irq_service *irq_service,
403	struct irq_service_init_data *init_data)
404{
405	dal_irq_service_construct(irq_service, init_data);
406
407	irq_service->info = irq_source_info_dcn30;
408	irq_service->funcs = &irq_service_funcs_dcn30;
409}
410
411struct irq_service *dal_irq_service_dcn30_create(
412	struct irq_service_init_data *init_data)
413{
414	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
415						  GFP_KERNEL);
416
417	if (!irq_service)
418		return NULL;
419
420	dcn30_irq_construct(irq_service, init_data);
421	return irq_service;
422}