irq_service_dcn21.c

  1/*
  2 * Copyright 2018 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#include "dm_services.h"
 27
 28#include "include/logger_interface.h"
 29
 30#include "../dce110/irq_service_dce110.h"
 31
 32#include "dcn/dcn_2_1_0_offset.h"
 33#include "dcn/dcn_2_1_0_sh_mask.h"
 34#include "renoir_ip_offset.h"
 35
 36
 37#include "irq_service_dcn21.h"
 38
 39#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
 40
 41static enum dc_irq_source to_dal_irq_source_dcn21(struct irq_service *irq_service,
 42						  uint32_t src_id,
 43						  uint32_t ext_id)
 44{
 45	switch (src_id) {
 46	case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
 47		return DC_IRQ_SOURCE_VBLANK1;
 48	case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
 49		return DC_IRQ_SOURCE_VBLANK2;
 50	case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
 51		return DC_IRQ_SOURCE_VBLANK3;
 52	case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
 53		return DC_IRQ_SOURCE_VBLANK4;
 54	case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
 55		return DC_IRQ_SOURCE_VBLANK5;
 56	case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
 57		return DC_IRQ_SOURCE_VBLANK6;
 58	case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
 59		return DC_IRQ_SOURCE_DMCUB_OUTBOX;
 60	case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
 61		return DC_IRQ_SOURCE_DC1_VLINE0;
 62	case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
 63		return DC_IRQ_SOURCE_DC2_VLINE0;
 64	case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
 65		return DC_IRQ_SOURCE_DC3_VLINE0;
 66	case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
 67		return DC_IRQ_SOURCE_DC4_VLINE0;
 68	case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
 69		return DC_IRQ_SOURCE_DC5_VLINE0;
 70	case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
 71		return DC_IRQ_SOURCE_DC6_VLINE0;
 72	case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
 73		return DC_IRQ_SOURCE_PFLIP1;
 74	case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
 75		return DC_IRQ_SOURCE_PFLIP2;
 76	case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
 77		return DC_IRQ_SOURCE_PFLIP3;
 78	case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
 79		return DC_IRQ_SOURCE_PFLIP4;
 80	case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
 81		return DC_IRQ_SOURCE_PFLIP5;
 82	case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
 83		return DC_IRQ_SOURCE_PFLIP6;
 84	case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 85		return DC_IRQ_SOURCE_VUPDATE1;
 86	case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 87		return DC_IRQ_SOURCE_VUPDATE2;
 88	case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 89		return DC_IRQ_SOURCE_VUPDATE3;
 90	case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 91		return DC_IRQ_SOURCE_VUPDATE4;
 92	case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 93		return DC_IRQ_SOURCE_VUPDATE5;
 94	case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 95		return DC_IRQ_SOURCE_VUPDATE6;
 96
 97	case DCN_1_0__SRCID__DC_HPD1_INT:
 98		/* generic src_id for all HPD and HPDRX interrupts */
 99		switch (ext_id) {
100		case DCN_1_0__CTXID__DC_HPD1_INT:
101			return DC_IRQ_SOURCE_HPD1;
102		case DCN_1_0__CTXID__DC_HPD2_INT:
103			return DC_IRQ_SOURCE_HPD2;
104		case DCN_1_0__CTXID__DC_HPD3_INT:
105			return DC_IRQ_SOURCE_HPD3;
106		case DCN_1_0__CTXID__DC_HPD4_INT:
107			return DC_IRQ_SOURCE_HPD4;
108		case DCN_1_0__CTXID__DC_HPD5_INT:
109			return DC_IRQ_SOURCE_HPD5;
110		case DCN_1_0__CTXID__DC_HPD6_INT:
111			return DC_IRQ_SOURCE_HPD6;
112		case DCN_1_0__CTXID__DC_HPD1_RX_INT:
113			return DC_IRQ_SOURCE_HPD1RX;
114		case DCN_1_0__CTXID__DC_HPD2_RX_INT:
115			return DC_IRQ_SOURCE_HPD2RX;
116		case DCN_1_0__CTXID__DC_HPD3_RX_INT:
117			return DC_IRQ_SOURCE_HPD3RX;
118		case DCN_1_0__CTXID__DC_HPD4_RX_INT:
119			return DC_IRQ_SOURCE_HPD4RX;
120		case DCN_1_0__CTXID__DC_HPD5_RX_INT:
121			return DC_IRQ_SOURCE_HPD5RX;
122		case DCN_1_0__CTXID__DC_HPD6_RX_INT:
123			return DC_IRQ_SOURCE_HPD6RX;
124		default:
125			return DC_IRQ_SOURCE_INVALID;
126		}
127		break;
128
129	default:
130		break;
131	}
132	return DC_IRQ_SOURCE_INVALID;
133}
134
135static struct irq_source_info_funcs hpd_irq_info_funcs  = {
136	.set = NULL,
137	.ack = hpd0_ack
138};
139
140static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
141	.set = NULL,
142	.ack = NULL
143};
144
145static struct irq_source_info_funcs pflip_irq_info_funcs = {
146	.set = NULL,
147	.ack = NULL
148};
149
150static struct irq_source_info_funcs vblank_irq_info_funcs = {
151	.set = NULL,
152	.ack = NULL
153};
154
155static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
156	.set = NULL,
157	.ack = NULL
158};
159
160static struct irq_source_info_funcs dmub_outbox_irq_info_funcs = {
161	.set = NULL,
162	.ack = NULL
163};
164
165static struct irq_source_info_funcs vline0_irq_info_funcs = {
166	.set = NULL,
167	.ack = NULL
168};
169
170#undef BASE_INNER
171#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
172
173/* compile time expand base address. */
174#define BASE(seg) \
175	BASE_INNER(seg)
176
177
178#define SRI(reg_name, block, id)\
179	BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
180			mm ## block ## id ## _ ## reg_name
181
182#define SRI_DMUB(reg_name)\
183	BASE(mm ## reg_name ## _BASE_IDX) + \
184			mm ## reg_name
185
186#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
187	.enable_reg = SRI(reg1, block, reg_num),\
188	.enable_mask = \
189		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
190	.enable_value = {\
191		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
192		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
193	},\
194	.ack_reg = SRI(reg2, block, reg_num),\
195	.ack_mask = \
196		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
197	.ack_value = \
198		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
199
200#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
201	.enable_reg = SRI_DMUB(reg1),\
202	.enable_mask = \
203		reg1 ## __ ## mask1 ## _MASK,\
204	.enable_value = {\
205		reg1 ## __ ## mask1 ## _MASK,\
206		~reg1 ## __ ## mask1 ## _MASK \
207	},\
208	.ack_reg = SRI_DMUB(reg2),\
209	.ack_mask = \
210		reg2 ## __ ## mask2 ## _MASK,\
211	.ack_value = \
212		reg2 ## __ ## mask2 ## _MASK \
213
214#define hpd_int_entry(reg_num)\
215	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
216		IRQ_REG_ENTRY(HPD, reg_num,\
217			DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
218			DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
219		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
220		.funcs = &hpd_irq_info_funcs\
221	}
222
223#define hpd_rx_int_entry(reg_num)\
224	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
225		IRQ_REG_ENTRY(HPD, reg_num,\
226			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
227			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
228		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
229		.funcs = &hpd_rx_irq_info_funcs\
230	}
231#define pflip_int_entry(reg_num)\
232	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
233		IRQ_REG_ENTRY(HUBPREQ, reg_num,\
234			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
235			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
236		.funcs = &pflip_irq_info_funcs\
237	}
238
239/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
240 * of DCE's DC_IRQ_SOURCE_VUPDATEx.
241 */
242#define vupdate_no_lock_int_entry(reg_num)\
243	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
244		IRQ_REG_ENTRY(OTG, reg_num,\
245			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
246			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
247		.funcs = &vupdate_no_lock_irq_info_funcs\
248	}
249
250#define vblank_int_entry(reg_num)\
251	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
252		IRQ_REG_ENTRY(OTG, reg_num,\
253			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
254			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
255		.funcs = &vblank_irq_info_funcs\
256	}
257
258#define vline0_int_entry(reg_num)\
259	[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
260		IRQ_REG_ENTRY(OTG, reg_num,\
261			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
262			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
263		.funcs = &vline0_irq_info_funcs\
264	}
265
266#define dmub_outbox_int_entry()\
267	[DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
268		IRQ_REG_ENTRY_DMUB(DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
269			DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
270		.funcs = &dmub_outbox_irq_info_funcs\
271	}
272
273#define dummy_irq_entry() \
274	{\
275		.funcs = &dummy_irq_info_funcs\
276	}
277
278#define i2c_int_entry(reg_num) \
279	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
280
281#define dp_sink_int_entry(reg_num) \
282	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
283
284#define gpio_pad_int_entry(reg_num) \
285	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
286
287#define dc_underflow_int_entry(reg_num) \
288	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
289
290static struct irq_source_info_funcs dummy_irq_info_funcs = {
291	.set = dal_irq_service_dummy_set,
292	.ack = dal_irq_service_dummy_ack
293};
294
295static const struct irq_source_info
296irq_source_info_dcn21[DAL_IRQ_SOURCES_NUMBER] = {
297	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
298	hpd_int_entry(0),
299	hpd_int_entry(1),
300	hpd_int_entry(2),
301	hpd_int_entry(3),
302	hpd_int_entry(4),
303	hpd_rx_int_entry(0),
304	hpd_rx_int_entry(1),
305	hpd_rx_int_entry(2),
306	hpd_rx_int_entry(3),
307	hpd_rx_int_entry(4),
308	i2c_int_entry(1),
309	i2c_int_entry(2),
310	i2c_int_entry(3),
311	i2c_int_entry(4),
312	i2c_int_entry(5),
313	i2c_int_entry(6),
314	dp_sink_int_entry(1),
315	dp_sink_int_entry(2),
316	dp_sink_int_entry(3),
317	dp_sink_int_entry(4),
318	dp_sink_int_entry(5),
319	dp_sink_int_entry(6),
320	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
321	pflip_int_entry(0),
322	pflip_int_entry(1),
323	pflip_int_entry(2),
324	pflip_int_entry(3),
325	[DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
326	[DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
327	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
328	gpio_pad_int_entry(0),
329	gpio_pad_int_entry(1),
330	gpio_pad_int_entry(2),
331	gpio_pad_int_entry(3),
332	gpio_pad_int_entry(4),
333	gpio_pad_int_entry(5),
334	gpio_pad_int_entry(6),
335	gpio_pad_int_entry(7),
336	gpio_pad_int_entry(8),
337	gpio_pad_int_entry(9),
338	gpio_pad_int_entry(10),
339	gpio_pad_int_entry(11),
340	gpio_pad_int_entry(12),
341	gpio_pad_int_entry(13),
342	gpio_pad_int_entry(14),
343	gpio_pad_int_entry(15),
344	gpio_pad_int_entry(16),
345	gpio_pad_int_entry(17),
346	gpio_pad_int_entry(18),
347	gpio_pad_int_entry(19),
348	gpio_pad_int_entry(20),
349	gpio_pad_int_entry(21),
350	gpio_pad_int_entry(22),
351	gpio_pad_int_entry(23),
352	gpio_pad_int_entry(24),
353	gpio_pad_int_entry(25),
354	gpio_pad_int_entry(26),
355	gpio_pad_int_entry(27),
356	gpio_pad_int_entry(28),
357	gpio_pad_int_entry(29),
358	gpio_pad_int_entry(30),
359	dc_underflow_int_entry(1),
360	dc_underflow_int_entry(2),
361	dc_underflow_int_entry(3),
362	dc_underflow_int_entry(4),
363	dc_underflow_int_entry(5),
364	dc_underflow_int_entry(6),
365	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
366	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
367	vupdate_no_lock_int_entry(0),
368	vupdate_no_lock_int_entry(1),
369	vupdate_no_lock_int_entry(2),
370	vupdate_no_lock_int_entry(3),
371	vupdate_no_lock_int_entry(4),
372	vupdate_no_lock_int_entry(5),
373	vblank_int_entry(0),
374	vblank_int_entry(1),
375	vblank_int_entry(2),
376	vblank_int_entry(3),
377	vblank_int_entry(4),
378	vblank_int_entry(5),
379	vline0_int_entry(0),
380	vline0_int_entry(1),
381	vline0_int_entry(2),
382	vline0_int_entry(3),
383	vline0_int_entry(4),
384	vline0_int_entry(5),
385	dmub_outbox_int_entry(),
386};
387
388static const struct irq_service_funcs irq_service_funcs_dcn21 = {
389		.to_dal_irq_source = to_dal_irq_source_dcn21
390};
391
392static void dcn21_irq_construct(
393	struct irq_service *irq_service,
394	struct irq_service_init_data *init_data)
395{
396	dal_irq_service_construct(irq_service, init_data);
397
398	irq_service->info = irq_source_info_dcn21;
399	irq_service->funcs = &irq_service_funcs_dcn21;
400}
401
402struct irq_service *dal_irq_service_dcn21_create(
403	struct irq_service_init_data *init_data)
404{
405	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
406						  GFP_KERNEL);
407
408	if (!irq_service)
409		return NULL;
410
411	dcn21_irq_construct(irq_service, init_data);
412	return irq_service;
413}