irq_service_dcn201.c

  1/*
  2 * Copyright 2022 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#include "dm_services.h"
 27
 28#include "include/logger_interface.h"
 29
 30#include "../dce110/irq_service_dce110.h"
 31#include "irq_service_dcn201.h"
 32
 33#include "dcn/dcn_2_0_1_offset.h"
 34#include "dcn/dcn_2_0_1_sh_mask.h"
 35
 36#include "cyan_skillfish_ip_offset.h"
 37#include "soc15_hw_ip.h"
 38#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
 39
 40static enum dc_irq_source to_dal_irq_source_dcn201(
 41		struct irq_service *irq_service,
 42		uint32_t src_id,
 43		uint32_t ext_id)
 44{
 45	switch (src_id) {
 46	case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
 47		return DC_IRQ_SOURCE_VBLANK1;
 48	case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
 49		return DC_IRQ_SOURCE_VBLANK2;
 50	case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
 51		return DC_IRQ_SOURCE_DC1_VLINE0;
 52	case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
 53		return DC_IRQ_SOURCE_DC2_VLINE0;
 54	case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
 55		return DC_IRQ_SOURCE_PFLIP1;
 56	case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
 57		return DC_IRQ_SOURCE_PFLIP2;
 58	case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 59		return DC_IRQ_SOURCE_VUPDATE1;
 60	case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 61		return DC_IRQ_SOURCE_VUPDATE2;
 62	case DCN_1_0__SRCID__DC_HPD1_INT:
 63		/* generic src_id for all HPD and HPDRX interrupts */
 64		switch (ext_id) {
 65		case DCN_1_0__CTXID__DC_HPD1_INT:
 66			return DC_IRQ_SOURCE_HPD1;
 67		case DCN_1_0__CTXID__DC_HPD2_INT:
 68			return DC_IRQ_SOURCE_HPD2;
 69		case DCN_1_0__CTXID__DC_HPD1_RX_INT:
 70			return DC_IRQ_SOURCE_HPD1RX;
 71		case DCN_1_0__CTXID__DC_HPD2_RX_INT:
 72			return DC_IRQ_SOURCE_HPD2RX;
 73		default:
 74			return DC_IRQ_SOURCE_INVALID;
 75		}
 76		break;
 77
 78	default:
 79		return DC_IRQ_SOURCE_INVALID;
 80	}
 81}
 82
 83static struct irq_source_info_funcs hpd_irq_info_funcs  = {
 84	.set = NULL,
 85	.ack = hpd0_ack
 86};
 87
 88static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
 89	.set = NULL,
 90	.ack = NULL
 91};
 92
 93static struct irq_source_info_funcs pflip_irq_info_funcs = {
 94	.set = NULL,
 95	.ack = NULL
 96};
 97
 98static struct irq_source_info_funcs vblank_irq_info_funcs = {
 99	.set = NULL,
100	.ack = NULL
101};
102
103static struct irq_source_info_funcs vline0_irq_info_funcs = {
104	.set = NULL,
105	.ack = NULL
106};
107static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
108	.set = NULL,
109	.ack = NULL
110};
111
112#undef BASE_INNER
113#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
114
115#define BASE(seg) BASE_INNER(seg)
116
117/* compile time expand base address. */
118#define BASE(seg) \
119	BASE_INNER(seg)
120
121#define SRI(reg_name, block, id)\
122	BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
123					mm ## block ## id ## _ ## reg_name
124
125#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
126	.enable_reg = SRI(reg1, block, reg_num),\
127	.enable_mask = \
128		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
129	.enable_value = {\
130		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
131		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
132	},\
133	.ack_reg = SRI(reg2, block, reg_num),\
134	.ack_mask = \
135		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
136	.ack_value = \
137		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
138
139#define hpd_int_entry(reg_num)\
140	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
141		IRQ_REG_ENTRY(HPD, reg_num,\
142			DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
143			DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
144		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
145		.funcs = &hpd_irq_info_funcs\
146	}
147
148#define hpd_rx_int_entry(reg_num)\
149	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
150		IRQ_REG_ENTRY(HPD, reg_num,\
151			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
152			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
153		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
154		.funcs = &hpd_rx_irq_info_funcs\
155	}
156#define pflip_int_entry(reg_num)\
157	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
158		IRQ_REG_ENTRY(HUBPREQ, reg_num,\
159			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
160			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
161		.funcs = &pflip_irq_info_funcs\
162	}
163
164#define vupdate_int_entry(reg_num)\
165	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
166		IRQ_REG_ENTRY(OTG, reg_num,\
167			OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\
168			OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\
169		.funcs = &vblank_irq_info_funcs\
170	}
171
172/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
173 * of DCE's DC_IRQ_SOURCE_VUPDATEx.
174 */
175#define vupdate_no_lock_int_entry(reg_num)\
176	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
177		IRQ_REG_ENTRY(OTG, reg_num,\
178			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
179			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
180		.funcs = &vupdate_no_lock_irq_info_funcs\
181	}
182#define vblank_int_entry(reg_num)\
183	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
184		IRQ_REG_ENTRY(OTG, reg_num,\
185			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
186			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
187		.funcs = &vblank_irq_info_funcs\
188	}
189
190#define vline0_int_entry(reg_num)\
191	[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
192		IRQ_REG_ENTRY(OTG, reg_num,\
193			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
194			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
195		.funcs = &vline0_irq_info_funcs\
196	}
197
198#define dummy_irq_entry() \
199	{\
200		.funcs = &dummy_irq_info_funcs\
201	}
202
203#define i2c_int_entry(reg_num) \
204	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
205
206#define dp_sink_int_entry(reg_num) \
207	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
208
209#define gpio_pad_int_entry(reg_num) \
210	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
211
212#define dc_underflow_int_entry(reg_num) \
213	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
214
215static struct irq_source_info_funcs dummy_irq_info_funcs = {
216	.set = dal_irq_service_dummy_set,
217	.ack = dal_irq_service_dummy_ack
218};
219
220static const struct irq_source_info
221irq_source_info_dcn201[DAL_IRQ_SOURCES_NUMBER] = {
222	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
223	hpd_int_entry(0),
224	hpd_int_entry(1),
225	dummy_irq_entry(),
226	dummy_irq_entry(),
227	dummy_irq_entry(),
228	dummy_irq_entry(),
229	hpd_rx_int_entry(0),
230	hpd_rx_int_entry(1),
231	dummy_irq_entry(),
232	dummy_irq_entry(),
233	dummy_irq_entry(),
234	dummy_irq_entry(),
235	i2c_int_entry(1),
236	i2c_int_entry(2),
237	dummy_irq_entry(),
238	dummy_irq_entry(),
239	dummy_irq_entry(),
240	dummy_irq_entry(),
241	dp_sink_int_entry(1),
242	dp_sink_int_entry(2),
243	dummy_irq_entry(),
244	dummy_irq_entry(),
245	dummy_irq_entry(),
246	dummy_irq_entry(),
247	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
248	pflip_int_entry(0),
249	pflip_int_entry(1),
250	pflip_int_entry(2),
251	pflip_int_entry(3),
252	[DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
253	[DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
254	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
255	gpio_pad_int_entry(0),
256	gpio_pad_int_entry(1),
257	gpio_pad_int_entry(2),
258	gpio_pad_int_entry(3),
259	gpio_pad_int_entry(4),
260	gpio_pad_int_entry(5),
261	gpio_pad_int_entry(6),
262	gpio_pad_int_entry(7),
263	gpio_pad_int_entry(8),
264	gpio_pad_int_entry(9),
265	gpio_pad_int_entry(10),
266	gpio_pad_int_entry(11),
267	gpio_pad_int_entry(12),
268	gpio_pad_int_entry(13),
269	gpio_pad_int_entry(14),
270	gpio_pad_int_entry(15),
271	gpio_pad_int_entry(16),
272	gpio_pad_int_entry(17),
273	gpio_pad_int_entry(18),
274	gpio_pad_int_entry(19),
275	gpio_pad_int_entry(20),
276	gpio_pad_int_entry(21),
277	gpio_pad_int_entry(22),
278	gpio_pad_int_entry(23),
279	gpio_pad_int_entry(24),
280	gpio_pad_int_entry(25),
281	gpio_pad_int_entry(26),
282	gpio_pad_int_entry(27),
283	gpio_pad_int_entry(28),
284	gpio_pad_int_entry(29),
285	gpio_pad_int_entry(30),
286	dc_underflow_int_entry(1),
287	dc_underflow_int_entry(2),
288	dummy_irq_entry(),
289	dummy_irq_entry(),
290	dummy_irq_entry(),
291	dummy_irq_entry(),
292	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
293	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
294	vupdate_no_lock_int_entry(0),
295	vupdate_no_lock_int_entry(1),
296	dummy_irq_entry(),
297	dummy_irq_entry(),
298	dummy_irq_entry(),
299	dummy_irq_entry(),
300	vblank_int_entry(0),
301	vblank_int_entry(1),
302	dummy_irq_entry(),
303	dummy_irq_entry(),
304	dummy_irq_entry(),
305	dummy_irq_entry(),
306	vline0_int_entry(0),
307	vline0_int_entry(1),
308	dummy_irq_entry(),
309	dummy_irq_entry(),
310	dummy_irq_entry(),
311	dummy_irq_entry(),
312};
313
314static const struct irq_service_funcs irq_service_funcs_dcn201 = {
315		.to_dal_irq_source = to_dal_irq_source_dcn201
316};
317
318static void dcn201_irq_construct(
319	struct irq_service *irq_service,
320	struct irq_service_init_data *init_data)
321{
322	dal_irq_service_construct(irq_service, init_data);
323
324	irq_service->info = irq_source_info_dcn201;
325	irq_service->funcs = &irq_service_funcs_dcn201;
326}
327
328struct irq_service *dal_irq_service_dcn201_create(
329	struct irq_service_init_data *init_data)
330{
331	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
332						  GFP_KERNEL);
333
334	if (!irq_service)
335		return NULL;
336
337	dcn201_irq_construct(irq_service, init_data);
338	return irq_service;
339}