irq_service_dcn20.c

  1/*
  2 * Copyright 2018 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#include "dm_services.h"
 27
 28#include "include/logger_interface.h"
 29
 30#include "../dce110/irq_service_dce110.h"
 31
 32#include "dcn/dcn_2_0_0_offset.h"
 33#include "dcn/dcn_2_0_0_sh_mask.h"
 34#include "navi10_ip_offset.h"
 35
 36
 37#include "irq_service_dcn20.h"
 38
 39#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
 40
 41static enum dc_irq_source to_dal_irq_source_dcn20(
 42		struct irq_service *irq_service,
 43		uint32_t src_id,
 44		uint32_t ext_id)
 45{
 46	switch (src_id) {
 47	case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
 48		return DC_IRQ_SOURCE_VBLANK1;
 49	case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
 50		return DC_IRQ_SOURCE_VBLANK2;
 51	case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
 52		return DC_IRQ_SOURCE_VBLANK3;
 53	case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
 54		return DC_IRQ_SOURCE_VBLANK4;
 55	case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
 56		return DC_IRQ_SOURCE_VBLANK5;
 57	case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
 58		return DC_IRQ_SOURCE_VBLANK6;
 59	case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
 60		return DC_IRQ_SOURCE_DC1_VLINE0;
 61	case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
 62		return DC_IRQ_SOURCE_DC2_VLINE0;
 63	case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
 64		return DC_IRQ_SOURCE_DC3_VLINE0;
 65	case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
 66		return DC_IRQ_SOURCE_DC4_VLINE0;
 67	case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
 68		return DC_IRQ_SOURCE_DC5_VLINE0;
 69	case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
 70		return DC_IRQ_SOURCE_DC6_VLINE0;
 71	case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
 72		return DC_IRQ_SOURCE_PFLIP1;
 73	case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
 74		return DC_IRQ_SOURCE_PFLIP2;
 75	case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
 76		return DC_IRQ_SOURCE_PFLIP3;
 77	case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
 78		return DC_IRQ_SOURCE_PFLIP4;
 79	case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
 80		return DC_IRQ_SOURCE_PFLIP5;
 81	case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
 82		return DC_IRQ_SOURCE_PFLIP6;
 83	case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 84		return DC_IRQ_SOURCE_VUPDATE1;
 85	case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 86		return DC_IRQ_SOURCE_VUPDATE2;
 87	case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 88		return DC_IRQ_SOURCE_VUPDATE3;
 89	case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 90		return DC_IRQ_SOURCE_VUPDATE4;
 91	case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 92		return DC_IRQ_SOURCE_VUPDATE5;
 93	case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
 94		return DC_IRQ_SOURCE_VUPDATE6;
 95
 96	case DCN_1_0__SRCID__DC_HPD1_INT:
 97		/* generic src_id for all HPD and HPDRX interrupts */
 98		switch (ext_id) {
 99		case DCN_1_0__CTXID__DC_HPD1_INT:
100			return DC_IRQ_SOURCE_HPD1;
101		case DCN_1_0__CTXID__DC_HPD2_INT:
102			return DC_IRQ_SOURCE_HPD2;
103		case DCN_1_0__CTXID__DC_HPD3_INT:
104			return DC_IRQ_SOURCE_HPD3;
105		case DCN_1_0__CTXID__DC_HPD4_INT:
106			return DC_IRQ_SOURCE_HPD4;
107		case DCN_1_0__CTXID__DC_HPD5_INT:
108			return DC_IRQ_SOURCE_HPD5;
109		case DCN_1_0__CTXID__DC_HPD6_INT:
110			return DC_IRQ_SOURCE_HPD6;
111		case DCN_1_0__CTXID__DC_HPD1_RX_INT:
112			return DC_IRQ_SOURCE_HPD1RX;
113		case DCN_1_0__CTXID__DC_HPD2_RX_INT:
114			return DC_IRQ_SOURCE_HPD2RX;
115		case DCN_1_0__CTXID__DC_HPD3_RX_INT:
116			return DC_IRQ_SOURCE_HPD3RX;
117		case DCN_1_0__CTXID__DC_HPD4_RX_INT:
118			return DC_IRQ_SOURCE_HPD4RX;
119		case DCN_1_0__CTXID__DC_HPD5_RX_INT:
120			return DC_IRQ_SOURCE_HPD5RX;
121		case DCN_1_0__CTXID__DC_HPD6_RX_INT:
122			return DC_IRQ_SOURCE_HPD6RX;
123		default:
124			return DC_IRQ_SOURCE_INVALID;
125		}
126		break;
127
128	default:
129		return DC_IRQ_SOURCE_INVALID;
130	}
131}
132
133static struct irq_source_info_funcs hpd_irq_info_funcs  = {
134	.set = NULL,
135	.ack = hpd0_ack
136};
137
138static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
139	.set = NULL,
140	.ack = NULL
141};
142
143static struct irq_source_info_funcs pflip_irq_info_funcs = {
144	.set = NULL,
145	.ack = NULL
146};
147
148static struct irq_source_info_funcs vblank_irq_info_funcs = {
149	.set = NULL,
150	.ack = NULL
151};
152
153static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
154	.set = NULL,
155	.ack = NULL
156};
157
158static struct irq_source_info_funcs vline0_irq_info_funcs = {
159	.set = NULL,
160	.ack = NULL
161};
162
163#undef BASE_INNER
164#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
165
166/* compile time expand base address. */
167#define BASE(seg) \
168	BASE_INNER(seg)
169
170
171#define SRI(reg_name, block, id)\
172	BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
173			mm ## block ## id ## _ ## reg_name
174
175
176#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
177	.enable_reg = SRI(reg1, block, reg_num),\
178	.enable_mask = \
179		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
180	.enable_value = {\
181		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
182		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
183	},\
184	.ack_reg = SRI(reg2, block, reg_num),\
185	.ack_mask = \
186		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
187	.ack_value = \
188		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
189
190
191
192#define hpd_int_entry(reg_num)\
193	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
194		IRQ_REG_ENTRY(HPD, reg_num,\
195			DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
196			DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
197		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
198		.funcs = &hpd_irq_info_funcs\
199	}
200
201#define hpd_rx_int_entry(reg_num)\
202	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
203		IRQ_REG_ENTRY(HPD, reg_num,\
204			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
205			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
206		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
207		.funcs = &hpd_rx_irq_info_funcs\
208	}
209#define pflip_int_entry(reg_num)\
210	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
211		IRQ_REG_ENTRY(HUBPREQ, reg_num,\
212			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
213			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
214		.funcs = &pflip_irq_info_funcs\
215	}
216
217/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
218 * of DCE's DC_IRQ_SOURCE_VUPDATEx.
219 */
220#define vupdate_no_lock_int_entry(reg_num)\
221	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
222		IRQ_REG_ENTRY(OTG, reg_num,\
223			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
224			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
225		.funcs = &vupdate_no_lock_irq_info_funcs\
226	}
227
228#define vblank_int_entry(reg_num)\
229	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
230		IRQ_REG_ENTRY(OTG, reg_num,\
231			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
232			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
233		.funcs = &vblank_irq_info_funcs\
234	}
235
236#define vline0_int_entry(reg_num)\
237	[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
238		IRQ_REG_ENTRY(OTG, reg_num,\
239			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
240			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
241		.funcs = &vline0_irq_info_funcs\
242	}
243
244#define dummy_irq_entry() \
245	{\
246		.funcs = &dummy_irq_info_funcs\
247	}
248
249#define i2c_int_entry(reg_num) \
250	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
251
252#define dp_sink_int_entry(reg_num) \
253	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
254
255#define gpio_pad_int_entry(reg_num) \
256	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
257
258#define dc_underflow_int_entry(reg_num) \
259	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
260
261static struct irq_source_info_funcs dummy_irq_info_funcs = {
262	.set = dal_irq_service_dummy_set,
263	.ack = dal_irq_service_dummy_ack
264};
265
266static const struct irq_source_info
267irq_source_info_dcn20[DAL_IRQ_SOURCES_NUMBER] = {
268	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
269	hpd_int_entry(0),
270	hpd_int_entry(1),
271	hpd_int_entry(2),
272	hpd_int_entry(3),
273	hpd_int_entry(4),
274	hpd_int_entry(5),
275	hpd_rx_int_entry(0),
276	hpd_rx_int_entry(1),
277	hpd_rx_int_entry(2),
278	hpd_rx_int_entry(3),
279	hpd_rx_int_entry(4),
280	hpd_rx_int_entry(5),
281	i2c_int_entry(1),
282	i2c_int_entry(2),
283	i2c_int_entry(3),
284	i2c_int_entry(4),
285	i2c_int_entry(5),
286	i2c_int_entry(6),
287	dp_sink_int_entry(1),
288	dp_sink_int_entry(2),
289	dp_sink_int_entry(3),
290	dp_sink_int_entry(4),
291	dp_sink_int_entry(5),
292	dp_sink_int_entry(6),
293	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
294	pflip_int_entry(0),
295	pflip_int_entry(1),
296	pflip_int_entry(2),
297	pflip_int_entry(3),
298	pflip_int_entry(4),
299	pflip_int_entry(5),
300	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
301	gpio_pad_int_entry(0),
302	gpio_pad_int_entry(1),
303	gpio_pad_int_entry(2),
304	gpio_pad_int_entry(3),
305	gpio_pad_int_entry(4),
306	gpio_pad_int_entry(5),
307	gpio_pad_int_entry(6),
308	gpio_pad_int_entry(7),
309	gpio_pad_int_entry(8),
310	gpio_pad_int_entry(9),
311	gpio_pad_int_entry(10),
312	gpio_pad_int_entry(11),
313	gpio_pad_int_entry(12),
314	gpio_pad_int_entry(13),
315	gpio_pad_int_entry(14),
316	gpio_pad_int_entry(15),
317	gpio_pad_int_entry(16),
318	gpio_pad_int_entry(17),
319	gpio_pad_int_entry(18),
320	gpio_pad_int_entry(19),
321	gpio_pad_int_entry(20),
322	gpio_pad_int_entry(21),
323	gpio_pad_int_entry(22),
324	gpio_pad_int_entry(23),
325	gpio_pad_int_entry(24),
326	gpio_pad_int_entry(25),
327	gpio_pad_int_entry(26),
328	gpio_pad_int_entry(27),
329	gpio_pad_int_entry(28),
330	gpio_pad_int_entry(29),
331	gpio_pad_int_entry(30),
332	dc_underflow_int_entry(1),
333	dc_underflow_int_entry(2),
334	dc_underflow_int_entry(3),
335	dc_underflow_int_entry(4),
336	dc_underflow_int_entry(5),
337	dc_underflow_int_entry(6),
338	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
339	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
340	vupdate_no_lock_int_entry(0),
341	vupdate_no_lock_int_entry(1),
342	vupdate_no_lock_int_entry(2),
343	vupdate_no_lock_int_entry(3),
344	vupdate_no_lock_int_entry(4),
345	vupdate_no_lock_int_entry(5),
346	vblank_int_entry(0),
347	vblank_int_entry(1),
348	vblank_int_entry(2),
349	vblank_int_entry(3),
350	vblank_int_entry(4),
351	vblank_int_entry(5),
352	vline0_int_entry(0),
353	vline0_int_entry(1),
354	vline0_int_entry(2),
355	vline0_int_entry(3),
356	vline0_int_entry(4),
357	vline0_int_entry(5),
358};
359
360static const struct irq_service_funcs irq_service_funcs_dcn20 = {
361		.to_dal_irq_source = to_dal_irq_source_dcn20
362};
363
364static void dcn20_irq_construct(
365	struct irq_service *irq_service,
366	struct irq_service_init_data *init_data)
367{
368	dal_irq_service_construct(irq_service, init_data);
369
370	irq_service->info = irq_source_info_dcn20;
371	irq_service->funcs = &irq_service_funcs_dcn20;
372}
373
374struct irq_service *dal_irq_service_dcn20_create(
375	struct irq_service_init_data *init_data)
376{
377	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
378						  GFP_KERNEL);
379
380	if (!irq_service)
381		return NULL;
382
383	dcn20_irq_construct(irq_service, init_data);
384	return irq_service;
385}