irq_service_dce80.c

  1/*
  2 * Copyright 2012-15 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#include "dm_services.h"
 27
 28#include "include/logger_interface.h"
 29
 30#include "irq_service_dce80.h"
 31#include "../dce110/irq_service_dce110.h"
 32
 33#include "dce/dce_8_0_d.h"
 34#include "dce/dce_8_0_sh_mask.h"
 35
 36#include "ivsrcid/ivsrcid_vislands30.h"
 37
 38#include "dc_types.h"
 39
 40static struct irq_source_info_funcs hpd_irq_info_funcs  = {
 41	.set = NULL,
 42	.ack = hpd1_ack
 43};
 44
 45static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
 46	.set = NULL,
 47	.ack = NULL
 48};
 49
 50static struct irq_source_info_funcs pflip_irq_info_funcs = {
 51	.set = NULL,
 52	.ack = NULL
 53};
 54
 55static struct irq_source_info_funcs vblank_irq_info_funcs = {
 56	.set = dce110_vblank_set,
 57	.ack = NULL
 58};
 59
 60static struct irq_source_info_funcs vupdate_irq_info_funcs = {
 61	.set = NULL,
 62	.ack = NULL
 63};
 64
 65#define hpd_int_entry(reg_num)\
 66	[DC_IRQ_SOURCE_INVALID + reg_num] = {\
 67		.enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
 68		.enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
 69		.enable_value = {\
 70			DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
 71			~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK\
 72		},\
 73		.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
 74		.ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
 75		.ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
 76		.status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
 77		.funcs = &hpd_irq_info_funcs\
 78	}
 79
 80#define hpd_rx_int_entry(reg_num)\
 81	[DC_IRQ_SOURCE_HPD6 + reg_num] = {\
 82		.enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
 83		.enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
 84		.enable_value = {\
 85				DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
 86			~DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK },\
 87		.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
 88		.ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
 89		.ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
 90		.status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
 91		.funcs = &hpd_rx_irq_info_funcs\
 92	}
 93
 94#define pflip_int_entry(reg_num)\
 95	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
 96		.enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\
 97		.enable_mask =\
 98		GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
 99		.enable_value = {\
100			GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
101			~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
102		.ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
103		.ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
104		.ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
105		.status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
106		.funcs = &pflip_irq_info_funcs\
107 	}
108
109#define vupdate_int_entry(reg_num)\
110	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
111		.enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\
112		.enable_mask =\
113		CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
114		.enable_value = {\
115			CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
116			~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
117		.ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
118		.ack_mask =\
119		CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
120		.ack_value =\
121		CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
122		.funcs = &vupdate_irq_info_funcs\
123	}
124
125#define vblank_int_entry(reg_num)\
126	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
127		.enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
128		.enable_mask =\
129		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
130		.enable_value = {\
131			CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
132			~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
133		.ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
134		.ack_mask =\
135		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
136		.ack_value =\
137		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
138		.funcs = &vblank_irq_info_funcs,\
139		.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
140	}
141
142#define dummy_irq_entry() \
143	{\
144		.funcs = &dummy_irq_info_funcs\
145	}
146
147#define i2c_int_entry(reg_num) \
148	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
149
150#define dp_sink_int_entry(reg_num) \
151	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
152
153#define gpio_pad_int_entry(reg_num) \
154	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
155
156#define dc_underflow_int_entry(reg_num) \
157	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
158
159
160static struct irq_source_info_funcs dummy_irq_info_funcs = {
161	.set = dal_irq_service_dummy_set,
162	.ack = dal_irq_service_dummy_ack
163};
164
165static const struct irq_source_info
166irq_source_info_dce80[DAL_IRQ_SOURCES_NUMBER] = {
167	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
168	hpd_int_entry(1),
169	hpd_int_entry(2),
170	hpd_int_entry(3),
171	hpd_int_entry(4),
172	hpd_int_entry(5),
173	hpd_int_entry(6),
174	hpd_rx_int_entry(1),
175	hpd_rx_int_entry(2),
176	hpd_rx_int_entry(3),
177	hpd_rx_int_entry(4),
178	hpd_rx_int_entry(5),
179	hpd_rx_int_entry(6),
180	i2c_int_entry(1),
181	i2c_int_entry(2),
182	i2c_int_entry(3),
183	i2c_int_entry(4),
184	i2c_int_entry(5),
185	i2c_int_entry(6),
186	dp_sink_int_entry(1),
187	dp_sink_int_entry(2),
188	dp_sink_int_entry(3),
189	dp_sink_int_entry(4),
190	dp_sink_int_entry(5),
191	dp_sink_int_entry(6),
192	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
193	pflip_int_entry(0),
194	pflip_int_entry(1),
195	pflip_int_entry(2),
196	pflip_int_entry(3),
197	pflip_int_entry(4),
198	pflip_int_entry(5),
199	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
200	gpio_pad_int_entry(0),
201	gpio_pad_int_entry(1),
202	gpio_pad_int_entry(2),
203	gpio_pad_int_entry(3),
204	gpio_pad_int_entry(4),
205	gpio_pad_int_entry(5),
206	gpio_pad_int_entry(6),
207	gpio_pad_int_entry(7),
208	gpio_pad_int_entry(8),
209	gpio_pad_int_entry(9),
210	gpio_pad_int_entry(10),
211	gpio_pad_int_entry(11),
212	gpio_pad_int_entry(12),
213	gpio_pad_int_entry(13),
214	gpio_pad_int_entry(14),
215	gpio_pad_int_entry(15),
216	gpio_pad_int_entry(16),
217	gpio_pad_int_entry(17),
218	gpio_pad_int_entry(18),
219	gpio_pad_int_entry(19),
220	gpio_pad_int_entry(20),
221	gpio_pad_int_entry(21),
222	gpio_pad_int_entry(22),
223	gpio_pad_int_entry(23),
224	gpio_pad_int_entry(24),
225	gpio_pad_int_entry(25),
226	gpio_pad_int_entry(26),
227	gpio_pad_int_entry(27),
228	gpio_pad_int_entry(28),
229	gpio_pad_int_entry(29),
230	gpio_pad_int_entry(30),
231	dc_underflow_int_entry(1),
232	dc_underflow_int_entry(2),
233	dc_underflow_int_entry(3),
234	dc_underflow_int_entry(4),
235	dc_underflow_int_entry(5),
236	dc_underflow_int_entry(6),
237	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
238	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
239	vupdate_int_entry(0),
240	vupdate_int_entry(1),
241	vupdate_int_entry(2),
242	vupdate_int_entry(3),
243	vupdate_int_entry(4),
244	vupdate_int_entry(5),
245	vblank_int_entry(0),
246	vblank_int_entry(1),
247	vblank_int_entry(2),
248	vblank_int_entry(3),
249	vblank_int_entry(4),
250	vblank_int_entry(5),
251};
252
253static const struct irq_service_funcs irq_service_funcs_dce80 = {
254		.to_dal_irq_source = to_dal_irq_source_dce110
255};
256
257static void dce80_irq_construct(
258	struct irq_service *irq_service,
259	struct irq_service_init_data *init_data)
260{
261	dal_irq_service_construct(irq_service, init_data);
262
263	irq_service->info = irq_source_info_dce80;
264	irq_service->funcs = &irq_service_funcs_dce80;
265}
266
267struct irq_service *dal_irq_service_dce80_create(
268	struct irq_service_init_data *init_data)
269{
270	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
271						  GFP_KERNEL);
272
273	if (!irq_service)
274		return NULL;
275
276	dce80_irq_construct(irq_service, init_data);
277	return irq_service;
278}