irq_service_dce120.c

  1/*
  2 * Copyright 2012-15 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#include "dm_services.h"
 27
 28#include "include/logger_interface.h"
 29
 30#include "irq_service_dce120.h"
 31#include "../dce110/irq_service_dce110.h"
 32
 33#include "dce/dce_12_0_offset.h"
 34#include "dce/dce_12_0_sh_mask.h"
 35#include "soc15_hw_ip.h"
 36#include "vega10_ip_offset.h"
 37
 38#include "ivsrcid/ivsrcid_vislands30.h"
 39
 40static struct irq_source_info_funcs hpd_irq_info_funcs  = {
 41	.set = NULL,
 42	.ack = hpd0_ack
 43};
 44
 45static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
 46	.set = NULL,
 47	.ack = NULL
 48};
 49
 50static struct irq_source_info_funcs pflip_irq_info_funcs = {
 51	.set = NULL,
 52	.ack = NULL
 53};
 54
 55static struct irq_source_info_funcs vblank_irq_info_funcs = {
 56	.set = dce110_vblank_set,
 57	.ack = NULL
 58};
 59
 60static struct irq_source_info_funcs vupdate_irq_info_funcs = {
 61	.set = NULL,
 62	.ack = NULL
 63};
 64
 65#define BASE_INNER(seg) \
 66	DCE_BASE__INST0_SEG ## seg
 67
 68#define BASE(seg) \
 69	BASE_INNER(seg)
 70
 71#define SRI(reg_name, block, id)\
 72	BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 73			mm ## block ## id ## _ ## reg_name
 74
 75
 76#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
 77	.enable_reg = SRI(reg1, block, reg_num),\
 78	.enable_mask = \
 79		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
 80	.enable_value = {\
 81		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
 82		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
 83	},\
 84	.ack_reg = SRI(reg2, block, reg_num),\
 85	.ack_mask = \
 86		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
 87	.ack_value = \
 88		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
 89
 90#define hpd_int_entry(reg_num)\
 91	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
 92		IRQ_REG_ENTRY(HPD, reg_num,\
 93			DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
 94			DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
 95		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
 96		.funcs = &hpd_irq_info_funcs\
 97	}
 98
 99#define hpd_rx_int_entry(reg_num)\
100	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
101		IRQ_REG_ENTRY(HPD, reg_num,\
102			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
103			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
104		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
105		.funcs = &hpd_rx_irq_info_funcs\
106	}
107#define pflip_int_entry(reg_num)\
108	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
109		IRQ_REG_ENTRY(DCP, reg_num, \
110			GRPH_INTERRUPT_CONTROL, GRPH_PFLIP_INT_MASK, \
111			GRPH_INTERRUPT_STATUS, GRPH_PFLIP_INT_CLEAR),\
112		.status_reg = SRI(GRPH_INTERRUPT_STATUS, DCP, reg_num),\
113		.funcs = &pflip_irq_info_funcs\
114	}
115
116#define vupdate_int_entry(reg_num)\
117	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
118		IRQ_REG_ENTRY(CRTC, reg_num,\
119			CRTC_INTERRUPT_CONTROL, CRTC_V_UPDATE_INT_MSK,\
120			CRTC_V_UPDATE_INT_STATUS, CRTC_V_UPDATE_INT_CLEAR),\
121		.funcs = &vupdate_irq_info_funcs\
122	}
123
124#define vblank_int_entry(reg_num)\
125	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
126		IRQ_REG_ENTRY(CRTC, reg_num,\
127				CRTC_VERTICAL_INTERRUPT0_CONTROL, CRTC_VERTICAL_INTERRUPT0_INT_ENABLE,\
128				CRTC_VERTICAL_INTERRUPT0_CONTROL, CRTC_VERTICAL_INTERRUPT0_CLEAR),\
129		.funcs = &vblank_irq_info_funcs,\
130		.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
131	}
132
133#define dummy_irq_entry() \
134	{\
135		.funcs = &dummy_irq_info_funcs\
136	}
137
138#define i2c_int_entry(reg_num) \
139	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
140
141#define dp_sink_int_entry(reg_num) \
142	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
143
144#define gpio_pad_int_entry(reg_num) \
145	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
146
147#define dc_underflow_int_entry(reg_num) \
148	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
149
150static struct irq_source_info_funcs dummy_irq_info_funcs = {
151	.set = dal_irq_service_dummy_set,
152	.ack = dal_irq_service_dummy_ack
153};
154
155static const struct irq_source_info
156irq_source_info_dce120[DAL_IRQ_SOURCES_NUMBER] = {
157	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
158	hpd_int_entry(0),
159	hpd_int_entry(1),
160	hpd_int_entry(2),
161	hpd_int_entry(3),
162	hpd_int_entry(4),
163	hpd_int_entry(5),
164	hpd_rx_int_entry(0),
165	hpd_rx_int_entry(1),
166	hpd_rx_int_entry(2),
167	hpd_rx_int_entry(3),
168	hpd_rx_int_entry(4),
169	hpd_rx_int_entry(5),
170	i2c_int_entry(1),
171	i2c_int_entry(2),
172	i2c_int_entry(3),
173	i2c_int_entry(4),
174	i2c_int_entry(5),
175	i2c_int_entry(6),
176	dp_sink_int_entry(1),
177	dp_sink_int_entry(2),
178	dp_sink_int_entry(3),
179	dp_sink_int_entry(4),
180	dp_sink_int_entry(5),
181	dp_sink_int_entry(6),
182	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
183	pflip_int_entry(0),
184	pflip_int_entry(1),
185	pflip_int_entry(2),
186	pflip_int_entry(3),
187	pflip_int_entry(4),
188	pflip_int_entry(5),
189	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
190	gpio_pad_int_entry(0),
191	gpio_pad_int_entry(1),
192	gpio_pad_int_entry(2),
193	gpio_pad_int_entry(3),
194	gpio_pad_int_entry(4),
195	gpio_pad_int_entry(5),
196	gpio_pad_int_entry(6),
197	gpio_pad_int_entry(7),
198	gpio_pad_int_entry(8),
199	gpio_pad_int_entry(9),
200	gpio_pad_int_entry(10),
201	gpio_pad_int_entry(11),
202	gpio_pad_int_entry(12),
203	gpio_pad_int_entry(13),
204	gpio_pad_int_entry(14),
205	gpio_pad_int_entry(15),
206	gpio_pad_int_entry(16),
207	gpio_pad_int_entry(17),
208	gpio_pad_int_entry(18),
209	gpio_pad_int_entry(19),
210	gpio_pad_int_entry(20),
211	gpio_pad_int_entry(21),
212	gpio_pad_int_entry(22),
213	gpio_pad_int_entry(23),
214	gpio_pad_int_entry(24),
215	gpio_pad_int_entry(25),
216	gpio_pad_int_entry(26),
217	gpio_pad_int_entry(27),
218	gpio_pad_int_entry(28),
219	gpio_pad_int_entry(29),
220	gpio_pad_int_entry(30),
221	dc_underflow_int_entry(1),
222	dc_underflow_int_entry(2),
223	dc_underflow_int_entry(3),
224	dc_underflow_int_entry(4),
225	dc_underflow_int_entry(5),
226	dc_underflow_int_entry(6),
227	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
228	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
229	vupdate_int_entry(0),
230	vupdate_int_entry(1),
231	vupdate_int_entry(2),
232	vupdate_int_entry(3),
233	vupdate_int_entry(4),
234	vupdate_int_entry(5),
235	vblank_int_entry(0),
236	vblank_int_entry(1),
237	vblank_int_entry(2),
238	vblank_int_entry(3),
239	vblank_int_entry(4),
240	vblank_int_entry(5),
241};
242
243static const struct irq_service_funcs irq_service_funcs_dce120 = {
244		.to_dal_irq_source = to_dal_irq_source_dce110
245};
246
247static void dce120_irq_construct(
248	struct irq_service *irq_service,
249	struct irq_service_init_data *init_data)
250{
251	dal_irq_service_construct(irq_service, init_data);
252
253	irq_service->info = irq_source_info_dce120;
254	irq_service->funcs = &irq_service_funcs_dce120;
255}
256
257struct irq_service *dal_irq_service_dce120_create(
258	struct irq_service_init_data *init_data)
259{
260	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
261						  GFP_KERNEL);
262
263	if (!irq_service)
264		return NULL;
265
266	dce120_irq_construct(irq_service, init_data);
267	return irq_service;
268}