irq_service_dce110.c

  1/*
  2 * Copyright 2012-15 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#include "dm_services.h"
 27
 28#include "include/logger_interface.h"
 29
 30#include "irq_service_dce110.h"
 31
 32#include "dce/dce_11_0_d.h"
 33#include "dce/dce_11_0_sh_mask.h"
 34
 35#include "ivsrcid/ivsrcid_vislands30.h"
 36
 37#include "dc.h"
 38#include "core_types.h"
 39#define DC_LOGGER \
 40	irq_service->ctx->logger
 41
 42static bool hpd_ack(struct irq_service *irq_service,
 43		    const struct irq_source_info *info)
 44{
 45	uint32_t addr = info->status_reg;
 46	uint32_t value = dm_read_reg(irq_service->ctx, addr);
 47	uint32_t current_status = get_reg_field_value(value,
 48						      DC_HPD_INT_STATUS,
 49						      DC_HPD_SENSE_DELAYED);
 50
 51	dal_irq_service_ack_generic(irq_service, info);
 52
 53	value = dm_read_reg(irq_service->ctx, info->enable_reg);
 54
 55	set_reg_field_value(value, current_status ? 0 : 1,
 56			    DC_HPD_INT_CONTROL,
 57			    DC_HPD_INT_POLARITY);
 58
 59	dm_write_reg(irq_service->ctx, info->enable_reg, value);
 60
 61	return true;
 62}
 63
 64static struct irq_source_info_funcs hpd_irq_info_funcs  = {
 65	.set = NULL,
 66	.ack = hpd_ack
 67};
 68
 69static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
 70	.set = NULL,
 71	.ack = NULL
 72};
 73
 74static struct irq_source_info_funcs pflip_irq_info_funcs = {
 75	.set = NULL,
 76	.ack = NULL
 77};
 78
 79static struct irq_source_info_funcs vblank_irq_info_funcs = {
 80	.set = dce110_vblank_set,
 81	.ack = NULL
 82};
 83
 84static struct irq_source_info_funcs vupdate_irq_info_funcs = {
 85	.set = NULL,
 86	.ack = NULL
 87};
 88
 89#define hpd_int_entry(reg_num)\
 90	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
 91		.enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
 92		.enable_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
 93		.enable_value = {\
 94			DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
 95			~DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK\
 96		},\
 97		.ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
 98		.ack_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK,\
 99		.ack_value = DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK,\
100		.status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
101		.funcs = &hpd_irq_info_funcs\
102	}
103
104#define hpd_rx_int_entry(reg_num)\
105	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
106		.enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
107		.enable_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK,\
108		.enable_value = {\
109			DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK,\
110			~DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK },\
111		.ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
112		.ack_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\
113		.ack_value = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\
114		.status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
115		.funcs = &hpd_rx_irq_info_funcs\
116	}
117#define pflip_int_entry(reg_num)\
118	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
119		.enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\
120		.enable_mask =\
121		GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
122		.enable_value = {\
123			GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
124			~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
125		.ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
126		.ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
127		.ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
128		.status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
129		.funcs = &pflip_irq_info_funcs\
130	}
131
132#define vupdate_int_entry(reg_num)\
133	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
134		.enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\
135		.enable_mask =\
136		CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
137		.enable_value = {\
138			CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
139			~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
140		.ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
141		.ack_mask =\
142		CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
143		.ack_value =\
144		CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
145		.funcs = &vupdate_irq_info_funcs\
146	}
147
148#define vblank_int_entry(reg_num)\
149	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
150		.enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
151		.enable_mask =\
152		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
153		.enable_value = {\
154			CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
155			~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
156		.ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
157		.ack_mask =\
158		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
159		.ack_value =\
160		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
161		.funcs = &vblank_irq_info_funcs,\
162		.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
163	}
164
165#define dummy_irq_entry() \
166	{\
167		.funcs = &dummy_irq_info_funcs\
168	}
169
170#define i2c_int_entry(reg_num) \
171	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
172
173#define dp_sink_int_entry(reg_num) \
174	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
175
176#define gpio_pad_int_entry(reg_num) \
177	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
178
179#define dc_underflow_int_entry(reg_num) \
180	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
181
182bool dal_irq_service_dummy_set(struct irq_service *irq_service,
183			       const struct irq_source_info *info,
184			       bool enable)
185{
186	DC_LOG_ERROR("%s: called for non-implemented irq source, src_id=%u, ext_id=%u\n",
187		     __func__, info->src_id, info->ext_id);
188
189	return false;
190}
191
192bool dal_irq_service_dummy_ack(struct irq_service *irq_service,
193			       const struct irq_source_info *info)
194{
195	DC_LOG_ERROR("%s: called for non-implemented irq source, src_id=%u, ext_id=%u\n",
196		     __func__, info->src_id, info->ext_id);
197
198	return false;
199}
200
201
202bool dce110_vblank_set(struct irq_service *irq_service,
203		       const struct irq_source_info *info,
204		       bool enable)
205{
206	struct dc_context *dc_ctx = irq_service->ctx;
207	struct dc *dc = irq_service->ctx->dc;
208	enum dc_irq_source dal_irq_src =
209			dc_interrupt_to_irq_source(irq_service->ctx->dc,
210						   info->src_id,
211						   info->ext_id);
212	uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK;
213
214	struct timing_generator *tg;
215
216	if (pipe_offset >= MAX_PIPES)
217		return false;
218
219	tg = dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
220
221	if (enable) {
222		if (!tg || !tg->funcs->arm_vert_intr(tg, 2)) {
223			DC_ERROR("Failed to get VBLANK!\n");
224			return false;
225		}
226	}
227
228	dal_irq_service_set_generic(irq_service, info, enable);
229	return true;
230}
231
232static struct irq_source_info_funcs dummy_irq_info_funcs = {
233	.set = dal_irq_service_dummy_set,
234	.ack = dal_irq_service_dummy_ack
235};
236
237static const struct irq_source_info
238irq_source_info_dce110[DAL_IRQ_SOURCES_NUMBER] = {
239	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
240	hpd_int_entry(0),
241	hpd_int_entry(1),
242	hpd_int_entry(2),
243	hpd_int_entry(3),
244	hpd_int_entry(4),
245	hpd_int_entry(5),
246	hpd_rx_int_entry(0),
247	hpd_rx_int_entry(1),
248	hpd_rx_int_entry(2),
249	hpd_rx_int_entry(3),
250	hpd_rx_int_entry(4),
251	hpd_rx_int_entry(5),
252	i2c_int_entry(1),
253	i2c_int_entry(2),
254	i2c_int_entry(3),
255	i2c_int_entry(4),
256	i2c_int_entry(5),
257	i2c_int_entry(6),
258	dp_sink_int_entry(1),
259	dp_sink_int_entry(2),
260	dp_sink_int_entry(3),
261	dp_sink_int_entry(4),
262	dp_sink_int_entry(5),
263	dp_sink_int_entry(6),
264	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
265	pflip_int_entry(0),
266	pflip_int_entry(1),
267	pflip_int_entry(2),
268	pflip_int_entry(3),
269	pflip_int_entry(4),
270	pflip_int_entry(5),
271	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
272	gpio_pad_int_entry(0),
273	gpio_pad_int_entry(1),
274	gpio_pad_int_entry(2),
275	gpio_pad_int_entry(3),
276	gpio_pad_int_entry(4),
277	gpio_pad_int_entry(5),
278	gpio_pad_int_entry(6),
279	gpio_pad_int_entry(7),
280	gpio_pad_int_entry(8),
281	gpio_pad_int_entry(9),
282	gpio_pad_int_entry(10),
283	gpio_pad_int_entry(11),
284	gpio_pad_int_entry(12),
285	gpio_pad_int_entry(13),
286	gpio_pad_int_entry(14),
287	gpio_pad_int_entry(15),
288	gpio_pad_int_entry(16),
289	gpio_pad_int_entry(17),
290	gpio_pad_int_entry(18),
291	gpio_pad_int_entry(19),
292	gpio_pad_int_entry(20),
293	gpio_pad_int_entry(21),
294	gpio_pad_int_entry(22),
295	gpio_pad_int_entry(23),
296	gpio_pad_int_entry(24),
297	gpio_pad_int_entry(25),
298	gpio_pad_int_entry(26),
299	gpio_pad_int_entry(27),
300	gpio_pad_int_entry(28),
301	gpio_pad_int_entry(29),
302	gpio_pad_int_entry(30),
303	dc_underflow_int_entry(1),
304	dc_underflow_int_entry(2),
305	dc_underflow_int_entry(3),
306	dc_underflow_int_entry(4),
307	dc_underflow_int_entry(5),
308	dc_underflow_int_entry(6),
309	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
310	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
311	vupdate_int_entry(0),
312	vupdate_int_entry(1),
313	vupdate_int_entry(2),
314	vupdate_int_entry(3),
315	vupdate_int_entry(4),
316	vupdate_int_entry(5),
317	vblank_int_entry(0),
318	vblank_int_entry(1),
319	vblank_int_entry(2),
320	vblank_int_entry(3),
321	vblank_int_entry(4),
322	vblank_int_entry(5),
323
324};
325
326enum dc_irq_source to_dal_irq_source_dce110(
327		struct irq_service *irq_service,
328		uint32_t src_id,
329		uint32_t ext_id)
330{
331	switch (src_id) {
332	case VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0:
333		return DC_IRQ_SOURCE_VBLANK1;
334	case VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT0:
335		return DC_IRQ_SOURCE_VBLANK2;
336	case VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT0:
337		return DC_IRQ_SOURCE_VBLANK3;
338	case VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT0:
339		return DC_IRQ_SOURCE_VBLANK4;
340	case VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT0:
341		return DC_IRQ_SOURCE_VBLANK5;
342	case VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0:
343		return DC_IRQ_SOURCE_VBLANK6;
344	case VISLANDS30_IV_SRCID_D1_V_UPDATE_INT:
345		return DC_IRQ_SOURCE_VUPDATE1;
346	case VISLANDS30_IV_SRCID_D2_V_UPDATE_INT:
347		return DC_IRQ_SOURCE_VUPDATE2;
348	case VISLANDS30_IV_SRCID_D3_V_UPDATE_INT:
349		return DC_IRQ_SOURCE_VUPDATE3;
350	case VISLANDS30_IV_SRCID_D4_V_UPDATE_INT:
351		return DC_IRQ_SOURCE_VUPDATE4;
352	case VISLANDS30_IV_SRCID_D5_V_UPDATE_INT:
353		return DC_IRQ_SOURCE_VUPDATE5;
354	case VISLANDS30_IV_SRCID_D6_V_UPDATE_INT:
355		return DC_IRQ_SOURCE_VUPDATE6;
356	case VISLANDS30_IV_SRCID_D1_GRPH_PFLIP:
357		return DC_IRQ_SOURCE_PFLIP1;
358	case VISLANDS30_IV_SRCID_D2_GRPH_PFLIP:
359		return DC_IRQ_SOURCE_PFLIP2;
360	case VISLANDS30_IV_SRCID_D3_GRPH_PFLIP:
361		return DC_IRQ_SOURCE_PFLIP3;
362	case VISLANDS30_IV_SRCID_D4_GRPH_PFLIP:
363		return DC_IRQ_SOURCE_PFLIP4;
364	case VISLANDS30_IV_SRCID_D5_GRPH_PFLIP:
365		return DC_IRQ_SOURCE_PFLIP5;
366	case VISLANDS30_IV_SRCID_D6_GRPH_PFLIP:
367		return DC_IRQ_SOURCE_PFLIP6;
368
369	case VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A:
370		/* generic src_id for all HPD and HPDRX interrupts */
371		switch (ext_id) {
372		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A:
373			return DC_IRQ_SOURCE_HPD1;
374		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_B:
375			return DC_IRQ_SOURCE_HPD2;
376		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_C:
377			return DC_IRQ_SOURCE_HPD3;
378		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_D:
379			return DC_IRQ_SOURCE_HPD4;
380		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_E:
381			return DC_IRQ_SOURCE_HPD5;
382		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_F:
383			return DC_IRQ_SOURCE_HPD6;
384		case VISLANDS30_IV_EXTID_HPD_RX_A:
385			return DC_IRQ_SOURCE_HPD1RX;
386		case VISLANDS30_IV_EXTID_HPD_RX_B:
387			return DC_IRQ_SOURCE_HPD2RX;
388		case VISLANDS30_IV_EXTID_HPD_RX_C:
389			return DC_IRQ_SOURCE_HPD3RX;
390		case VISLANDS30_IV_EXTID_HPD_RX_D:
391			return DC_IRQ_SOURCE_HPD4RX;
392		case VISLANDS30_IV_EXTID_HPD_RX_E:
393			return DC_IRQ_SOURCE_HPD5RX;
394		case VISLANDS30_IV_EXTID_HPD_RX_F:
395			return DC_IRQ_SOURCE_HPD6RX;
396		default:
397			return DC_IRQ_SOURCE_INVALID;
398		}
399		break;
400
401	default:
402		return DC_IRQ_SOURCE_INVALID;
403	}
404}
405
406static const struct irq_service_funcs irq_service_funcs_dce110 = {
407		.to_dal_irq_source = to_dal_irq_source_dce110
408};
409
410static void dce110_irq_construct(struct irq_service *irq_service,
411		      struct irq_service_init_data *init_data)
412{
413	dal_irq_service_construct(irq_service, init_data);
414
415	irq_service->info = irq_source_info_dce110;
416	irq_service->funcs = &irq_service_funcs_dce110;
417}
418
419struct irq_service *
420dal_irq_service_dce110_create(struct irq_service_init_data *init_data)
421{
422	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
423						  GFP_KERNEL);
424
425	if (!irq_service)
426		return NULL;
427
428	dce110_irq_construct(irq_service, init_data);
429	return irq_service;
430}