link_encoder.h

  1/*
  2 * Copyright 2017 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 */
 23/*
 24 * link_encoder.h
 25 *
 26 *  Created on: Oct 6, 2015
 27 *      Author: yonsun
 28 */
 29
 30#ifndef LINK_ENCODER_H_
 31#define LINK_ENCODER_H_
 32
 33#include "grph_object_defs.h"
 34#include "signal_types.h"
 35#include "dc_types.h"
 36
 37struct dc_context;
 38struct encoder_set_dp_phy_pattern_param;
 39struct link_mst_stream_allocation_table;
 40struct dc_link_settings;
 41struct link_training_settings;
 42struct pipe_ctx;
 43
 44struct encoder_init_data {
 45	enum channel_id channel;
 46	struct graphics_object_id connector;
 47	enum hpd_source_id hpd_source;
 48	/* TODO: in DAL2, here was pointer to EventManagerInterface */
 49	struct graphics_object_id encoder;
 50	struct graphics_object_id analog_encoder;
 51	enum engine_id analog_engine;
 52	struct dc_context *ctx;
 53	enum transmitter transmitter;
 54};
 55
 56struct encoder_feature_support {
 57	union {
 58		struct {
 59			uint32_t IS_HBR2_CAPABLE:1;
 60			uint32_t IS_HBR3_CAPABLE:1;
 61			uint32_t IS_TPS3_CAPABLE:1;
 62			uint32_t IS_TPS4_CAPABLE:1;
 63			uint32_t HDMI_6GB_EN:1;
 64			uint32_t IS_DP2_CAPABLE:1;
 65			uint32_t IS_UHBR10_CAPABLE:1;
 66			uint32_t IS_UHBR13_5_CAPABLE:1;
 67			uint32_t IS_UHBR20_CAPABLE:1;
 68			uint32_t DP_IS_USB_C:1;
 69		} bits;
 70		uint32_t raw;
 71	} flags;
 72
 73	enum dc_color_depth max_hdmi_deep_color;
 74	unsigned int max_hdmi_pixel_clock;
 75	bool hdmi_ycbcr420_supported;
 76	bool dp_ycbcr420_supported;
 77	bool fec_supported;
 78};
 79
 80struct link_encoder {
 81	const struct link_encoder_funcs *funcs;
 82	int32_t aux_channel_offset;
 83	struct dc_context *ctx;
 84	struct graphics_object_id id;
 85	struct graphics_object_id analog_id;
 86	struct graphics_object_id connector;
 87	uint32_t output_signals;
 88	enum engine_id preferred_engine;
 89	enum engine_id analog_engine;
 90	struct encoder_feature_support features;
 91	enum transmitter transmitter;
 92	enum hpd_source_id hpd_source;
 93	bool usbc_combo_phy;
 94};
 95
 96struct link_enc_state {
 97
 98		uint32_t dphy_fec_en;
 99		uint32_t dphy_fec_ready_shadow;
100		uint32_t dphy_fec_active_status;
101		uint32_t dp_link_training_complete;
102
103};
104
105enum encoder_type_select {
106	ENCODER_TYPE_DIG = 0,
107	ENCODER_TYPE_HDMI_FRL = 1,
108	ENCODER_TYPE_DP_128B132B = 2
109};
110
111struct link_encoder_funcs {
112	void (*read_state)(
113			struct link_encoder *enc, struct link_enc_state *s);
114	bool (*validate_output_with_stream)(
115		struct link_encoder *enc, const struct dc_stream_state *stream);
116	void (*hw_init)(struct link_encoder *enc);
117	void (*setup)(struct link_encoder *enc,
118		enum signal_type signal);
119	void (*enable_tmds_output)(struct link_encoder *enc,
120		enum clock_source_id clock_source,
121		enum dc_color_depth color_depth,
122		enum signal_type signal,
123		uint32_t pixel_clock);
124	void (*enable_dp_output)(struct link_encoder *enc,
125		const struct dc_link_settings *link_settings,
126		enum clock_source_id clock_source);
127	void (*enable_dp_mst_output)(struct link_encoder *enc,
128		const struct dc_link_settings *link_settings,
129		enum clock_source_id clock_source);
130	void (*enable_lvds_output)(struct link_encoder *enc,
131		enum clock_source_id clock_source,
132		uint32_t pixel_clock);
133	void (*enable_analog_output)(struct link_encoder *enc,
134		uint32_t pixel_clock);
135	void (*disable_output)(struct link_encoder *link_enc,
136		enum signal_type signal);
137	void (*dp_set_lane_settings)(struct link_encoder *enc,
138		const struct dc_link_settings *link_settings,
139		const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
140	void (*dp_set_phy_pattern)(struct link_encoder *enc,
141		const struct encoder_set_dp_phy_pattern_param *para);
142	void (*update_mst_stream_allocation_table)(
143		struct link_encoder *enc,
144		const struct link_mst_stream_allocation_table *table);
145	void (*psr_program_dp_dphy_fast_training)(struct link_encoder *enc,
146			bool exit_link_training_required);
147	void (*psr_program_secondary_packet)(struct link_encoder *enc,
148				unsigned int sdp_transmit_line_num_deadline);
149	void (*connect_dig_be_to_fe)(struct link_encoder *enc,
150		enum engine_id engine,
151		bool connect);
152	void (*enable_hpd)(struct link_encoder *enc);
153	void (*disable_hpd)(struct link_encoder *enc);
154	bool (*is_dig_enabled)(struct link_encoder *enc);
155	unsigned int (*get_dig_frontend)(struct link_encoder *enc);
156	void (*destroy)(struct link_encoder **enc);
157
158	void (*fec_set_enable)(struct link_encoder *enc,
159		bool enable);
160
161	void (*fec_set_ready)(struct link_encoder *enc,
162		bool ready);
163
164	bool (*fec_is_active)(struct link_encoder *enc);
165	bool (*is_in_alt_mode) (struct link_encoder *enc);
166
167	void (*get_max_link_cap)(struct link_encoder *enc,
168		struct dc_link_settings *link_settings);
169
170	enum signal_type (*get_dig_mode)(
171		struct link_encoder *enc);
172
173	void (*set_dio_phy_mux)(
174		struct link_encoder *enc,
175		enum encoder_type_select sel,
176		uint32_t hpo_inst);
177	void (*enable_dpia_output)(struct link_encoder *enc,
178		const struct dc_link_settings *link_settings,
179		uint8_t dpia_id,
180		uint8_t digmode,
181		uint8_t fec_rdy);
182	void (*disable_dpia_output)(struct link_encoder *link_enc,
183		uint8_t dpia_id,
184		uint8_t digmode);
185};
186
187/*
188 * Used to track assignments of links (display endpoints) to link encoders.
189 *
190 * Entry in link_enc_assignments table in struct resource_context.
191 * Entries only marked valid once encoder assigned to a link and invalidated once unassigned.
192 * Uses engine ID as identifier since PHY ID not relevant for USB4 DPIA endpoint.
193 */
194struct link_enc_assignment {
195	bool valid;
196	struct display_endpoint_id ep_id;
197	enum engine_id eng_id;
198	struct dc_stream_state *stream;
199};
200
201enum link_enc_cfg_mode {
202	LINK_ENC_CFG_STEADY, /* Normal operation - use current_state. */
203	LINK_ENC_CFG_TRANSIENT /* During commit state - use state to be committed. */
204};
205
206enum dp2_link_mode {
207	DP2_LINK_TRAINING_TPS1,
208	DP2_LINK_TRAINING_TPS2,
209	DP2_LINK_ACTIVE,
210	DP2_TEST_PATTERN
211};
212
213enum dp2_phy_tp_select {
214	DP_DPHY_TP_SELECT_TPS1,
215	DP_DPHY_TP_SELECT_TPS2,
216	DP_DPHY_TP_SELECT_PRBS,
217	DP_DPHY_TP_SELECT_CUSTOM,
218	DP_DPHY_TP_SELECT_SQUARE
219};
220
221enum dp2_phy_tp_prbs {
222	DP_DPHY_TP_PRBS7,
223	DP_DPHY_TP_PRBS9,
224	DP_DPHY_TP_PRBS11,
225	DP_DPHY_TP_PRBS15,
226	DP_DPHY_TP_PRBS23,
227	DP_DPHY_TP_PRBS31
228};
229
230struct hpo_dp_link_enc_state {
231	uint32_t   link_enc_enabled;
232	uint32_t   link_mode;
233	uint32_t   lane_count;
234	uint32_t   slot_count[4];
235	uint32_t   stream_src[4];
236	uint32_t   vc_rate_x[4];
237	uint32_t   vc_rate_y[4];
238};
239
240struct hpo_dp_link_encoder {
241	const struct hpo_dp_link_encoder_funcs *funcs;
242	struct dc_context *ctx;
243	int inst;
244	enum engine_id preferred_engine;
245	enum transmitter transmitter;
246	enum hpd_source_id hpd_source;
247};
248
249struct hpo_dp_link_encoder_funcs {
250
251	void (*enable_link_phy)(struct hpo_dp_link_encoder *enc,
252		const struct dc_link_settings *link_settings,
253		enum transmitter transmitter,
254		enum hpd_source_id hpd_source);
255
256	void (*disable_link_phy)(struct hpo_dp_link_encoder *link_enc,
257		enum signal_type signal);
258
259	void (*link_enable)(
260			struct hpo_dp_link_encoder *enc,
261			enum dc_lane_count num_lanes);
262
263	void (*link_disable)(
264			struct hpo_dp_link_encoder *enc);
265
266	void (*set_link_test_pattern)(
267			struct hpo_dp_link_encoder *enc,
268			struct encoder_set_dp_phy_pattern_param *tp_params);
269
270	void (*update_stream_allocation_table)(
271			struct hpo_dp_link_encoder *enc,
272			const struct link_mst_stream_allocation_table *table);
273
274	void (*set_throttled_vcp_size)(
275			struct hpo_dp_link_encoder *enc,
276			uint32_t stream_encoder_inst,
277			struct fixed31_32 avg_time_slots_per_mtp);
278
279	bool (*is_in_alt_mode) (
280			struct hpo_dp_link_encoder *enc);
281
282	void (*read_state)(
283			struct hpo_dp_link_encoder *enc,
284			struct hpo_dp_link_enc_state *state);
285
286	void (*set_ffe)(
287		struct hpo_dp_link_encoder *enc,
288		const struct dc_link_settings *link_settings,
289		uint8_t ffe_preset);
290};
291
292#endif /* LINK_ENCODER_H_ */