hw_shared.h

  1/*
  2 * Copyright 2015 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#ifndef __DAL_HW_SHARED_H__
 27#define __DAL_HW_SHARED_H__
 28
 29#include "os_types.h"
 30#include "fixed31_32.h"
 31#include "dc_hw_types.h"
 32
 33/******************************************************************************
 34 * Data types shared between different Virtual HW blocks
 35 ******************************************************************************/
 36
 37#define MAX_AUDIOS 7
 38
 39/**
 40 * @MAX_PIPES:
 41 *
 42 * Every ASIC support a fixed number of pipes; MAX_PIPES defines a large number
 43 * to be used inside loops and for determining array sizes.
 44 */
 45#define MAX_PIPES 6
 46#define MAX_PHANTOM_PIPES (MAX_PIPES / 2)
 47
 48#define MAX_DPIA 6
 49#define MAX_CONNECTOR 6
 50#define MAX_VIRTUAL_LINKS 4
 51
 52#define MAX_LINKS (MAX_DPIA + MAX_CONNECTOR + MAX_VIRTUAL_LINKS)
 53
 54/**
 55 * define MAX_DIG_LINK_ENCODERS - maximum number of digital encoders
 56 *
 57 * Digital encoders are ENGINE_ID_DIGA...G, there are at most 7,
 58 * although not every GPU may have that many.
 59 */
 60#define MAX_DIG_LINK_ENCODERS 7
 61
 62/**
 63 * define MAX_DAC_LINK_ENCODERS - maximum number of analog link encoders
 64 *
 65 * Analog encoders are ENGINE_ID_DACA/B, there are at most 2,
 66 * although not every GPU may have that many. Modern GPUs typically
 67 * don't have analog encoders.
 68 */
 69#define MAX_DAC_LINK_ENCODERS 2
 70
 71/**
 72 * define MAX_LINK_ENCODERS - maximum number link encoders in total
 73 *
 74 * This includes both analog and digital encoders.
 75 */
 76#define MAX_LINK_ENCODERS (MAX_DIG_LINK_ENCODERS + MAX_DAC_LINK_ENCODERS)
 77
 78#define MAX_DWB_PIPES	1
 79#define MAX_HPO_DP2_ENCODERS	4
 80#define MAX_HPO_DP2_LINK_ENCODERS	4
 81
 82/* Pipe topology snapshot structures */
 83#define MAX_TOPOLOGY_SNAPSHOTS 4
 84
 85struct pipe_topology_line {
 86	bool is_phantom_pipe;
 87	int plane_idx;
 88	int slice_idx;
 89	int stream_idx;
 90	int dpp_inst;
 91	int opp_inst;
 92	int tg_inst;
 93};
 94
 95struct pipe_topology_snapshot {
 96	struct pipe_topology_line pipe_log_lines[MAX_PIPES];
 97	int line_count;
 98	uint64_t timestamp_us;
 99	int stream_count;
100	int phantom_stream_count;
101};
102
103struct pipe_topology_history {
104	struct pipe_topology_snapshot snapshots[MAX_TOPOLOGY_SNAPSHOTS];
105	int current_snapshot_index;
106};
107
108struct gamma_curve {
109	uint32_t offset;
110	uint32_t segments_num;
111};
112
113struct curve_points {
114	struct fixed31_32 x;
115	struct fixed31_32 y;
116	struct fixed31_32 offset;
117	struct fixed31_32 slope;
118
119	uint32_t custom_float_x;
120	uint32_t custom_float_y;
121	uint32_t custom_float_offset;
122	uint32_t custom_float_slope;
123};
124
125struct curve_points3 {
126	struct curve_points red;
127	struct curve_points green;
128	struct curve_points blue;
129};
130
131struct pwl_result_data {
132	struct fixed31_32 red;
133	struct fixed31_32 green;
134	struct fixed31_32 blue;
135
136	struct fixed31_32 delta_red;
137	struct fixed31_32 delta_green;
138	struct fixed31_32 delta_blue;
139
140	uint32_t red_reg;
141	uint32_t green_reg;
142	uint32_t blue_reg;
143
144	uint32_t delta_red_reg;
145	uint32_t delta_green_reg;
146	uint32_t delta_blue_reg;
147};
148
149struct dc_rgb {
150	uint32_t red;
151	uint32_t green;
152	uint32_t blue;
153};
154
155struct tetrahedral_17x17x17 {
156	struct dc_rgb lut0[1229];
157	struct dc_rgb lut1[1228];
158	struct dc_rgb lut2[1228];
159	struct dc_rgb lut3[1228];
160};
161struct tetrahedral_9x9x9 {
162	struct dc_rgb lut0[183];
163	struct dc_rgb lut1[182];
164	struct dc_rgb lut2[182];
165	struct dc_rgb lut3[182];
166};
167
168struct tetrahedral_params {
169	union {
170		struct tetrahedral_17x17x17 tetrahedral_17;
171		struct tetrahedral_9x9x9 tetrahedral_9;
172	};
173	bool use_tetrahedral_9;
174	bool use_12bits;
175
176};
177
178/* arr_curve_points - regamma regions/segments specification
179 * arr_points - beginning and end point specified separately (only one on DCE)
180 * corner_points - beginning and end point for all 3 colors (DCN)
181 * rgb_resulted - final curve
182 */
183struct pwl_params {
184	struct gamma_curve arr_curve_points[34];
185	union {
186		struct curve_points arr_points[2];
187		struct curve_points3 corner_points[2];
188	};
189	struct pwl_result_data rgb_resulted[256 + 3];
190	uint32_t hw_points_num;
191};
192
193/* move to dpp
194 * while we are moving functionality out of opp to dpp to align
195 * HW programming to HW IP, we define these struct in hw_shared
196 * so we can still compile while refactoring
197 */
198
199enum lb_pixel_depth {
200	/* do not change the values because it is used as bit vector */
201	LB_PIXEL_DEPTH_18BPP = 1,
202	LB_PIXEL_DEPTH_24BPP = 2,
203	LB_PIXEL_DEPTH_30BPP = 4,
204	LB_PIXEL_DEPTH_36BPP = 8
205};
206
207enum graphics_csc_adjust_type {
208	GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0,
209	GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */
210	GRAPHICS_CSC_ADJUST_TYPE_SW  /*use adjustments */
211};
212
213enum ipp_degamma_mode {
214	IPP_DEGAMMA_MODE_BYPASS,
215	IPP_DEGAMMA_MODE_HW_sRGB,
216	IPP_DEGAMMA_MODE_HW_xvYCC,
217	IPP_DEGAMMA_MODE_USER_PWL
218};
219
220enum gamcor_mode {
221	GAMCOR_MODE_BYPASS,
222	GAMCOR_MODE_RESERVED_1,
223	GAMCOR_MODE_USER_PWL,
224	GAMCOR_MODE_RESERVED_3
225};
226
227enum ipp_output_format {
228	IPP_OUTPUT_FORMAT_12_BIT_FIX,
229	IPP_OUTPUT_FORMAT_16_BIT_BYPASS,
230	IPP_OUTPUT_FORMAT_FLOAT
231};
232
233enum expansion_mode {
234	EXPANSION_MODE_DYNAMIC,
235	EXPANSION_MODE_ZERO
236};
237
238struct default_adjustment {
239	enum lb_pixel_depth lb_color_depth;
240	enum dc_color_space out_color_space;
241	enum dc_color_space in_color_space;
242	enum dc_color_depth color_depth;
243	enum pixel_format surface_pixel_format;
244	enum graphics_csc_adjust_type csc_adjust_type;
245	bool force_hw_default;
246};
247
248
249struct out_csc_color_matrix {
250	enum dc_color_space color_space;
251	uint16_t regval[12];
252};
253
254enum gamut_remap_select {
255	GAMUT_REMAP_BYPASS = 0,
256	GAMUT_REMAP_COEFF,
257	GAMUT_REMAP_COMA_COEFF,
258	GAMUT_REMAP_COMB_COEFF
259};
260
261enum opp_regamma {
262	OPP_REGAMMA_BYPASS = 0,
263	OPP_REGAMMA_SRGB,
264	OPP_REGAMMA_XVYCC,
265	OPP_REGAMMA_USER
266};
267
268enum optc_dsc_mode {
269	OPTC_DSC_DISABLED = 0,
270	OPTC_DSC_ENABLED_444 = 1, /* 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4) */
271	OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED = 2 /* Native 4:2:2 or 4:2:0 */
272};
273
274struct dc_bias_and_scale {
275	uint32_t scale_red;
276	uint32_t bias_red;
277	uint32_t scale_green;
278	uint32_t bias_green;
279	uint32_t scale_blue;
280	uint32_t bias_blue;
281	bool bias_and_scale_valid;
282};
283
284enum test_pattern_dyn_range {
285	TEST_PATTERN_DYN_RANGE_VESA = 0,
286	TEST_PATTERN_DYN_RANGE_CEA
287};
288
289enum test_pattern_mode {
290	TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,
291	TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,
292	TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,
293	TEST_PATTERN_MODE_VERTICALBARS,
294	TEST_PATTERN_MODE_HORIZONTALBARS,
295	TEST_PATTERN_MODE_SINGLERAMP_RGB,
296	TEST_PATTERN_MODE_DUALRAMP_RGB,
297	TEST_PATTERN_MODE_XR_BIAS_RGB
298};
299
300enum test_pattern_color_format {
301	TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,
302	TEST_PATTERN_COLOR_FORMAT_BPC_8,
303	TEST_PATTERN_COLOR_FORMAT_BPC_10,
304	TEST_PATTERN_COLOR_FORMAT_BPC_12
305};
306
307enum controller_dp_test_pattern {
308	CONTROLLER_DP_TEST_PATTERN_D102 = 0,
309	CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,
310	CONTROLLER_DP_TEST_PATTERN_PRBS7,
311	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,
312	CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,
313	CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,
314	CONTROLLER_DP_TEST_PATTERN_COLORRAMP,
315	CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
316	CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
317	CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
318	CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
319	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA,
320	CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR
321};
322
323enum controller_dp_color_space {
324	CONTROLLER_DP_COLOR_SPACE_RGB,
325	CONTROLLER_DP_COLOR_SPACE_YCBCR601,
326	CONTROLLER_DP_COLOR_SPACE_YCBCR709,
327	CONTROLLER_DP_COLOR_SPACE_UDEFINED
328};
329
330enum dc_lut_mode {
331	LUT_BYPASS,
332	LUT_RAM_A,
333	LUT_RAM_B
334};
335
336/**
337 * speakersToChannels
338 *
339 * @brief
340 *  translate speakers to channels
341 *
342 *  FL  - Front Left
343 *  FR  - Front Right
344 *  RL  - Rear Left
345 *  RR  - Rear Right
346 *  RC  - Rear Center
347 *  FC  - Front Center
348 *  FLC - Front Left Center
349 *  FRC - Front Right Center
350 *  RLC - Rear Left Center
351 *  RRC - Rear Right Center
352 *  LFE - Low Freq Effect
353 *
354 *               FC
355 *          FLC      FRC
356 *    FL                    FR
357 *
358 *                    LFE
359 *              ()
360 *
361 *
362 *    RL                    RR
363 *          RLC      RRC
364 *               RC
365 *
366 *             ch  8   7   6   5   4   3   2   1
367 * 0b00000011      -   -   -   -   -   -   FR  FL
368 * 0b00000111      -   -   -   -   -   LFE FR  FL
369 * 0b00001011      -   -   -   -   FC  -   FR  FL
370 * 0b00001111      -   -   -   -   FC  LFE FR  FL
371 * 0b00010011      -   -   -   RC  -   -   FR  FL
372 * 0b00010111      -   -   -   RC  -   LFE FR  FL
373 * 0b00011011      -   -   -   RC  FC  -   FR  FL
374 * 0b00011111      -   -   -   RC  FC  LFE FR  FL
375 * 0b00110011      -   -   RR  RL  -   -   FR  FL
376 * 0b00110111      -   -   RR  RL  -   LFE FR  FL
377 * 0b00111011      -   -   RR  RL  FC  -   FR  FL
378 * 0b00111111      -   -   RR  RL  FC  LFE FR  FL
379 * 0b01110011      -   RC  RR  RL  -   -   FR  FL
380 * 0b01110111      -   RC  RR  RL  -   LFE FR  FL
381 * 0b01111011      -   RC  RR  RL  FC  -   FR  FL
382 * 0b01111111      -   RC  RR  RL  FC  LFE FR  FL
383 * 0b11110011      RRC RLC RR  RL  -   -   FR  FL
384 * 0b11110111      RRC RLC RR  RL  -   LFE FR  FL
385 * 0b11111011      RRC RLC RR  RL  FC  -   FR  FL
386 * 0b11111111      RRC RLC RR  RL  FC  LFE FR  FL
387 * 0b11000011      FRC FLC -   -   -   -   FR  FL
388 * 0b11000111      FRC FLC -   -   -   LFE FR  FL
389 * 0b11001011      FRC FLC -   -   FC  -   FR  FL
390 * 0b11001111      FRC FLC -   -   FC  LFE FR  FL
391 * 0b11010011      FRC FLC -   RC  -   -   FR  FL
392 * 0b11010111      FRC FLC -   RC  -   LFE FR  FL
393 * 0b11011011      FRC FLC -   RC  FC  -   FR  FL
394 * 0b11011111      FRC FLC -   RC  FC  LFE FR  FL
395 * 0b11110011      FRC FLC RR  RL  -   -   FR  FL
396 * 0b11110111      FRC FLC RR  RL  -   LFE FR  FL
397 * 0b11111011      FRC FLC RR  RL  FC  -   FR  FL
398 * 0b11111111      FRC FLC RR  RL  FC  LFE FR  FL
399 *
400 * @param
401 *  speakers - speaker information as it comes from CEA audio block
402 */
403/* translate speakers to channels */
404
405union audio_cea_channels {
406	uint8_t all;
407	struct audio_cea_channels_bits {
408		uint32_t FL:1;
409		uint32_t FR:1;
410		uint32_t LFE:1;
411		uint32_t FC:1;
412		uint32_t RL_RC:1;
413		uint32_t RR:1;
414		uint32_t RC_RLC_FLC:1;
415		uint32_t RRC_FRC:1;
416	} channels;
417};
418
419#endif /* __DAL_HW_SHARED_H__ */