dchubbub.h

  1/*
  2 * Copyright 2012-15 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#ifndef __DAL_DCHUBBUB_H__
 27#define __DAL_DCHUBBUB_H__
 28
 29/**
 30 * DOC: overview
 31 *
 32 * There is only one common DCHUBBUB. It contains the common request and return
 33 * blocks for the Data Fabric Interface that are not clock/power gated.
 34 */
 35
 36#include "dc/dc_hw_types.h"
 37
 38enum dcc_control {
 39	dcc_control__256_256_xxx,
 40	dcc_control__128_128_xxx,
 41	dcc_control__256_64_64,
 42	dcc_control__256_128_128,
 43	dcc_control__256_256,
 44	dcc_control__256_128,
 45	dcc_control__256_64,
 46
 47};
 48
 49enum segment_order {
 50	segment_order__na,
 51	segment_order__contiguous,
 52	segment_order__non_contiguous,
 53};
 54
 55struct dcn_hubbub_wm_set {
 56	uint32_t wm_set;
 57	uint32_t data_urgent;
 58	uint32_t pte_meta_urgent;
 59	uint32_t sr_enter;
 60	uint32_t sr_exit;
 61	uint32_t dram_clk_change;
 62	uint32_t usr_retrain;
 63	uint32_t fclk_pstate_change;
 64	uint32_t sr_enter_exit_Z8;
 65	uint32_t sr_enter_Z8;
 66};
 67
 68struct dcn_hubbub_wm {
 69	struct dcn_hubbub_wm_set sets[4];
 70};
 71
 72enum dcn_hubbub_page_table_depth {
 73	DCN_PAGE_TABLE_DEPTH_1_LEVEL,
 74	DCN_PAGE_TABLE_DEPTH_2_LEVEL,
 75	DCN_PAGE_TABLE_DEPTH_3_LEVEL,
 76	DCN_PAGE_TABLE_DEPTH_4_LEVEL
 77};
 78
 79enum dcn_hubbub_page_table_block_size {
 80	DCN_PAGE_TABLE_BLOCK_SIZE_4KB = 0,
 81	DCN_PAGE_TABLE_BLOCK_SIZE_8KB = 1,
 82	DCN_PAGE_TABLE_BLOCK_SIZE_16KB = 2,
 83	DCN_PAGE_TABLE_BLOCK_SIZE_32KB = 3,
 84	DCN_PAGE_TABLE_BLOCK_SIZE_64KB = 4,
 85	DCN_PAGE_TABLE_BLOCK_SIZE_128KB = 5,
 86	DCN_PAGE_TABLE_BLOCK_SIZE_256KB = 6,
 87	DCN_PAGE_TABLE_BLOCK_SIZE_512KB = 7,
 88	DCN_PAGE_TABLE_BLOCK_SIZE_1024KB = 8,
 89	DCN_PAGE_TABLE_BLOCK_SIZE_2048KB = 9
 90};
 91
 92struct dcn_hubbub_phys_addr_config {
 93	struct {
 94		uint64_t fb_top;
 95		uint64_t fb_offset;
 96		uint64_t fb_base;
 97		uint64_t agp_top;
 98		uint64_t agp_bot;
 99		uint64_t agp_base;
100	} system_aperture;
101
102	struct {
103		uint64_t page_table_start_addr;
104		uint64_t page_table_end_addr;
105		uint64_t page_table_base_addr;
106	} gart_config;
107
108	uint64_t page_table_default_page_addr;
109};
110
111struct dcn_hubbub_virt_addr_config {
112	uint64_t				page_table_start_addr;
113	uint64_t				page_table_end_addr;
114	enum dcn_hubbub_page_table_block_size	page_table_block_size;
115	enum dcn_hubbub_page_table_depth	page_table_depth;
116	uint64_t				page_table_base_addr;
117};
118
119struct hubbub_addr_config {
120	struct dcn_hubbub_phys_addr_config pa_config;
121	struct dcn_hubbub_virt_addr_config va_config;
122	struct {
123		uint64_t aperture_check_fault;
124		uint64_t generic_fault;
125	} default_addrs;
126};
127
128struct dcn_hubbub_state {
129	uint32_t vm_fault_addr_msb;
130	uint32_t vm_fault_addr_lsb;
131	uint32_t vm_error_status;
132	uint32_t vm_error_vmid;
133	uint32_t vm_error_pipe;
134	uint32_t vm_error_mode;
135	uint32_t test_debug_data;
136	uint32_t watermark_change_cntl;
137	uint32_t dram_state_cntl;
138};
139
140struct dcn_hubbub_reg_state {
141	uint32_t det0_ctrl;
142	uint32_t det1_ctrl;
143	uint32_t det2_ctrl;
144	uint32_t det3_ctrl;
145	uint32_t compbuf_ctrl;
146};
147
148struct hubbub_system_latencies {
149	uint32_t max_latency_ns;
150	uint32_t avg_latency_ns;
151	uint32_t min_latency_ns;
152};
153
154struct hubbub_urgent_latency_params {
155	uint32_t refclk_mhz;
156	uint32_t t_win_ns;
157	uint32_t bandwidth_mbps;
158	uint32_t bw_factor_x1000;
159};
160
161struct hubbub_funcs {
162	void (*update_dchub)(
163			struct hubbub *hubbub,
164			struct dchub_init_data *dh_data);
165
166	int (*init_dchub_sys_ctx)(
167			struct hubbub *hubbub,
168			struct dcn_hubbub_phys_addr_config *pa_config);
169	void (*init_vm_ctx)(
170			struct hubbub *hubbub,
171			struct dcn_hubbub_virt_addr_config *va_config,
172			int vmid);
173
174	bool (*get_dcc_compression_cap)(struct hubbub *hubbub,
175			const struct dc_dcc_surface_param *input,
176			struct dc_surface_dcc_cap *output);
177
178	bool (*dcc_support_swizzle)(
179			enum swizzle_mode_values swizzle,
180			unsigned int bytes_per_element,
181			enum segment_order *segment_order_horz,
182			enum segment_order *segment_order_vert);
183
184	bool (*dcc_support_swizzle_addr3)(
185			enum swizzle_mode_addr3_values swizzle,
186			unsigned int plane_pitch,
187			unsigned int bytes_per_element,
188			enum segment_order *segment_order_horz,
189			enum segment_order *segment_order_vert);
190
191	bool (*dcc_support_pixel_format_plane0_plane1)(
192			enum surface_pixel_format format,
193			unsigned int *plane0_bpe,
194			unsigned int *plane1_bpe);
195	bool (*dcc_support_pixel_format)(
196			enum surface_pixel_format format,
197			unsigned int *bytes_per_element);
198
199	void (*wm_read_state)(struct hubbub *hubbub,
200			struct dcn_hubbub_wm *wm);
201
202	void (*get_dchub_ref_freq)(struct hubbub *hubbub,
203			unsigned int dccg_ref_freq_inKhz,
204			unsigned int *dchub_ref_freq_inKhz);
205
206	bool (*program_watermarks)(
207			struct hubbub *hubbub,
208			union dcn_watermark_set *watermarks,
209			unsigned int refclk_mhz,
210			bool safe_to_lower);
211
212	bool (*is_allow_self_refresh_enabled)(struct hubbub *hubbub);
213	void (*allow_self_refresh_control)(struct hubbub *hubbub, bool allow);
214
215	bool (*verify_allow_pstate_change_high)(struct hubbub *hubbub);
216
217	void (*apply_DEDCN21_147_wa)(struct hubbub *hubbub);
218
219	void (*force_wm_propagate_to_pipes)(struct hubbub *hubbub);
220
221	void (*hubbub_read_state)(struct hubbub *hubbub, struct dcn_hubbub_state *hubbub_state);
222
223	void (*force_pstate_change_control)(struct hubbub *hubbub, bool force, bool allow);
224
225	void (*init_watermarks)(struct hubbub *hubbub);
226
227	void (*hubbub_read_reg_state)(struct hubbub *hubbub, struct dcn_hubbub_reg_state *hubbub_reg_state);
228
229	/**
230	 * @program_det_size:
231	 *
232	 * DE-Tile buffers (DET) is a memory that is used to convert the tiled
233	 * data into linear, which the rest of the display can use to generate
234	 * the graphics output. One of the main features of this component is
235	 * that each pipe has a configurable DET buffer which means that when a
236	 * pipe is not enabled, the device can assign the memory to other
237	 * enabled pipes to try to be more efficient.
238	 *
239	 * DET logic is handled by dchubbub. Some ASICs provide a feature named
240	 * Configurable Return Buffer (CRB) segments which can be allocated to
241	 * compressed or detiled buffers.
242	 */
243	void (*program_det_size)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_in_kbyte);
244	void (*wait_for_det_apply)(struct hubbub *hubbub, int hubp_inst);
245	void (*program_compbuf_size)(struct hubbub *hubbub, unsigned compbuf_size_kb, bool safe_to_increase);
246	void (*init_crb)(struct hubbub *hubbub);
247	void (*force_usr_retraining_allow)(struct hubbub *hubbub, bool allow);
248	void (*set_request_limit)(struct hubbub *hubbub, int memory_channel_count, int words_per_channel);
249	void (*dchubbub_init)(struct hubbub *hubbub);
250	void (*get_mall_en)(struct hubbub *hubbub, unsigned int *mall_in_use);
251	void (*program_det_segments)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_seg);
252	void (*program_compbuf_segments)(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase);
253	void (*wait_for_det_update)(struct hubbub *hubbub, int hubp_inst);
254	bool (*program_arbiter)(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower);
255	void (*dchvm_init)(struct hubbub *hubbub);
256
257	struct hubbub_perfmon_funcs {
258		void (*reset)(struct hubbub *hubbub);
259		void (*start_measuring_max_memory_latency_ns)(
260				struct hubbub *hubbub);
261		uint32_t (*get_max_memory_latency_ns)(struct hubbub *hubbub,
262				uint32_t refclk_mhz, uint32_t *sample_count);
263		void (*start_measuring_average_memory_latency_ns)(
264				struct hubbub *hubbub);
265		uint32_t (*get_average_memory_latency_ns)(struct hubbub *hubbub,
266				uint32_t refclk_mhz, uint32_t *sample_count);
267		void (*start_measuring_urgent_ramp_latency_ns)(
268				struct hubbub *hubbub,
269				const struct hubbub_urgent_latency_params *params);
270		uint32_t (*get_urgent_ramp_latency_ns)(struct hubbub *hubbub,
271				uint32_t refclk_mhz);
272		void (*start_measuring_unbounded_bandwidth_mbps)(
273				struct hubbub *hubbub);
274		uint32_t (*get_unbounded_bandwidth_mbps)(struct hubbub *hubbub,
275				uint32_t refclk_mhz, uint32_t *duration_ns);
276		void (*start_measuring_average_bandwidth_mbps)(
277				struct hubbub *hubbub);
278		uint32_t (*get_average_bandwidth_mbps)(struct hubbub *hubbub,
279				uint32_t refclk_mhz, uint32_t min_duration_ns,
280				uint32_t *duration_ns);
281	} perfmon;
282
283	struct hubbub_qos_funcs {
284		void (*force_display_nominal_profile)(struct hubbub *hubbub);
285		void (*force_display_urgent_profile)(struct hubbub *hubbub);
286		void (*reset_display_qos_profile)(struct hubbub *hubbub);
287	} qos;
288};
289
290struct hubbub {
291	const struct hubbub_funcs *funcs;
292	struct dc_context *ctx;
293	bool riommu_active;
294};
295
296#endif