hw_sequencer_private.h

  1/*
  2 * Copyright 2015 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#ifndef __DC_HW_SEQUENCER_PRIVATE_H__
 27#define __DC_HW_SEQUENCER_PRIVATE_H__
 28
 29#include "dc_types.h"
 30#include "hw_sequencer.h"
 31
 32enum pipe_gating_control {
 33	PIPE_GATING_CONTROL_DISABLE = 0,
 34	PIPE_GATING_CONTROL_ENABLE,
 35	PIPE_GATING_CONTROL_INIT
 36};
 37
 38struct dce_hwseq_wa {
 39	bool blnd_crtc_trigger;
 40	bool DEGVIDCN10_253;
 41	bool false_optc_underflow;
 42	bool DEGVIDCN10_254;
 43	bool DEGVIDCN21;
 44	bool disallow_self_refresh_during_multi_plane_transition;
 45	bool dp_hpo_and_otg_sequence;
 46	bool wait_hubpret_read_start_during_mpo_transition;
 47};
 48
 49struct hwseq_wa_state {
 50	bool DEGVIDCN10_253_applied;
 51	bool disallow_self_refresh_during_multi_plane_transition_applied;
 52	unsigned int disallow_self_refresh_during_multi_plane_transition_applied_on_frame;
 53	bool skip_blank_stream;
 54};
 55
 56struct pipe_ctx;
 57struct dc_state;
 58struct dc_stream_status;
 59struct dc_writeback_info;
 60struct dchub_init_data;
 61struct dc_static_screen_params;
 62struct resource_pool;
 63struct resource_context;
 64struct stream_resource;
 65struct dc_phy_addr_space_config;
 66struct dc_virtual_addr_space_config;
 67struct hubp;
 68struct dpp;
 69struct dce_hwseq;
 70struct timing_generator;
 71struct tg_color;
 72struct output_pixel_processor;
 73struct mpcc_blnd_cfg;
 74
 75struct hwseq_private_funcs {
 76
 77	void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
 78	void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
 79	void (*init_pipes)(struct dc *dc, struct dc_state *context);
 80	void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);
 81	void (*plane_atomic_disconnect)(struct dc *dc,
 82			struct dc_state *state,
 83			struct pipe_ctx *pipe_ctx);
 84	void (*plane_atomic_disconnect_sequence)(struct dc *dc,
 85			struct dc_state *state,
 86			struct pipe_ctx *pipe_ctx,
 87			struct block_sequence_state *seq_state);
 88	void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);
 89	void (*update_mpcc_sequence)(struct dc *dc, struct pipe_ctx *pipe_ctx,
 90			struct block_sequence_state *seq_state);
 91	bool (*set_input_transfer_func)(struct dc *dc,
 92				struct pipe_ctx *pipe_ctx,
 93				const struct dc_plane_state *plane_state);
 94	bool (*set_output_transfer_func)(struct dc *dc,
 95				struct pipe_ctx *pipe_ctx,
 96				const struct dc_stream_state *stream);
 97	void (*power_down)(struct dc *dc);
 98	void (*enable_display_pipe_clock_gating)(struct dc_context *ctx,
 99					bool clock_gating);
100	bool (*enable_display_power_gating)(struct dc *dc,
101					uint8_t controller_id,
102					struct dc_bios *dcb,
103					enum pipe_gating_control power_gating);
104	void (*blank_pixel_data)(struct dc *dc,
105			struct pipe_ctx *pipe_ctx,
106			bool blank);
107	void (*blank_pixel_data_sequence)(struct dc *dc,
108			struct pipe_ctx *pipe_ctx,
109			bool blank,
110			struct block_sequence_state *seq_state);
111	enum dc_status (*enable_stream_timing)(
112			struct pipe_ctx *pipe_ctx,
113			struct dc_state *context,
114			struct dc *dc);
115	void (*edp_backlight_control)(struct dc_link *link,
116			bool enable);
117	void (*setup_vupdate_interrupt)(struct dc *dc,
118			struct pipe_ctx *pipe_ctx);
119	void (*setup_vupdate_interrupt_sequence)(struct dc *dc, struct pipe_ctx *pipe_ctx,
120		struct block_sequence_state *seq_state);
121	bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
122	void (*init_blank)(struct dc *dc, struct timing_generator *tg);
123	void (*disable_vga)(struct dce_hwseq *hws);
124	void (*bios_golden_init)(struct dc *dc);
125	void (*plane_atomic_power_down)(struct dc *dc,
126			struct dpp *dpp,
127			struct hubp *hubp);
128	void (*plane_atomic_power_down_sequence)(struct dc *dc,
129			struct dpp *dpp,
130			struct hubp *hubp,
131			struct block_sequence_state *seq_state);
132	void (*plane_atomic_disable)(struct dc *dc, struct pipe_ctx *pipe_ctx);
133	void (*enable_power_gating_plane)(struct dce_hwseq *hws,
134		bool enable);
135	void (*dpp_root_clock_control)(
136			struct dce_hwseq *hws,
137			unsigned int dpp_inst,
138			bool clock_on);
139	void (*dpstream_root_clock_control)(
140			struct dce_hwseq *hws,
141			unsigned int dpp_inst,
142			bool clock_on);
143	void (*physymclk_root_clock_control)(
144			struct dce_hwseq *hws,
145			unsigned int phy_inst,
146			bool clock_on);
147	void (*dpp_pg_control)(struct dce_hwseq *hws,
148			unsigned int dpp_inst,
149			bool power_on);
150	void (*hubp_pg_control)(struct dce_hwseq *hws,
151			unsigned int hubp_inst,
152			bool power_on);
153	void (*dsc_pg_control)(struct dce_hwseq *hws,
154			unsigned int dsc_inst,
155			bool power_on);
156	bool (*dsc_pg_status)(struct dce_hwseq *hws,
157			unsigned int dsc_inst);
158	void (*update_odm)(struct dc *dc, struct dc_state *context,
159			struct pipe_ctx *pipe_ctx);
160	void (*update_odm_sequence)(struct dc *dc, struct dc_state *context,
161			struct pipe_ctx *pipe_ctx, struct block_sequence_state *seq_state);
162	void (*program_all_writeback_pipes_in_tree)(struct dc *dc,
163			const struct dc_stream_state *stream,
164			struct dc_state *context);
165	void (*program_all_writeback_pipes_in_tree_sequence)(
166			struct dc *dc,
167			const struct dc_stream_state *stream,
168			struct dc_state *context,
169			struct block_sequence_state *seq_state);
170	bool (*s0i3_golden_init_wa)(struct dc *dc);
171	void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx);
172	void (*set_hdr_multiplier_sequence)(struct pipe_ctx *pipe_ctx,
173			struct block_sequence_state *seq_state);
174	void (*verify_allow_pstate_change_high)(struct dc *dc);
175	void (*verify_allow_pstate_change_high_sequence)(struct dc *dc,
176		struct block_sequence_state *seq_state);
177	void (*program_pipe)(struct dc *dc,
178			struct pipe_ctx *pipe_ctx,
179			struct dc_state *context);
180	void (*program_pipe_sequence)(
181		struct dc *dc,
182		struct pipe_ctx *pipe_ctx,
183		struct dc_state *context,
184		struct block_sequence_state *seq_state);
185	bool (*wait_for_blank_complete)(struct output_pixel_processor *opp);
186	void (*dccg_init)(struct dce_hwseq *hws);
187	bool (*set_blend_lut)(struct pipe_ctx *pipe_ctx,
188			const struct dc_plane_state *plane_state);
189	bool (*set_shaper_3dlut)(struct pipe_ctx *pipe_ctx,
190			const struct dc_plane_state *plane_state);
191	bool (*set_mcm_luts)(struct pipe_ctx *pipe_ctx,
192			const struct dc_plane_state *plane_state);
193	void (*PLAT_58856_wa)(struct dc_state *context,
194			struct pipe_ctx *pipe_ctx);
195	void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);
196	void (*enable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx,
197			       struct dc_state *context);
198	void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context);
199	void (*program_mall_pipe_config_sequence)(struct dc *dc, struct dc_state *context,
200			struct block_sequence_state *seq_state);
201	void (*update_force_pstate)(struct dc *dc, struct dc_state *context);
202	void (*update_mall_sel)(struct dc *dc, struct dc_state *context);
203	unsigned int (*calculate_dccg_k1_k2_values)(struct pipe_ctx *pipe_ctx,
204			unsigned int *k1_div,
205			unsigned int *k2_div);
206	void (*resync_fifo_dccg_dio)(struct dce_hwseq *hws, struct dc *dc,
207			struct dc_state *context,
208			unsigned int current_pipe_idx);
209	enum dc_status (*apply_single_controller_ctx_to_hw)(
210			struct pipe_ctx *pipe_ctx,
211			struct dc_state *context,
212			struct dc *dc);
213	bool (*is_dp_dig_pixel_rate_div_policy)(struct pipe_ctx *pipe_ctx);
214	void (*reset_back_end_for_pipe)(struct dc *dc,
215			struct pipe_ctx *pipe_ctx,
216			struct dc_state *context);
217	void (*populate_mcm_luts)(struct dc *dc,
218			struct pipe_ctx *pipe_ctx,
219			struct dc_cm2_func_luts mcm_luts,
220			bool lut_bank_a);
221	void (*perform_3dlut_wa_unlock)(struct pipe_ctx *pipe_ctx);
222	void (*wait_for_pipe_update_if_needed)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface_update_only);
223	void (*set_wait_for_update_needed_for_pipe)(struct dc *dc, struct pipe_ctx *pipe_ctx);
224	void (*dc_ip_request_cntl)(struct dc *dc, bool enable);
225};
226
227struct dce_hwseq {
228	struct dc_context *ctx;
229	const struct dce_hwseq_registers *regs;
230	const struct dce_hwseq_shift *shifts;
231	const struct dce_hwseq_mask *masks;
232	struct dce_hwseq_wa wa;
233	struct hwseq_wa_state wa_state;
234	struct hwseq_private_funcs funcs;
235
236	PHYSICAL_ADDRESS_LOC fb_base;
237	PHYSICAL_ADDRESS_LOC fb_top;
238	PHYSICAL_ADDRESS_LOC fb_offset;
239	PHYSICAL_ADDRESS_LOC uma_top;
240};
241
242#endif /* __DC_HW_SEQUENCER_PRIVATE_H__ */