dcn401_init.c

  1// SPDX-License-Identifier: MIT
  2//
  3// Copyright 2024 Advanced Micro Devices, Inc.
  4
  5#include "dce110/dce110_hwseq.h"
  6#include "dcn10/dcn10_hwseq.h"
  7#include "dcn20/dcn20_hwseq.h"
  8#include "dcn21/dcn21_hwseq.h"
  9#include "dcn30/dcn30_hwseq.h"
 10#include "dcn31/dcn31_hwseq.h"
 11#include "dcn32/dcn32_hwseq.h"
 12#include "dcn35/dcn35_hwseq.h"
 13#include "dcn401/dcn401_hwseq.h"
 14#include "dcn401_init.h"
 15
 16static const struct hw_sequencer_funcs dcn401_funcs = {
 17	.program_gamut_remap = dcn401_program_gamut_remap,
 18	.init_hw = dcn401_init_hw,
 19	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
 20	.apply_ctx_for_surface = NULL,
 21	.program_front_end_for_ctx = dcn401_program_front_end_for_ctx,
 22	.clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
 23	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
 24	.post_unlock_program_front_end = dcn401_post_unlock_program_front_end,
 25	.update_plane_addr = dcn20_update_plane_addr,
 26	.update_dchub = dcn10_update_dchub,
 27	.update_pending_status = dcn10_update_pending_status,
 28	.program_output_csc = dcn20_program_output_csc,
 29	.trigger_3dlut_dma_load = dcn401_trigger_3dlut_dma_load,
 30	.enable_accelerated_mode = dce110_enable_accelerated_mode,
 31	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
 32	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
 33	.update_info_frame = dcn31_update_info_frame,
 34	.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
 35	.enable_stream = dcn401_enable_stream,
 36	.disable_stream = dce110_disable_stream,
 37	.unblank_stream = dcn401_unblank_stream,
 38	.blank_stream = dce110_blank_stream,
 39	.enable_audio_stream = dce110_enable_audio_stream,
 40	.disable_audio_stream = dce110_disable_audio_stream,
 41	.disable_plane = dcn20_disable_plane,
 42	.disable_plane_sequence = dcn401_disable_plane_sequence,
 43	.pipe_control_lock = dcn20_pipe_control_lock,
 44	.interdependent_update_lock = dcn401_interdependent_update_lock,
 45	.cursor_lock = dcn10_cursor_lock,
 46	.prepare_bandwidth = dcn401_prepare_bandwidth,
 47	.optimize_bandwidth = dcn401_optimize_bandwidth,
 48	.update_bandwidth = dcn401_update_bandwidth,
 49	.set_drr = dcn10_set_drr,
 50	.get_position = dcn10_get_position,
 51	.set_static_screen_control = dcn31_set_static_screen_control,
 52	.setup_stereo = dcn10_setup_stereo,
 53	.set_avmute = dcn30_set_avmute,
 54	.log_hw_state = dcn10_log_hw_state,
 55	.get_hw_state = dcn10_get_hw_state,
 56	.clear_status_bits = dcn10_clear_status_bits,
 57	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
 58	.wait_for_mpcc_disconnect_sequence = dcn401_wait_for_mpcc_disconnect_sequence,
 59	.edp_backlight_control = dce110_edp_backlight_control,
 60	.edp_power_control = dce110_edp_power_control,
 61	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
 62	.edp_wait_for_T12 = dce110_edp_wait_for_T12,
 63	.set_cursor_position = dcn401_set_cursor_position,
 64	.set_cursor_attribute = dcn10_set_cursor_attribute,
 65	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
 66	.abort_cursor_offload_update = dcn35_abort_cursor_offload_update,
 67	.begin_cursor_offload_update = dcn35_begin_cursor_offload_update,
 68	.commit_cursor_offload_update = dcn35_commit_cursor_offload_update,
 69	.update_cursor_offload_pipe = dcn401_update_cursor_offload_pipe,
 70	.notify_cursor_offload_drr_update = dcn35_notify_cursor_offload_drr_update,
 71	.program_cursor_offload_now = dcn35_program_cursor_offload_now,
 72	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
 73	.set_clock = dcn10_set_clock,
 74	.get_clock = dcn10_get_clock,
 75	.program_triplebuffer = dcn20_program_triple_buffer,
 76	.enable_writeback = dcn30_enable_writeback,
 77	.disable_writeback = dcn30_disable_writeback,
 78	.update_writeback = dcn30_update_writeback,
 79	.dmdata_status_done = dcn20_dmdata_status_done,
 80	.program_dmdata_engine = dcn30_program_dmdata_engine,
 81	.set_dmdata_attributes = dcn20_set_dmdata_attributes,
 82	.init_sys_ctx = dcn20_init_sys_ctx,
 83	.init_vm_ctx = dcn20_init_vm_ctx,
 84	.set_flip_control_gsl = dcn20_set_flip_control_gsl,
 85	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
 86	.calc_vupdate_position = dcn10_calc_vupdate_position,
 87	.apply_idle_power_optimizations = dcn401_apply_idle_power_optimizations,
 88	.does_plane_fit_in_mall = NULL,
 89	.set_backlight_level = dcn31_set_backlight_level,
 90	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
 91	.hardware_release = dcn401_hardware_release,
 92	.set_pipe = dcn21_set_pipe,
 93	.enable_lvds_link_output = dce110_enable_lvds_link_output,
 94	.enable_tmds_link_output = dce110_enable_tmds_link_output,
 95	.enable_dp_link_output = dce110_enable_dp_link_output,
 96	.disable_link_output = dcn401_disable_link_output,
 97	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
 98	.get_dcc_en_bits = dcn10_get_dcc_en_bits,
 99	.enable_phantom_streams = dcn32_enable_phantom_streams,
100	.disable_phantom_streams = dcn32_disable_phantom_streams,
101	.update_visual_confirm_color = dcn10_update_visual_confirm_color,
102	.update_phantom_vp_position = dcn32_update_phantom_vp_position,
103	.update_dsc_pg = dcn32_update_dsc_pg,
104	.apply_update_flags_for_phantom = dcn32_apply_update_flags_for_phantom,
105	.wait_for_dcc_meta_propagation = dcn401_wait_for_dcc_meta_propagation,
106	.is_pipe_topology_transition_seamless = dcn32_is_pipe_topology_transition_seamless,
107	.dmub_hw_control_lock = dcn401_dmub_hw_control_lock,
108	.fams2_update_config = dcn401_fams2_update_config,
109	.dmub_hw_control_lock_fast = dcn401_dmub_hw_control_lock_fast,
110	.program_outstanding_updates = dcn401_program_outstanding_updates,
111	.wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates,
112	.detect_pipe_changes = dcn401_detect_pipe_changes,
113	.enable_plane = dcn20_enable_plane,
114	.enable_plane_sequence = dcn401_enable_plane_sequence,
115	.update_dchubp_dpp = dcn20_update_dchubp_dpp,
116	.update_dchubp_dpp_sequence = dcn401_update_dchubp_dpp_sequence,
117	.post_unlock_reset_opp = dcn20_post_unlock_reset_opp,
118	.post_unlock_reset_opp_sequence = dcn401_post_unlock_reset_opp_sequence,
119	.get_underflow_debug_data = dcn30_get_underflow_debug_data,
120};
121
122static const struct hwseq_private_funcs dcn401_private_funcs = {
123	.init_pipes = dcn10_init_pipes,
124	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
125	.plane_atomic_disconnect_sequence = dcn401_plane_atomic_disconnect_sequence,
126	.update_mpcc = dcn20_update_mpcc,
127	.update_mpcc_sequence = dcn401_update_mpcc_sequence,
128	.set_input_transfer_func = dcn32_set_input_transfer_func,
129	.set_output_transfer_func = dcn401_set_output_transfer_func,
130	.power_down = dce110_power_down,
131	.enable_display_power_gating = dcn10_dummy_display_power_gating,
132	.blank_pixel_data = dcn20_blank_pixel_data,
133	.blank_pixel_data_sequence = dcn401_blank_pixel_data_sequence,
134	.reset_hw_ctx_wrap = dcn401_reset_hw_ctx_wrap,
135	.enable_stream_timing = dcn401_enable_stream_timing,
136	.edp_backlight_control = dce110_edp_backlight_control,
137	.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
138	.setup_vupdate_interrupt_sequence = dcn401_setup_vupdate_interrupt_sequence,
139	.did_underflow_occur = dcn10_did_underflow_occur,
140	.init_blank = dcn32_init_blank,
141	.disable_vga = dcn20_disable_vga,
142	.bios_golden_init = dcn10_bios_golden_init,
143	.plane_atomic_disable = dcn20_plane_atomic_disable,
144	.plane_atomic_power_down = dcn401_plane_atomic_power_down,
145	.plane_atomic_power_down_sequence = dcn401_plane_atomic_power_down_sequence,
146	.enable_power_gating_plane = dcn32_enable_power_gating_plane,
147	.hubp_pg_control = dcn32_hubp_pg_control,
148	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
149	.program_all_writeback_pipes_in_tree_sequence = dcn401_program_all_writeback_pipes_in_tree_sequence,
150	.update_odm = dcn401_update_odm,
151	.update_odm_sequence = dcn401_update_odm_sequence,
152	.dsc_pg_control = dcn32_dsc_pg_control,
153	.dsc_pg_status = dcn32_dsc_pg_status,
154	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
155	.set_hdr_multiplier_sequence = dcn401_set_hdr_multiplier_sequence,
156	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
157	.verify_allow_pstate_change_high_sequence = dcn401_verify_allow_pstate_change_high_sequence,
158	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
159	.dccg_init = dcn20_dccg_init,
160	.set_mcm_luts = dcn401_set_mcm_luts,
161	.program_mall_pipe_config = dcn32_program_mall_pipe_config,
162	.program_mall_pipe_config_sequence = dcn401_program_mall_pipe_config_sequence,
163	.update_mall_sel = dcn32_update_mall_sel,
164	.calculate_dccg_k1_k2_values = NULL,
165	.apply_single_controller_ctx_to_hw = dce110_apply_single_controller_ctx_to_hw,
166	.reset_back_end_for_pipe = dcn401_reset_back_end_for_pipe,
167	.populate_mcm_luts = NULL,
168	.perform_3dlut_wa_unlock = dcn401_perform_3dlut_wa_unlock,
169	.program_pipe_sequence = dcn401_program_pipe_sequence,
170	.dc_ip_request_cntl = dcn401_dc_ip_request_cntl,
171};
172
173void dcn401_hw_sequencer_init_functions(struct dc *dc)
174{
175	dc->hwss = dcn401_funcs;
176	dc->hwseq->funcs = dcn401_private_funcs;
177}