dcn401_hwseq.h

  1// SPDX-License-Identifier: MIT
  2//
  3// Copyright 2024 Advanced Micro Devices, Inc.
  4
  5#ifndef __DC_HWSS_DCN401_H__
  6#define __DC_HWSS_DCN401_H__
  7
  8#include "inc/core_types.h"
  9#include "dc.h"
 10#include "dc_stream.h"
 11#include "hw_sequencer_private.h"
 12#include "hwss/hw_sequencer.h"
 13#include "dcn401/dcn401_dccg.h"
 14
 15struct dc;
 16
 17enum ips_ono_state {
 18	ONO_ON = 0,
 19	ONO_ON_IN_PROGRESS = 1,
 20	ONO_OFF = 2,
 21	ONO_OFF_IN_PROGRESS = 3
 22};
 23
 24struct ips_ono_region_state {
 25	/**
 26	 * @desire_pwr_state: desired power state based on configured value
 27	 */
 28	uint32_t desire_pwr_state;
 29	/**
 30	 * @current_pwr_state: current power gate status
 31	 */
 32	uint32_t current_pwr_state;
 33};
 34
 35void dcn401_program_gamut_remap(struct pipe_ctx *pipe_ctx);
 36
 37void dcn401_init_hw(struct dc *dc);
 38
 39bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,
 40				const struct dc_plane_state *plane_state);
 41bool dcn401_set_output_transfer_func(struct dc *dc,
 42				struct pipe_ctx *pipe_ctx,
 43				const struct dc_stream_state *stream);
 44void dcn401_trigger_3dlut_dma_load(struct dc *dc,
 45				struct pipe_ctx *pipe_ctx);
 46void dcn401_calculate_dccg_tmds_div_value(struct pipe_ctx *pipe_ctx,
 47				unsigned int *tmds_div);
 48enum dc_status dcn401_enable_stream_timing(
 49				struct pipe_ctx *pipe_ctx,
 50				struct dc_state *context,
 51				struct dc *dc);
 52void dcn401_enable_stream(struct pipe_ctx *pipe_ctx);
 53void dcn401_populate_mcm_luts(struct dc *dc,
 54		struct pipe_ctx *pipe_ctx,
 55		struct dc_cm2_func_luts mcm_luts,
 56		bool lut_bank_a);
 57void dcn401_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);
 58
 59void dcn401_disable_link_output(struct dc_link *link,
 60		const struct link_resource *link_res,
 61		enum signal_type signal);
 62
 63void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx);
 64
 65bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable);
 66
 67void dcn401_wait_for_dcc_meta_propagation(const struct dc *dc,
 68		const struct pipe_ctx *top_pipe_to_program);
 69
 70void dcn401_prepare_bandwidth(struct dc *dc,
 71		struct dc_state *context);
 72
 73void dcn401_optimize_bandwidth(
 74		struct dc *dc,
 75		struct dc_state *context);
 76
 77void dcn401_dmub_hw_control_lock(struct dc *dc,
 78		struct dc_state *context,
 79		bool lock);
 80void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable);
 81void dcn401_dmub_hw_control_lock_fast(union block_sequence_params *params);
 82void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx, struct dc_link_settings *link_settings);
 83void dcn401_hardware_release(struct dc *dc);
 84void dcn401_update_odm(struct dc *dc, struct dc_state *context,
 85		struct pipe_ctx *otg_master);
 86void dcn401_update_odm_sequence(struct dc *dc, struct dc_state *context,
 87		struct pipe_ctx *otg_master, struct block_sequence_state *seq_state);
 88void adjust_hotspot_between_slices_for_2x_magnify(uint32_t cursor_width, struct dc_cursor_position *pos_cpy);
 89void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master);
 90void dcn401_interdependent_update_lock(struct dc *dc, struct dc_state *context, bool lock);
 91void dcn401_program_outstanding_updates(struct dc *dc, struct dc_state *context);
 92void dcn401_reset_back_end_for_pipe(
 93		struct dc *dc,
 94		struct pipe_ctx *pipe_ctx,
 95		struct dc_state *context);
 96void dcn401_reset_hw_ctx_wrap(
 97		struct dc *dc,
 98		struct dc_state *context);
 99void dcn401_program_pipe(
100	struct dc *dc,
101	struct pipe_ctx *pipe_ctx,
102	struct dc_state *context);
103void dcn401_program_pipe_sequence(
104	struct dc *dc,
105	struct pipe_ctx *pipe_ctx,
106	struct dc_state *context,
107	struct block_sequence_state *seq_state);
108void dcn401_perform_3dlut_wa_unlock(struct pipe_ctx *pipe_ctx);
109void dcn401_program_front_end_for_ctx(struct dc *dc, struct dc_state *context);
110void dcn401_post_unlock_program_front_end(struct dc *dc, struct dc_state *context);
111bool dcn401_update_bandwidth(struct dc *dc, struct dc_state *context);
112void dcn401_detect_pipe_changes(
113	struct dc_state *old_state,
114	struct dc_state *new_state,
115	struct pipe_ctx *old_pipe,
116	struct pipe_ctx *new_pipe);
117void dcn401_plane_atomic_power_down(struct dc *dc,
118		struct dpp *dpp,
119		struct hubp *hubp);
120void dcn401_plane_atomic_power_down_sequence(struct dc *dc,
121		struct dpp *dpp,
122		struct hubp *hubp,
123		struct block_sequence_state *seq_state);
124void dcn401_plane_atomic_disconnect_sequence(struct dc *dc,
125		struct dc_state *state,
126		struct pipe_ctx *pipe_ctx,
127		struct block_sequence_state *seq_state);
128void dcn401_blank_pixel_data_sequence(
129	struct dc *dc,
130	struct pipe_ctx *pipe_ctx,
131	bool blank,
132	struct block_sequence_state *seq_state);
133void dcn401_initialize_min_clocks(struct dc *dc);
134void dcn401_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe);
135
136void dcn401_program_all_writeback_pipes_in_tree_sequence(
137		struct dc *dc,
138		const struct dc_stream_state *stream,
139		struct dc_state *context,
140		struct block_sequence_state *seq_state);
141
142void dcn401_enable_writeback_sequence(
143		struct dc *dc,
144		struct dc_writeback_info *wb_info,
145		struct dc_state *context,
146		int mpcc_inst,
147		struct block_sequence_state *seq_state);
148
149void dcn401_disable_writeback_sequence(
150		struct dc *dc,
151		struct dc_writeback_info *wb_info,
152		struct block_sequence_state *seq_state);
153
154void dcn401_update_writeback_sequence(
155		struct dc *dc,
156		struct dc_writeback_info *wb_info,
157		struct dc_state *context,
158		struct block_sequence_state *seq_state);
159
160void dcn401_setup_gsl_group_as_lock_sequence(
161		const struct dc *dc,
162		struct pipe_ctx *pipe_ctx,
163		bool enable,
164		struct block_sequence_state *seq_state);
165
166void dcn401_disable_plane_sequence(
167		struct dc *dc,
168		struct dc_state *state,
169		struct pipe_ctx *pipe_ctx,
170		struct block_sequence_state *seq_state);
171
172void dcn401_post_unlock_reset_opp_sequence(
173		struct dc *dc,
174		struct pipe_ctx *opp_head,
175		struct block_sequence_state *seq_state);
176
177void dcn401_dc_ip_request_cntl(struct dc *dc, bool enable);
178
179void dcn401_enable_plane_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx,
180				 struct dc_state *context,
181				 struct block_sequence_state *seq_state);
182
183void dcn401_update_dchubp_dpp_sequence(struct dc *dc,
184				       struct pipe_ctx *pipe_ctx,
185				       struct dc_state *context,
186				       struct block_sequence_state *seq_state);
187
188void dcn401_update_mpcc_sequence(struct dc *dc,
189				struct pipe_ctx *pipe_ctx,
190				struct block_sequence_state *seq_state);
191
192void dcn401_wait_for_mpcc_disconnect_sequence(
193		struct dc *dc,
194		struct resource_pool *res_pool,
195		struct pipe_ctx *pipe_ctx,
196		struct block_sequence_state *seq_state);
197
198void dcn401_setup_vupdate_interrupt_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx,
199		struct block_sequence_state *seq_state);
200
201void dcn401_set_hdr_multiplier_sequence(struct pipe_ctx *pipe_ctx,
202		struct block_sequence_state *seq_state);
203
204void dcn401_program_mall_pipe_config_sequence(struct dc *dc, struct dc_state *context,
205		struct block_sequence_state *seq_state);
206
207void dcn401_verify_allow_pstate_change_high_sequence(struct dc *dc,
208		struct block_sequence_state *seq_state);
209
210bool dcn401_hw_wa_force_recovery_sequence(struct dc *dc,
211		struct block_sequence_state *seq_state);
212
213#endif /* __DC_HWSS_DCN401_H__ */