dcn35_init.c

  1/* SPDX-License-Identifier: MIT */
  2/*
  3 * Copyright 2023 Advanced Micro Devices, Inc.
  4 *
  5 * Permission is hereby granted, free of charge, to any person obtaining a
  6 * copy of this software and associated documentation files (the "Software"),
  7 * to deal in the Software without restriction, including without limitation
  8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9 * and/or sell copies of the Software, and to permit persons to whom the
 10 * Software is furnished to do so, subject to the following conditions:
 11 *
 12 * The above copyright notice and this permission notice shall be included in
 13 * all copies or substantial portions of the Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 21 * OTHER DEALINGS IN THE SOFTWARE.
 22 *
 23 * Authors: AMD
 24 *
 25 */
 26
 27#include "dce110/dce110_hwseq.h"
 28#include "dcn10/dcn10_hwseq.h"
 29#include "dcn20/dcn20_hwseq.h"
 30#include "dcn21/dcn21_hwseq.h"
 31#include "dcn30/dcn30_hwseq.h"
 32#include "dcn301/dcn301_hwseq.h"
 33#include "dcn31/dcn31_hwseq.h"
 34#include "dcn314/dcn314_hwseq.h"
 35#include "dcn32/dcn32_hwseq.h"
 36#include "dcn35/dcn35_hwseq.h"
 37
 38#include "dcn35_init.h"
 39
 40static const struct hw_sequencer_funcs dcn35_funcs = {
 41	.program_gamut_remap = dcn30_program_gamut_remap,
 42	.init_hw = dcn35_init_hw,
 43	.power_down_on_boot = dcn35_power_down_on_boot,
 44	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
 45	.apply_ctx_for_surface = NULL,
 46	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
 47	.clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
 48	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
 49	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
 50	.update_plane_addr = dcn20_update_plane_addr,
 51	.update_dchub = dcn10_update_dchub,
 52	.update_pending_status = dcn10_update_pending_status,
 53	.program_output_csc = dcn20_program_output_csc,
 54	.enable_accelerated_mode = dce110_enable_accelerated_mode,
 55	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
 56	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
 57	.update_info_frame = dcn31_update_info_frame,
 58	.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
 59	.enable_stream = dcn20_enable_stream,
 60	.disable_stream = dce110_disable_stream,
 61	.unblank_stream = dcn32_unblank_stream,
 62	.blank_stream = dce110_blank_stream,
 63	.enable_audio_stream = dce110_enable_audio_stream,
 64	.disable_audio_stream = dce110_disable_audio_stream,
 65	.disable_plane = dcn35_disable_plane,
 66	.disable_pixel_data = dcn20_disable_pixel_data,
 67	.pipe_control_lock = dcn20_pipe_control_lock,
 68	.interdependent_update_lock = dcn10_lock_all_pipes,
 69	.cursor_lock = dcn10_cursor_lock,
 70	.prepare_bandwidth = dcn35_prepare_bandwidth,
 71	.optimize_bandwidth = dcn35_optimize_bandwidth,
 72	.update_bandwidth = dcn20_update_bandwidth,
 73	.set_drr = dcn35_set_drr,
 74	.get_position = dcn10_get_position,
 75	.set_static_screen_control = dcn35_set_static_screen_control,
 76	.setup_stereo = dcn10_setup_stereo,
 77	.set_avmute = dcn30_set_avmute,
 78	.log_hw_state = dcn10_log_hw_state,
 79	.get_hw_state = dcn10_get_hw_state,
 80	.clear_status_bits = dcn10_clear_status_bits,
 81	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
 82	.edp_backlight_control = dce110_edp_backlight_control,
 83	.edp_power_control = dce110_edp_power_control,
 84	.edp_wait_for_T12 = dce110_edp_wait_for_T12,
 85	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
 86	.set_cursor_position = dcn10_set_cursor_position,
 87	.set_cursor_attribute = dcn10_set_cursor_attribute,
 88	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
 89	.abort_cursor_offload_update = dcn35_abort_cursor_offload_update,
 90	.begin_cursor_offload_update = dcn35_begin_cursor_offload_update,
 91	.commit_cursor_offload_update = dcn35_commit_cursor_offload_update,
 92	.update_cursor_offload_pipe = dcn35_update_cursor_offload_pipe,
 93	.notify_cursor_offload_drr_update = dcn35_notify_cursor_offload_drr_update,
 94	.program_cursor_offload_now = dcn35_program_cursor_offload_now,
 95	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
 96	.set_clock = dcn10_set_clock,
 97	.get_clock = dcn10_get_clock,
 98	.program_triplebuffer = dcn20_program_triple_buffer,
 99	.enable_writeback = dcn30_enable_writeback,
100	.disable_writeback = dcn30_disable_writeback,
101	.update_writeback = dcn30_update_writeback,
102	.dmdata_status_done = dcn20_dmdata_status_done,
103	.program_dmdata_engine = dcn30_program_dmdata_engine,
104	.set_dmdata_attributes = dcn20_set_dmdata_attributes,
105	.init_sys_ctx = dcn31_init_sys_ctx,
106	.init_vm_ctx = dcn20_init_vm_ctx,
107	.set_flip_control_gsl = dcn20_set_flip_control_gsl,
108	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
109	.calc_vupdate_position = dcn10_calc_vupdate_position,
110	.set_backlight_level = dcn31_set_backlight_level,
111	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
112	.set_pipe = dcn21_set_pipe,
113	.enable_lvds_link_output = dce110_enable_lvds_link_output,
114	.enable_tmds_link_output = dce110_enable_tmds_link_output,
115	.enable_dp_link_output = dce110_enable_dp_link_output,
116	.disable_link_output = dcn35_disable_link_output,
117	.z10_restore = dcn35_z10_restore,
118	.z10_save_init = dcn31_z10_save_init,
119	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
120	.optimize_pwr_state = dcn21_optimize_pwr_state,
121	.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
122	.update_visual_confirm_color = dcn10_update_visual_confirm_color,
123	.apply_idle_power_optimizations = dcn35_apply_idle_power_optimizations,
124	.calc_blocks_to_gate = dcn35_calc_blocks_to_gate,
125	.calc_blocks_to_ungate = dcn35_calc_blocks_to_ungate,
126	.hw_block_power_up = dcn35_hw_block_power_up,
127	.hw_block_power_down = dcn35_hw_block_power_down,
128	.root_clock_control = dcn35_root_clock_control,
129	.set_long_vtotal = dcn35_set_long_vblank,
130	.calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider,
131	.hardware_release = dcn35_hardware_release,
132	.detect_pipe_changes = dcn20_detect_pipe_changes,
133	.enable_plane = dcn20_enable_plane,
134	.update_dchubp_dpp = dcn20_update_dchubp_dpp,
135	.post_unlock_reset_opp = dcn20_post_unlock_reset_opp,
136	.get_underflow_debug_data = dcn30_get_underflow_debug_data,
137};
138
139static const struct hwseq_private_funcs dcn35_private_funcs = {
140	.init_pipes = dcn35_init_pipes,
141	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
142	.update_mpcc = dcn20_update_mpcc,
143	.set_input_transfer_func = dcn32_set_input_transfer_func,
144	.set_output_transfer_func = dcn32_set_output_transfer_func,
145	.power_down = dce110_power_down,
146	.enable_display_power_gating = dcn10_dummy_display_power_gating,
147	.blank_pixel_data = dcn20_blank_pixel_data,
148	.reset_hw_ctx_wrap = dcn31_reset_hw_ctx_wrap,
149	.enable_stream_timing = dcn20_enable_stream_timing,
150	.edp_backlight_control = dce110_edp_backlight_control,
151	.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
152	.did_underflow_occur = dcn10_did_underflow_occur,
153	.init_blank = dcn20_init_blank,
154	.disable_vga = NULL,
155	.bios_golden_init = dcn10_bios_golden_init,
156	.plane_atomic_disable = dcn35_plane_atomic_disable,
157	//.plane_atomic_disable = dcn20_plane_atomic_disable,/*todo*/
158	//.hubp_pg_control = dcn35_hubp_pg_control,
159	.dpp_root_clock_control = dcn35_dpp_root_clock_control,
160	.dpstream_root_clock_control = dcn35_dpstream_root_clock_control,
161	.physymclk_root_clock_control = dcn35_physymclk_root_clock_control,
162	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
163	.update_odm = dcn35_update_odm,
164	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
165	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
166	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
167	.dccg_init = dcn20_dccg_init,
168	.set_mcm_luts = dcn32_set_mcm_luts,
169	.setup_hpo_hw_control = dcn35_setup_hpo_hw_control,
170	.calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values,
171	.resync_fifo_dccg_dio = dcn314_resync_fifo_dccg_dio,
172	.is_dp_dig_pixel_rate_div_policy = dcn35_is_dp_dig_pixel_rate_div_policy,
173	.dsc_pg_status = dcn32_dsc_pg_status,
174	.enable_plane = dcn35_enable_plane,
175	.wait_for_pipe_update_if_needed = dcn10_wait_for_pipe_update_if_needed,
176	.set_wait_for_update_needed_for_pipe = dcn10_set_wait_for_update_needed_for_pipe,
177};
178
179void dcn35_hw_sequencer_construct(struct dc *dc)
180{
181	dc->hwss = dcn35_funcs;
182	dc->hwseq->funcs = dcn35_private_funcs;
183
184}