dcn35_hwseq.h

  1/* SPDX-License-Identifier: MIT */
  2/*
  3 * Copyright 2023 Advanced Micro Devices, Inc.
  4 *
  5 * Permission is hereby granted, free of charge, to any person obtaining a
  6 * copy of this software and associated documentation files (the "Software"),
  7 * to deal in the Software without restriction, including without limitation
  8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9 * and/or sell copies of the Software, and to permit persons to whom the
 10 * Software is furnished to do so, subject to the following conditions:
 11 *
 12 * The above copyright notice and this permission notice shall be included in
 13 * all copies or substantial portions of the Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 21 * OTHER DEALINGS IN THE SOFTWARE.
 22 *
 23 * Authors: AMD
 24 *
 25 */
 26
 27#ifndef __DC_HWSS_DCN35_H__
 28#define __DC_HWSS_DCN35_H__
 29
 30#include "hw_sequencer_private.h"
 31
 32struct dc;
 33
 34void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
 35
 36void dcn35_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);
 37
 38void dcn35_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);
 39
 40void dcn35_dpstream_root_clock_control(struct dce_hwseq *hws, unsigned int dp_hpo_inst, bool clock_on);
 41
 42void dcn35_physymclk_root_clock_control(struct dce_hwseq *hws, unsigned int phy_inst, bool clock_on);
 43
 44void dcn35_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);
 45
 46void dcn35_set_dmu_fgcg(struct dce_hwseq *hws, bool enable);
 47
 48void dcn35_init_hw(struct dc *dc);
 49
 50void dcn35_disable_link_output(struct dc_link *link,
 51		const struct link_resource *link_res,
 52		enum signal_type signal);
 53
 54void dcn35_power_down_on_boot(struct dc *dc);
 55
 56bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable);
 57
 58void dcn35_z10_restore(const struct dc *dc);
 59
 60void dcn35_init_pipes(struct dc *dc, struct dc_state *context);
 61void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);
 62void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,
 63			       struct dc_state *context);
 64void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
 65
 66void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,
 67	struct pg_block_update *update_state);
 68void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,
 69	struct pg_block_update *update_state);
 70void dcn35_hw_block_power_up(struct dc *dc,
 71	struct pg_block_update *update_state);
 72void dcn35_hw_block_power_down(struct dc *dc,
 73	struct pg_block_update *update_state);
 74void dcn35_root_clock_control(struct dc *dc,
 75	struct pg_block_update *update_state, bool power_on);
 76
 77void dcn35_prepare_bandwidth(
 78		struct dc *dc,
 79		struct dc_state *context);
 80
 81void dcn35_optimize_bandwidth(
 82		struct dc *dc,
 83		struct dc_state *context);
 84
 85void dcn35_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);
 86void dcn35_dsc_pg_control(
 87		struct dce_hwseq *hws,
 88		unsigned int dsc_inst,
 89		bool power_on);
 90
 91void dcn35_set_drr(struct pipe_ctx **pipe_ctx,
 92		int num_pipes, struct dc_crtc_timing_adjust adjust);
 93
 94void dcn35_set_static_screen_control(struct pipe_ctx **pipe_ctx,
 95		int num_pipes, const struct dc_static_screen_params *params);
 96
 97void dcn35_set_long_vblank(struct pipe_ctx **pipe_ctx,
 98		int num_pipes, uint32_t v_total_min, uint32_t v_total_max);
 99
100bool dcn35_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);
101
102void dcn35_hardware_release(struct dc *dc);
103
104void dcn35_abort_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe);
105void dcn35_begin_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe);
106void dcn35_commit_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe);
107void dcn35_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe);
108void dcn35_notify_cursor_offload_drr_update(struct dc *dc, struct dc_state *context,
109					    const struct dc_stream_state *stream);
110void dcn35_program_cursor_offload_now(struct dc *dc, const struct pipe_ctx *pipe);
111void dcn35_disable_link_output(struct dc_link *link,
112		const struct link_resource *link_res,
113		enum signal_type signal);
114
115#endif /* __DC_HWSS_DCN35_H__ */