dcn314_hwseq.c

  1// SPDX-License-Identifier: MIT
  2/*
  3 * Copyright 2022 Advanced Micro Devices, Inc.
  4 *
  5 * Permission is hereby granted, free of charge, to any person obtaining a
  6 * copy of this software and associated documentation files (the "Software"),
  7 * to deal in the Software without restriction, including without limitation
  8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9 * and/or sell copies of the Software, and to permit persons to whom the
 10 * Software is furnished to do so, subject to the following conditions:
 11 *
 12 * The above copyright notice and this permission notice shall be included in
 13 * all copies or substantial portions of the Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 21 * OTHER DEALINGS IN THE SOFTWARE.
 22 *
 23 * Authors: AMD
 24 *
 25 */
 26
 27
 28#include "dm_services.h"
 29#include "dm_helpers.h"
 30#include "core_types.h"
 31#include "resource.h"
 32#include "dccg.h"
 33#include "dce/dce_hwseq.h"
 34#include "clk_mgr.h"
 35#include "reg_helper.h"
 36#include "abm.h"
 37#include "hubp.h"
 38#include "dchubbub.h"
 39#include "timing_generator.h"
 40#include "opp.h"
 41#include "ipp.h"
 42#include "mpc.h"
 43#include "mcif_wb.h"
 44#include "dc_dmub_srv.h"
 45#include "dcn314_hwseq.h"
 46#include "link_hwss.h"
 47#include "dpcd_defs.h"
 48#include "dce/dmub_outbox.h"
 49#include "link_service.h"
 50#include "dcn10/dcn10_hwseq.h"
 51#include "inc/link_enc_cfg.h"
 52#include "dcn30/dcn30_vpg.h"
 53#include "dce/dce_i2c_hw.h"
 54#include "dsc.h"
 55#include "dcn20/dcn20_optc.h"
 56#include "dcn30/dcn30_cm_common.h"
 57
 58#define DC_LOGGER_INIT(logger)
 59
 60#define CTX \
 61	hws->ctx
 62#define REG(reg)\
 63	hws->regs->reg
 64#define DC_LOGGER \
 65	stream->ctx->logger
 66
 67
 68#undef FN
 69#define FN(reg_name, field_name) \
 70	hws->shifts->field_name, hws->masks->field_name
 71
 72static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
 73{
 74	struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
 75	struct dc_stream_state *stream = pipe_ctx->stream;
 76	struct pipe_ctx *odm_pipe;
 77	int opp_cnt = 1;
 78
 79	ASSERT(dsc);
 80	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
 81		opp_cnt++;
 82
 83	if (enable) {
 84		struct dsc_config dsc_cfg;
 85		struct dsc_optc_config dsc_optc_cfg = {0};
 86		enum optc_dsc_mode optc_dsc_mode;
 87		struct dcn_dsc_state dsc_state = {0};
 88
 89		if (!dsc) {
 90			DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);
 91			return;
 92		}
 93
 94		if (dsc->funcs->dsc_read_state) {
 95			dsc->funcs->dsc_read_state(dsc, &dsc_state);
 96			if (!dsc_state.dsc_fw_en) {
 97				DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);
 98				return;
 99			}
100		}
101
102		/* Enable DSC hw block */
103		dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
104		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
105		dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
106		dsc_cfg.color_depth = stream->timing.display_color_depth;
107		dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
108		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
109		ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
110		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
111		dsc_cfg.dsc_padding = 0;
112
113		dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
114		dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
115		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
116			struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;
117
118			ASSERT(odm_dsc);
119			odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);
120			odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
121		}
122		dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
123		dsc_cfg.pic_width *= opp_cnt;
124
125		optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
126
127		/* Enable DSC in OPTC */
128		DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
129		pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
130							optc_dsc_mode,
131							dsc_optc_cfg.bytes_per_pixel,
132							dsc_optc_cfg.slice_width);
133	} else {
134		/* disable DSC in OPTC */
135		pipe_ctx->stream_res.tg->funcs->set_dsc_config(
136				pipe_ctx->stream_res.tg,
137				OPTC_DSC_DISABLED, 0, 0);
138
139		/* disable DSC block */
140		dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
141		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
142			ASSERT(odm_pipe->stream_res.dsc);
143			odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);
144		}
145	}
146}
147
148// Given any pipe_ctx, return the total ODM combine factor, and optionally return
149// the OPPids which are used
150static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)
151{
152	unsigned int opp_count = 1;
153	struct pipe_ctx *odm_pipe;
154
155	// First get to the top pipe
156	for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)
157		;
158
159	// First pipe is always used
160	if (opp_instances)
161		opp_instances[0] = odm_pipe->stream_res.opp->inst;
162
163	// Find and count odm pipes, if any
164	for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
165		if (opp_instances)
166			opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;
167		opp_count++;
168	}
169
170	return opp_count;
171}
172
173void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
174{
175	struct pipe_ctx *odm_pipe;
176	int opp_cnt = 0;
177	int opp_inst[MAX_PIPES] = {0};
178	int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);
179	int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);
180	struct mpc *mpc = dc->res_pool->mpc;
181	int i;
182
183	opp_cnt = get_odm_config(pipe_ctx, opp_inst);
184
185	if (opp_cnt > 1)
186		pipe_ctx->stream_res.tg->funcs->set_odm_combine(
187				pipe_ctx->stream_res.tg,
188				opp_inst, opp_cnt,
189				odm_slice_width, last_odm_slice_width);
190	else
191		pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
192				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
193
194	if (mpc->funcs->set_out_rate_control) {
195		for (i = 0; i < opp_cnt; ++i) {
196			mpc->funcs->set_out_rate_control(
197					mpc, opp_inst[i],
198					false,
199					0,
200					NULL);
201		}
202	}
203
204	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
205		odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
206				odm_pipe->stream_res.opp,
207				true);
208	}
209
210	if (pipe_ctx->stream_res.dsc) {
211		struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
212
213		update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);
214
215		/* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */
216		if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&
217				current_pipe_ctx->next_odm_pipe->stream_res.dsc) {
218			struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc;
219			/* disconnect DSC block from stream */
220			dsc->funcs->dsc_disconnect(dsc);
221		}
222	}
223}
224
225void dcn314_dsc_pg_control(
226		struct dce_hwseq *hws,
227		unsigned int dsc_inst,
228		bool power_on)
229{
230	uint32_t power_gate = power_on ? 0 : 1;
231	uint32_t pwr_status = power_on ? 0 : 2;
232	uint32_t org_ip_request_cntl = 0;
233
234	if (hws->ctx->dc->debug.disable_dsc_power_gate)
235		return;
236
237	if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc &&
238		hws->ctx->dc->res_pool->dccg->funcs->enable_dsc &&
239		power_on)
240		hws->ctx->dc->res_pool->dccg->funcs->enable_dsc(
241			hws->ctx->dc->res_pool->dccg, dsc_inst);
242
243	REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
244	if (org_ip_request_cntl == 0)
245		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
246
247	switch (dsc_inst) {
248	case 0: /* DSC0 */
249		REG_UPDATE(DOMAIN16_PG_CONFIG,
250				DOMAIN_POWER_GATE, power_gate);
251
252		REG_WAIT(DOMAIN16_PG_STATUS,
253				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
254				1, 1000);
255		break;
256	case 1: /* DSC1 */
257		REG_UPDATE(DOMAIN17_PG_CONFIG,
258				DOMAIN_POWER_GATE, power_gate);
259
260		REG_WAIT(DOMAIN17_PG_STATUS,
261				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
262				1, 1000);
263		break;
264	case 2: /* DSC2 */
265		REG_UPDATE(DOMAIN18_PG_CONFIG,
266				DOMAIN_POWER_GATE, power_gate);
267
268		REG_WAIT(DOMAIN18_PG_STATUS,
269				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
270				1, 1000);
271		break;
272	case 3: /* DSC3 */
273		REG_UPDATE(DOMAIN19_PG_CONFIG,
274				DOMAIN_POWER_GATE, power_gate);
275
276		REG_WAIT(DOMAIN19_PG_STATUS,
277				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
278				1, 1000);
279		break;
280	default:
281		BREAK_TO_DEBUGGER();
282		break;
283	}
284
285	if (org_ip_request_cntl == 0)
286		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
287
288	if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) {
289		if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on)
290			hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(
291				hws->ctx->dc->res_pool->dccg, dsc_inst);
292	}
293
294}
295
296void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable)
297{
298	bool force_on = true; /* disable power gating */
299	uint32_t org_ip_request_cntl = 0;
300
301	if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate)
302		force_on = false;
303
304	REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
305	if (org_ip_request_cntl == 0)
306		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
307	/* DCHUBP0/1/2/3/4/5 */
308	REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
309	REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
310	/* DPP0/1/2/3/4/5 */
311	REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
312	REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
313
314	force_on = true; /* disable power gating */
315	if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate)
316		force_on = false;
317
318	/* DCS0/1/2/3/4 */
319	REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
320	REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
321	REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
322	REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
323
324	if (org_ip_request_cntl == 0)
325		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
326}
327
328unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
329{
330	struct dc_stream_state *stream = pipe_ctx->stream;
331	unsigned int odm_combine_factor = 0;
332	bool two_pix_per_container = false;
333
334	two_pix_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);
335	odm_combine_factor = get_odm_config(pipe_ctx, NULL);
336
337	if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
338		*k1_div = PIXEL_RATE_DIV_BY_1;
339		*k2_div = PIXEL_RATE_DIV_BY_1;
340	} else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) {
341		*k1_div = PIXEL_RATE_DIV_BY_1;
342		if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
343			*k2_div = PIXEL_RATE_DIV_BY_2;
344		else
345			*k2_div = PIXEL_RATE_DIV_BY_4;
346	} else if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) {
347		if (two_pix_per_container) {
348			*k1_div = PIXEL_RATE_DIV_BY_1;
349			*k2_div = PIXEL_RATE_DIV_BY_2;
350		} else {
351			*k1_div = PIXEL_RATE_DIV_BY_1;
352			*k2_div = PIXEL_RATE_DIV_BY_4;
353			if (odm_combine_factor == 2)
354				*k2_div = PIXEL_RATE_DIV_BY_2;
355		}
356	}
357
358	if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
359		ASSERT(false);
360
361	return odm_combine_factor;
362}
363
364void dcn314_calculate_pix_rate_divider(
365		struct dc *dc,
366		struct dc_state *context,
367		const struct dc_stream_state *stream)
368{
369	struct dce_hwseq *hws = dc->hwseq;
370	struct pipe_ctx *pipe_ctx = NULL;
371	unsigned int k1_div = PIXEL_RATE_DIV_NA;
372	unsigned int k2_div = PIXEL_RATE_DIV_NA;
373
374	pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
375
376	if (pipe_ctx) {
377		if (hws->funcs.calculate_dccg_k1_k2_values)
378			hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
379
380		pipe_ctx->pixel_rate_divider.div_factor1 = k1_div;
381		pipe_ctx->pixel_rate_divider.div_factor2 = k2_div;
382	}
383}
384
385static bool dcn314_is_pipe_dig_fifo_on(struct pipe_ctx *pipe)
386{
387	return pipe && pipe->stream
388		// Check dig's otg instance.
389		&& pipe->stream_res.stream_enc
390		&& pipe->stream_res.stream_enc->funcs->dig_source_otg
391		&& pipe->stream_res.tg->inst == pipe->stream_res.stream_enc->funcs->dig_source_otg(pipe->stream_res.stream_enc)
392		&& pipe->stream->link && pipe->stream->link->link_enc
393		&& pipe->stream->link->link_enc->funcs->is_dig_enabled
394		&& pipe->stream->link->link_enc->funcs->is_dig_enabled(pipe->stream->link->link_enc)
395		&& pipe->stream_res.stream_enc->funcs->is_fifo_enabled
396		&& pipe->stream_res.stream_enc->funcs->is_fifo_enabled(pipe->stream_res.stream_enc);
397}
398
399void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx)
400{
401	unsigned int i;
402	struct pipe_ctx *pipe = NULL;
403	bool otg_disabled[MAX_PIPES] = {false};
404
405	for (i = 0; i < dc->res_pool->pipe_count; i++) {
406		if (i <= current_pipe_idx) {
407			pipe = &context->res_ctx.pipe_ctx[i];
408		} else {
409			pipe = &dc->current_state->res_ctx.pipe_ctx[i];
410		}
411
412		if (pipe->top_pipe || pipe->prev_odm_pipe)
413			continue;
414
415		if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal)) &&
416			!pipe->stream->apply_seamless_boot_optimization &&
417			!pipe->stream->apply_edp_fast_boot_optimization) {
418			if (dcn314_is_pipe_dig_fifo_on(pipe))
419				continue;
420			pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);
421			reset_sync_context_for_pipe(dc, context, i);
422			otg_disabled[i] = true;
423		}
424	}
425
426	hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);
427
428	for (i = 0; i < dc->res_pool->pipe_count; i++) {
429		if (i <= current_pipe_idx)
430			pipe = &context->res_ctx.pipe_ctx[i];
431		else
432			pipe = &dc->current_state->res_ctx.pipe_ctx[i];
433
434		if (otg_disabled[i]) {
435			int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst };
436			int opp_cnt = 1;
437			int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe, true);
438			int odm_slice_width = resource_get_odm_slice_dst_width(pipe, false);
439			struct pipe_ctx *odm_pipe;
440
441			for (odm_pipe = pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
442				opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
443				opp_cnt++;
444			}
445			if (opp_cnt > 1)
446				pipe->stream_res.tg->funcs->set_odm_combine(
447						pipe->stream_res.tg,
448						opp_inst, opp_cnt,
449						odm_slice_width,
450						last_odm_slice_width);
451			pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
452		}
453	}
454}
455
456void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on)
457{
458	if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpp)
459		return;
460
461	if (hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control)
462		hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control(
463			hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on);
464}
465
466static void apply_symclk_on_tx_off_wa(struct dc_link *link)
467{
468	/* There are use cases where SYMCLK is referenced by OTG. For instance
469	 * for TMDS signal, OTG relies SYMCLK even if TX video output is off.
470	 * However current link interface will power off PHY when disabling link
471	 * output. This will turn off SYMCLK generated by PHY. The workaround is
472	 * to identify such case where SYMCLK is still in use by OTG when we
473	 * power off PHY. When this is detected, we will temporarily power PHY
474	 * back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling
475	 * program_pix_clk interface. When OTG is disabled, we will then power
476	 * off PHY by calling disable link output again.
477	 *
478	 * In future dcn generations, we plan to rework transmitter control
479	 * interface so that we could have an option to set SYMCLK ON TX OFF
480	 * state in one step without this workaround
481	 */
482
483	struct dc *dc = link->ctx->dc;
484	struct pipe_ctx *pipe_ctx = NULL;
485	uint8_t i;
486
487	if (link->phy_state.symclk_ref_cnts.otg > 0) {
488		for (i = 0; i < MAX_PIPES; i++) {
489			pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
490			if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) {
491				pipe_ctx->clock_source->funcs->program_pix_clk(
492						pipe_ctx->clock_source,
493						&pipe_ctx->stream_res.pix_clk_params,
494						dc->link_srv->dp_get_encoding_format(
495								&pipe_ctx->link_config.dp_link_settings),
496						&pipe_ctx->pll_settings);
497				link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
498				break;
499			}
500		}
501	}
502}
503
504void dcn314_disable_link_output(struct dc_link *link,
505		const struct link_resource *link_res,
506		enum signal_type signal)
507{
508	struct dc *dc = link->ctx->dc;
509	const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
510	struct dmcu *dmcu = dc->res_pool->dmcu;
511
512	if (signal == SIGNAL_TYPE_EDP &&
513			link->dc->hwss.edp_backlight_control &&
514			!link->skip_implict_edp_power_control)
515		link->dc->hwss.edp_backlight_control(link, false);
516	else if (dmcu != NULL && dmcu->funcs->lock_phy)
517		dmcu->funcs->lock_phy(dmcu);
518
519	link_hwss->disable_link_output(link, link_res, signal);
520	link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
521	/*
522	 * Add the logic to extract BOTH power up and power down sequences
523	 * from enable/disable link output and only call edp panel control
524	 * in enable_link_dp and disable_link_dp once.
525	 */
526	if (dmcu != NULL && dmcu->funcs->unlock_phy)
527		dmcu->funcs->unlock_phy(dmcu);
528	dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
529
530	apply_symclk_on_tx_off_wa(link);
531}
532
533/**
534 * dcn314_dpp_pg_control - DPP power gate control.
535 *
536 * @hws: dce_hwseq reference.
537 * @dpp_inst: DPP instance reference.
538 * @power_on: true if we want to enable power gate, false otherwise.
539 *
540 * Enable or disable power gate in the specific DPP instance.
541 * If power gating is disabled, will force disable cursor in the DPP instance.
542 */
543void dcn314_dpp_pg_control(
544		struct dce_hwseq *hws,
545		unsigned int dpp_inst,
546		bool power_on)
547{
548	uint32_t power_gate = power_on ? 0 : 1;
549	uint32_t pwr_status = power_on ? 0 : 2;
550
551
552	if (hws->ctx->dc->debug.disable_dpp_power_gate) {
553		/* Workaround for DCN314 with disabled power gating */
554		if (!power_on) {
555
556			/* Force disable cursor if power gating is disabled */
557			struct dpp *dpp = hws->ctx->dc->res_pool->dpps[dpp_inst];
558			if (dpp && dpp->funcs->dpp_force_disable_cursor)
559				dpp->funcs->dpp_force_disable_cursor(dpp);
560		}
561		return;
562	}
563	if (REG(DOMAIN1_PG_CONFIG) == 0)
564		return;
565
566	switch (dpp_inst) {
567	case 0: /* DPP0 */
568		REG_UPDATE(DOMAIN1_PG_CONFIG,
569				DOMAIN1_POWER_GATE, power_gate);
570
571		REG_WAIT(DOMAIN1_PG_STATUS,
572				DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
573				1, 1000);
574		break;
575	case 1: /* DPP1 */
576		REG_UPDATE(DOMAIN3_PG_CONFIG,
577				DOMAIN3_POWER_GATE, power_gate);
578
579		REG_WAIT(DOMAIN3_PG_STATUS,
580				DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
581				1, 1000);
582		break;
583	case 2: /* DPP2 */
584		REG_UPDATE(DOMAIN5_PG_CONFIG,
585				DOMAIN5_POWER_GATE, power_gate);
586
587		REG_WAIT(DOMAIN5_PG_STATUS,
588				DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
589				1, 1000);
590		break;
591	case 3: /* DPP3 */
592		REG_UPDATE(DOMAIN7_PG_CONFIG,
593				DOMAIN7_POWER_GATE, power_gate);
594
595		REG_WAIT(DOMAIN7_PG_STATUS,
596				DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
597				1, 1000);
598		break;
599	default:
600		BREAK_TO_DEBUGGER();
601		break;
602	}
603}