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dcn30_hwseq.h

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linux-6.19.14/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h C
  1/*
  2* Copyright 2020 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#ifndef __DC_HWSS_DCN30_H__
 27#define __DC_HWSS_DCN30_H__
 28
 29#include "hw_sequencer_private.h"
 30
 31struct dc;
 32struct dc_underflow_debug_data;
 33
 34void dcn30_init_hw(struct dc *dc);
 35void dcn30_program_all_writeback_pipes_in_tree(
 36		struct dc *dc,
 37		const struct dc_stream_state *stream,
 38		struct dc_state *context);
 39void dcn30_update_writeback(
 40		struct dc *dc,
 41		struct dc_writeback_info *wb_info,
 42		struct dc_state *context);
 43void dcn30_enable_writeback(
 44		struct dc *dc,
 45		struct dc_writeback_info *wb_info,
 46		struct dc_state *context);
 47void dcn30_disable_writeback(
 48		struct dc *dc,
 49		unsigned int dwb_pipe_inst);
 50
 51bool dcn30_mmhubbub_warmup(
 52	struct dc *dc,
 53	unsigned int num_dwb,
 54	struct dc_writeback_info *wb_info);
 55
 56void dcn30_log_color_state(struct dc *dc,
 57			   struct dc_log_buffer_ctx *log_ctx);
 58
 59bool dcn30_set_blend_lut(struct pipe_ctx *pipe_ctx,
 60		const struct dc_plane_state *plane_state);
 61
 62bool dcn30_set_input_transfer_func(struct dc *dc,
 63				struct pipe_ctx *pipe_ctx,
 64				const struct dc_plane_state *plane_state);
 65
 66void dcn30_program_gamut_remap(struct pipe_ctx *pipe_ctx);
 67
 68bool dcn30_set_output_transfer_func(struct dc *dc,
 69				struct pipe_ctx *pipe_ctx,
 70				const struct dc_stream_state *stream);
 71void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
 72void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx);
 73void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx);
 74
 75bool dcn30_does_plane_fit_in_mall(struct dc *dc,
 76		unsigned int pitch,
 77		unsigned int height,
 78		enum surface_pixel_format format,
 79		struct dc_cursor_attributes *cursor_attr);
 80
 81bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable);
 82
 83void dcn30_hardware_release(struct dc *dc);
 84
 85void dcn30_set_disp_pattern_generator(const struct dc *dc,
 86		struct pipe_ctx *pipe_ctx,
 87		enum controller_dp_test_pattern test_pattern,
 88		enum controller_dp_color_space color_space,
 89		enum dc_color_depth color_depth,
 90		const struct tg_color *solid_color,
 91		int width, int height, int offset);
 92
 93void dcn30_set_hubp_blank(const struct dc *dc,
 94		struct pipe_ctx *pipe_ctx,
 95		bool blank_enable);
 96
 97void dcn30_prepare_bandwidth(struct dc *dc,
 98	struct dc_state *context);
 99
100void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx);
101
102void dcn30_get_underflow_debug_data(const struct dc *dc,
103	struct timing_generator *tg,
104	struct dc_underflow_debug_data *out_data);
105
106#endif /* __DC_HWSS_DCN30_H__ */
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