dcn20_hubp.h

  1/*
  2 * Copyright 2012-17 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#ifndef __DC_MEM_INPUT_DCN20_H__
 27#define __DC_MEM_INPUT_DCN20_H__
 28
 29#include "../dcn10/dcn10_hubp.h"
 30
 31#define TO_DCN20_HUBP(hubp)\
 32	container_of(hubp, struct dcn20_hubp, base)
 33
 34#define HUBP_REG_LIST_DCN2_COMMON(id)\
 35	HUBP_REG_LIST_DCN(id),\
 36	HUBP_REG_LIST_DCN_VM(id),\
 37	SRI(PREFETCH_SETTINGS, HUBPREQ, id),\
 38	SRI(PREFETCH_SETTINGS_C, HUBPREQ, id),\
 39	SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id),\
 40	SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id),\
 41	SRI(CURSOR_SETTINGS, HUBPREQ, id), \
 42	SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \
 43	SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \
 44	SRI(CURSOR_SIZE, CURSOR0_, id), \
 45	SRI(CURSOR_CONTROL, CURSOR0_, id), \
 46	SRI(CURSOR_POSITION, CURSOR0_, id), \
 47	SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \
 48	SRI(CURSOR_DST_OFFSET, CURSOR0_, id), \
 49	SRI(DMDATA_ADDRESS_HIGH, CURSOR0_, id), \
 50	SRI(DMDATA_ADDRESS_LOW, CURSOR0_, id), \
 51	SRI(DMDATA_CNTL, CURSOR0_, id), \
 52	SRI(DMDATA_SW_CNTL, CURSOR0_, id), \
 53	SRI(DMDATA_QOS_CNTL, CURSOR0_, id), \
 54	SRI(DMDATA_SW_DATA, CURSOR0_, id), \
 55	SRI(DMDATA_STATUS, CURSOR0_, id),\
 56	SRI(FLIP_PARAMETERS_0, HUBPREQ, id),\
 57	SRI(FLIP_PARAMETERS_1, HUBPREQ, id),\
 58	SRI(FLIP_PARAMETERS_2, HUBPREQ, id),\
 59	SRI(DCN_CUR1_TTU_CNTL0, HUBPREQ, id),\
 60	SRI(DCN_CUR1_TTU_CNTL1, HUBPREQ, id),\
 61	SRI(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \
 62	SRI(VMID_SETTINGS_0, HUBPREQ, id)
 63
 64#define HUBP_REG_LIST_DCN20(id)\
 65	HUBP_REG_LIST_DCN2_COMMON(id),\
 66	SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
 67	SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB)
 68
 69#define HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON(mask_sh)\
 70	HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\
 71	HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
 72	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
 73	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
 74	HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\
 75	HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\
 76	HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\
 77	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\
 78	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\
 79	HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \
 80	HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
 81	HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
 82	HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
 83	HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
 84	HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
 85	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
 86	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
 87	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
 88	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
 89	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
 90	HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
 91	HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
 92	HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
 93	HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
 94	HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
 95	HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \
 96	HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \
 97	HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \
 98	HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \
 99	HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \
100	HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \
101	HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \
102	HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \
103	HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \
104	HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \
105	HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \
106	HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\
107	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\
108	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\
109	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\
110	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\
111	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\
112	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\
113	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\
114	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\
115	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\
116	HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh)
117
118/*DCN2.x and DCN1.x*/
119#define HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh)\
120	HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON(mask_sh),\
121	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
122	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\
123	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh)
124
125/*DCN2.0 specific*/
126#define HUBP_MASK_SH_LIST_DCN20(mask_sh)\
127	HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh),\
128	HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
129	HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
130	HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh)
131
132/*DCN2.x */
133#define DCN2_HUBP_REG_COMMON_VARIABLE_LIST \
134	HUBP_COMMON_REG_VARIABLE_LIST; \
135	uint32_t DMDATA_ADDRESS_HIGH; \
136	uint32_t DMDATA_ADDRESS_LOW; \
137	uint32_t DMDATA_CNTL; \
138	uint32_t DMDATA_SW_CNTL; \
139	uint32_t DMDATA_QOS_CNTL; \
140	uint32_t DMDATA_SW_DATA; \
141	uint32_t DMDATA_STATUS;\
142	uint32_t DCSURF_FLIP_CONTROL2;\
143	uint32_t FLIP_PARAMETERS_0;\
144	uint32_t FLIP_PARAMETERS_1;\
145	uint32_t FLIP_PARAMETERS_2;\
146	uint32_t DCN_CUR1_TTU_CNTL0;\
147	uint32_t DCN_CUR1_TTU_CNTL1;\
148	uint32_t VMID_SETTINGS_0;\
149	uint32_t DST_Y_DELTA_DRQ_LIMIT
150
151/*shared with dcn3.x*/
152#define DCN21_HUBP_REG_COMMON_VARIABLE_LIST \
153	DCN2_HUBP_REG_COMMON_VARIABLE_LIST; \
154	uint32_t FLIP_PARAMETERS_3;\
155	uint32_t FLIP_PARAMETERS_4;\
156	uint32_t FLIP_PARAMETERS_5;\
157	uint32_t FLIP_PARAMETERS_6;\
158	uint32_t VBLANK_PARAMETERS_5;\
159	uint32_t VBLANK_PARAMETERS_6
160
161#define DCN30_HUBP_REG_COMMON_VARIABLE_LIST \
162	DCN21_HUBP_REG_COMMON_VARIABLE_LIST;\
163	uint32_t DCN_DMDATA_VM_CNTL
164
165#define DCN32_HUBP_REG_COMMON_VARIABLE_LIST \
166	DCN30_HUBP_REG_COMMON_VARIABLE_LIST;\
167	uint32_t DCHUBP_MALL_CONFIG;\
168	uint32_t DCHUBP_VMPG_CONFIG;\
169	uint32_t UCLK_PSTATE_FORCE
170
171#define DCN401_HUBP_REG_COMMON_VARIABLE_LIST \
172	DCN32_HUBP_REG_COMMON_VARIABLE_LIST;\
173	uint32_t _3DLUT_FL_BIAS_SCALE;\
174	uint32_t _3DLUT_FL_CONFIG;\
175	uint32_t HUBP_3DLUT_ADDRESS_HIGH;\
176	uint32_t HUBP_3DLUT_ADDRESS_LOW;\
177	uint32_t HUBP_3DLUT_CONTROL;\
178	uint32_t HUBP_3DLUT_DLG_PARAM;\
179	uint32_t DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE;\
180	uint32_t DCHUBP_MCACHEID_CONFIG;\
181	uint32_t DCHUBP_MALL_SUB_VP;\
182	uint32_t DCHUBP_ADDR_CONFIG;\
183	uint32_t HUBP_MALL_STATUS
184
185#define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \
186	DCN_HUBP_REG_FIELD_BASE_LIST(type); \
187	type DMDATA_ADDRESS_HIGH;\
188	type DMDATA_MODE;\
189	type DMDATA_UPDATED;\
190	type DMDATA_REPEAT;\
191	type DMDATA_SIZE;\
192	type DMDATA_SW_UPDATED;\
193	type DMDATA_SW_REPEAT;\
194	type DMDATA_SW_SIZE;\
195	type DMDATA_QOS_MODE;\
196	type DMDATA_QOS_LEVEL;\
197	type DMDATA_DL_DELTA;\
198	type DMDATA_DONE;\
199	type DST_Y_PER_VM_FLIP;\
200	type DST_Y_PER_ROW_FLIP;\
201	type REFCYC_PER_PTE_GROUP_FLIP_L;\
202	type REFCYC_PER_META_CHUNK_FLIP_L;\
203	type HUBP_VREADY_AT_OR_AFTER_VSYNC;\
204	type HUBP_DISABLE_STOP_DATA_DURING_VM;\
205	type HUBPREQ_MASTER_UPDATE_LOCK_STATUS;\
206	type SURFACE_GSL_ENABLE;\
207	type SURFACE_TRIPLE_BUFFER_ENABLE;\
208	type VMID
209
210#define DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type) \
211	DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type);\
212	type REFCYC_PER_VM_GROUP_FLIP;\
213	type REFCYC_PER_VM_REQ_FLIP;\
214	type REFCYC_PER_VM_GROUP_VBLANK;\
215	type REFCYC_PER_VM_REQ_VBLANK;\
216	type REFCYC_PER_PTE_GROUP_FLIP_C; \
217	type REFCYC_PER_META_CHUNK_FLIP_C; \
218	type VM_GROUP_SIZE
219
220#define DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type) \
221	DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type);\
222	type PRIMARY_SURFACE_DCC_IND_BLK;\
223	type SECONDARY_SURFACE_DCC_IND_BLK;\
224	type PRIMARY_SURFACE_DCC_IND_BLK_C;\
225	type SECONDARY_SURFACE_DCC_IND_BLK_C;\
226	type ALPHA_PLANE_EN;\
227	type REFCYC_PER_VM_DMDATA;\
228	type DMDATA_VM_FAULT_STATUS;\
229	type DMDATA_VM_FAULT_STATUS_CLEAR; \
230	type DMDATA_VM_UNDERFLOW_STATUS;\
231	type DMDATA_VM_LATE_STATUS;\
232	type DMDATA_VM_UNDERFLOW_STATUS_CLEAR; \
233	type DMDATA_VM_DONE; \
234	type CROSSBAR_SRC_Y_G; \
235	type CROSSBAR_SRC_ALPHA; \
236	type PACK_3TO2_ELEMENT_DISABLE; \
237	type ROW_TTU_MODE; \
238	type NUM_PKRS
239
240#define DCN31_HUBP_REG_FIELD_VARIABLE_LIST(type) \
241	DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type);\
242	type HUBP_UNBOUNDED_REQ_MODE;\
243	type CURSOR_REQ_MODE;\
244	type HUBP_SOFT_RESET
245
246#define DCN32_HUBP_REG_FIELD_VARIABLE_LIST(type) \
247	DCN31_HUBP_REG_FIELD_VARIABLE_LIST(type);\
248	type USE_MALL_SEL; \
249	type USE_MALL_FOR_CURSOR;\
250	type VMPG_SIZE; \
251	type PTE_BUFFER_MODE; \
252	type BIGK_FRAGMENT_SIZE; \
253	type FORCE_ONE_ROW_FOR_FRAME; \
254	type DATA_UCLK_PSTATE_FORCE_EN; \
255	type DATA_UCLK_PSTATE_FORCE_VALUE; \
256	type CURSOR_UCLK_PSTATE_FORCE_EN; \
257	type CURSOR_UCLK_PSTATE_FORCE_VALUE
258
259#define DCN401_HUBP_REG_FIELD_VARIABLE_LIST(type) \
260	DCN32_HUBP_REG_FIELD_VARIABLE_LIST(type);\
261	type MALL_PREF_CMD_TYPE; \
262	type MALL_PREF_MODE; \
263	type HUBP0_3DLUT_FL_MODE; \
264	type HUBP0_3DLUT_FL_FORMAT; \
265	type HUBP0_3DLUT_FL_SCALE; \
266	type HUBP0_3DLUT_FL_BIAS; \
267	type HUBP_3DLUT_ENABLE;\
268	type HUBP_3DLUT_DONE;\
269	type HUBP_3DLUT_ADDRESSING_MODE;\
270	type HUBP_3DLUT_WIDTH;\
271	type HUBP_3DLUT_MPC_WIDTH;\
272	type HUBP_3DLUT_TMZ;\
273	type HUBP_3DLUT_CROSSBAR_SELECT_Y_G;\
274	type HUBP_3DLUT_CROSSBAR_SELECT_CB_B;\
275	type HUBP_3DLUT_CROSSBAR_SELECT_CR_R;\
276	type HUBP_3DLUT_ADDRESS_HIGH;\
277	type HUBP_3DLUT_ADDRESS_LOW;\
278	type REFCYC_PER_3DLUT_GROUP;\
279	type VIEWPORT_MCACHE_SPLIT_COORDINATE;\
280	type VIEWPORT_MCACHE_SPLIT_COORDINATE_C;\
281	type MCACHEID_REG_READ_1H_P0;\
282	type MCACHEID_REG_READ_2H_P0;\
283	type MCACHEID_REG_READ_1H_P1;\
284	type MCACHEID_REG_READ_2H_P1;\
285	type MCACHEID_MALL_PREF_1H_P0;\
286	type MCACHEID_MALL_PREF_2H_P0;\
287	type MCACHEID_MALL_PREF_1H_P1;\
288	type MCACHEID_MALL_PREF_2H_P1;\
289	type HUBP_FGCG_REP_DIS
290
291struct dcn_hubp2_registers {
292	DCN401_HUBP_REG_COMMON_VARIABLE_LIST;
293};
294
295struct dcn_hubp2_shift {
296	DCN401_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
297};
298
299struct dcn_hubp2_mask {
300	DCN401_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
301};
302
303struct dcn20_hubp {
304	struct hubp base;
305	struct dcn_hubp_state state;
306	const struct dcn_hubp2_registers *hubp_regs;
307	const struct dcn_hubp2_shift *hubp_shift;
308	const struct dcn_hubp2_mask *hubp_mask;
309};
310
311bool hubp2_construct(
312		struct dcn20_hubp *hubp2,
313		struct dc_context *ctx,
314		uint32_t inst,
315		const struct dcn_hubp2_registers *hubp_regs,
316		const struct dcn_hubp2_shift *hubp_shift,
317		const struct dcn_hubp2_mask *hubp_mask);
318
319void hubp2_setup_interdependent(
320		struct hubp *hubp,
321		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
322		struct _vcs_dpi_display_ttu_regs_st *ttu_attr);
323
324void hubp2_vready_at_or_After_vsync(struct hubp *hubp,
325		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
326
327void hubp2_cursor_set_attributes(
328		struct hubp *hubp,
329		const struct dc_cursor_attributes *attr);
330
331void hubp2_set_vm_system_aperture_settings(struct hubp *hubp,
332		struct vm_system_aperture_param *apt);
333
334enum cursor_lines_per_chunk hubp2_get_lines_per_chunk(
335		unsigned int cursor_width,
336		enum dc_cursor_color_format cursor_mode);
337
338void hubp2_dmdata_set_attributes(
339		struct hubp *hubp,
340		const struct dc_dmdata_attributes *attr);
341
342void hubp2_dmdata_load(
343		struct hubp *hubp,
344		uint32_t dmdata_sw_size,
345		const uint32_t *dmdata_sw_data);
346
347bool hubp2_dmdata_status_done(struct hubp *hubp);
348
349void hubp2_enable_triplebuffer(
350		struct hubp *hubp,
351		bool enable);
352
353bool hubp2_is_triplebuffer_enabled(
354		struct hubp *hubp);
355
356void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable);
357
358void hubp2_program_deadline(
359		struct hubp *hubp,
360		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
361		struct _vcs_dpi_display_ttu_regs_st *ttu_attr);
362
363bool hubp2_program_surface_flip_and_addr(
364	struct hubp *hubp,
365	const struct dc_plane_address *address,
366	bool flip_immediate);
367
368void hubp2_dcc_control(struct hubp *hubp, bool enable,
369		enum hubp_ind_block_size independent_64b_blks);
370
371void hubp2_program_size(
372	struct hubp *hubp,
373	enum surface_pixel_format format,
374	const struct plane_size *plane_size,
375	struct dc_plane_dcc_param *dcc);
376
377void hubp2_program_rotation(
378	struct hubp *hubp,
379	enum dc_rotation_angle rotation,
380	bool horizontal_mirror);
381
382void hubp2_program_pixel_format(
383	struct hubp *hubp,
384	enum surface_pixel_format format);
385
386void hubp2_program_surface_config(
387	struct hubp *hubp,
388	enum surface_pixel_format format,
389	struct dc_tiling_info *tiling_info,
390	struct plane_size *plane_size,
391	enum dc_rotation_angle rotation,
392	struct dc_plane_dcc_param *dcc,
393	bool horizontal_mirror,
394	unsigned int compat_level);
395
396bool hubp2_is_flip_pending(struct hubp *hubp);
397
398void hubp2_set_blank(struct hubp *hubp, bool blank);
399void hubp2_set_blank_regs(struct hubp *hubp, bool blank);
400
401void hubp2_cursor_set_position(
402		struct hubp *hubp,
403		const struct dc_cursor_position *pos,
404		const struct dc_cursor_mi_param *param);
405
406void hubp2_clk_cntl(struct hubp *hubp, bool enable);
407
408void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst);
409
410void hubp2_clear_underflow(struct hubp *hubp);
411
412void hubp2_read_state_common(struct hubp *hubp);
413
414void hubp2_read_state(struct hubp *hubp);
415
416void hubp2_clear_tiling(struct hubp *hubp);
417
418#endif /* __DC_MEM_INPUT_DCN20_H__ */
419
420