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dcn10_hubp.h
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linux-6.19.14/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
1/* Copyright 2012-15 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25#ifndef __DC_MEM_INPUT_DCN10_H__ 26#define __DC_MEM_INPUT_DCN10_H__ 27 28#include "hubp.h" 29 30#define TO_DCN10_HUBP(hubp)\ 31 container_of(hubp, struct dcn10_hubp, base) 32 33/* Register address initialization macro for all ASICs (including those with reduced functionality) */ 34#define HUBP_REG_LIST_DCN(id)\ 35 SRI(DCHUBP_CNTL, HUBP, id),\ 36 SRI(HUBPREQ_DEBUG_DB, HUBP, id),\ 37 SRI(HUBPREQ_DEBUG, HUBP, id),\ 38 SRI(DCSURF_ADDR_CONFIG, HUBP, id),\ 39 SRI(DCSURF_TILING_CONFIG, HUBP, id),\ 40 SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\ 41 SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\ 42 SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\ 43 SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\ 44 SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \ 45 SRI(DCSURF_PRI_VIEWPORT_START, HUBP, id), \ 46 SRI(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \ 47 SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \ 48 SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \ 49 SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \ 50 SRI(DCSURF_SEC_VIEWPORT_DIMENSION_C, HUBP, id), \ 51 SRI(DCSURF_SEC_VIEWPORT_START_C, HUBP, id), \ 52 SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\ 53 SRI(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),\ 54 SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\ 55 SRI(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id),\ 56 SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\ 57 SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id),\ 58 SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\ 59 SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id),\ 60 SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\ 61 SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),\ 62 SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\ 63 SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_C, HUBPREQ, id),\ 64 SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\ 65 SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\ 66 SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\ 67 SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\ 68 SRI(DCSURF_SURFACE_INUSE, HUBPREQ, id),\ 69 SRI(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id),\ 70 SRI(DCSURF_SURFACE_INUSE_C, HUBPREQ, id),\ 71 SRI(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id),\ 72 SRI(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id),\ 73 SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id),\ 74 SRI(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id),\ 75 SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id),\ 76 SRI(DCSURF_SURFACE_CONTROL, HUBPREQ, id),\ 77 SRI(DCSURF_SURFACE_FLIP_INTERRUPT, HUBPREQ, id),\ 78 SRI(HUBPRET_CONTROL, HUBPRET, id),\ 79 SRI(HUBPRET_READ_LINE_STATUS, HUBPRET, id),\ 80 SRI(DCN_EXPANSION_MODE, HUBPREQ, id),\ 81 SRI(DCHUBP_REQ_SIZE_CONFIG, HUBP, id),\ 82 SRI(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id),\ 83 SRI(BLANK_OFFSET_0, HUBPREQ, id),\ 84 SRI(BLANK_OFFSET_1, HUBPREQ, id),\ 85 SRI(DST_DIMENSIONS, HUBPREQ, id),\ 86 SRI(DST_AFTER_SCALER, HUBPREQ, id),\ 87 SRI(VBLANK_PARAMETERS_0, HUBPREQ, id),\ 88 SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\ 89 SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\ 90 SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\ 91 SRI(NOM_PARAMETERS_4, HUBPREQ, id),\ 92 SRI(NOM_PARAMETERS_5, HUBPREQ, id),\ 93 SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\ 94 SRI(PER_LINE_DELIVERY, HUBPREQ, id),\ 95 SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\ 96 SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\ 97 SRI(NOM_PARAMETERS_6, HUBPREQ, id),\ 98 SRI(NOM_PARAMETERS_7, HUBPREQ, id),\ 99 SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\ 100 SRI(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id),\ 101 SRI(DCN_SURF0_TTU_CNTL0, HUBPREQ, id),\ 102 SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\ 103 SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\ 104 SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\ 105 SRI(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),\ 106 SRI(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),\ 107 SRI(HUBP_CLK_CNTL, HUBP, id),\ 108 SRI(HUBPRET_READ_LINE_VALUE, HUBPRET, id),\ 109 SRI(HUBP_MEASURE_WIN_CTRL_DCFCLK, HUBP, id),\ 110 SRI(HUBP_MEASURE_WIN_CTRL_DPPCLK, HUBP, id) 111 112/* Register address initialization macro for ASICs with VM */ 113#define HUBP_REG_LIST_DCN_VM(id)\ 114 SRI(NOM_PARAMETERS_0, HUBPREQ, id),\ 115 SRI(NOM_PARAMETERS_1, HUBPREQ, id),\ 116 SRI(NOM_PARAMETERS_2, HUBPREQ, id),\ 117 SRI(NOM_PARAMETERS_3, HUBPREQ, id),\ 118 SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id) 119 120#define HUBP_REG_LIST_DCN10(id)\ 121 HUBP_REG_LIST_DCN(id),\ 122 HUBP_REG_LIST_DCN_VM(id),\ 123 SRI(PREFETCH_SETTINS, HUBPREQ, id),\ 124 SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\ 125 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\ 126 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, HUBPREQ, id),\ 127 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, HUBPREQ, id),\ 128 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, HUBPREQ, id),\ 129 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, HUBPREQ, id),\ 130 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, HUBPREQ, id),\ 131 SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, HUBPREQ, id),\ 132 SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, HUBPREQ, id),\ 133 SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, HUBPREQ, id),\ 134 SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, HUBPREQ, id),\ 135 SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, HUBPREQ, id),\ 136 SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\ 137 SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\ 138 SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\ 139 SRI(CURSOR_SETTINS, HUBPREQ, id), \ 140 SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \ 141 SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \ 142 SRI(CURSOR_SIZE, CURSOR, id), \ 143 SRI(CURSOR_CONTROL, CURSOR, id), \ 144 SRI(CURSOR_POSITION, CURSOR, id), \ 145 SRI(CURSOR_HOT_SPOT, CURSOR, id), \ 146 SRI(CURSOR_DST_OFFSET, CURSOR, id) 147 148#define HUBP_COMMON_REG_VARIABLE_LIST \ 149 uint32_t DCHUBP_CNTL; \ 150 uint32_t HUBPREQ_DEBUG_DB; \ 151 uint32_t HUBPREQ_DEBUG; \ 152 uint32_t DCSURF_ADDR_CONFIG; \ 153 uint32_t DCSURF_TILING_CONFIG; \ 154 uint32_t DCSURF_SURFACE_PITCH; \ 155 uint32_t DCSURF_SURFACE_PITCH_C; \ 156 uint32_t DCSURF_SURFACE_CONFIG; \ 157 uint32_t DCSURF_FLIP_CONTROL; \ 158 uint32_t DCSURF_PRI_VIEWPORT_DIMENSION; \ 159 uint32_t DCSURF_PRI_VIEWPORT_START; \ 160 uint32_t DCSURF_SEC_VIEWPORT_DIMENSION; \ 161 uint32_t DCSURF_SEC_VIEWPORT_START; \ 162 uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C; \ 163 uint32_t DCSURF_PRI_VIEWPORT_START_C; \ 164 uint32_t DCSURF_SEC_VIEWPORT_DIMENSION_C; \ 165 uint32_t DCSURF_SEC_VIEWPORT_START_C; \ 166 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; \ 167 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; \ 168 uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH; \ 169 uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS; \ 170 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH; \ 171 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS; \ 172 uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH; \ 173 uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS; \ 174 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; \ 175 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; \ 176 uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C; \ 177 uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_C; \ 178 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C; \ 179 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C; \ 180 uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C; \ 181 uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_C; \ 182 uint32_t DCSURF_SURFACE_INUSE; \ 183 uint32_t DCSURF_SURFACE_INUSE_HIGH; \ 184 uint32_t DCSURF_SURFACE_INUSE_C; \ 185 uint32_t DCSURF_SURFACE_INUSE_HIGH_C; \ 186 uint32_t DCSURF_SURFACE_EARLIEST_INUSE; \ 187 uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH; \ 188 uint32_t DCSURF_SURFACE_EARLIEST_INUSE_C; \ 189 uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C; \ 190 uint32_t DCSURF_SURFACE_CONTROL; \ 191 uint32_t DCSURF_SURFACE_FLIP_INTERRUPT; \ 192 uint32_t HUBPRET_CONTROL; \ 193 uint32_t HUBPRET_READ_LINE_STATUS; \ 194 uint32_t DCN_EXPANSION_MODE; \ 195 uint32_t DCHUBP_REQ_SIZE_CONFIG; \ 196 uint32_t DCHUBP_REQ_SIZE_CONFIG_C; \ 197 uint32_t BLANK_OFFSET_0; \ 198 uint32_t BLANK_OFFSET_1; \ 199 uint32_t DST_DIMENSIONS; \ 200 uint32_t DST_AFTER_SCALER; \ 201 uint32_t PREFETCH_SETTINS; \ 202 uint32_t PREFETCH_SETTINGS; \ 203 uint32_t VBLANK_PARAMETERS_0; \ 204 uint32_t REF_FREQ_TO_PIX_FREQ; \ 205 uint32_t VBLANK_PARAMETERS_1; \ 206 uint32_t VBLANK_PARAMETERS_3; \ 207 uint32_t NOM_PARAMETERS_0; \ 208 uint32_t NOM_PARAMETERS_1; \ 209 uint32_t NOM_PARAMETERS_4; \ 210 uint32_t NOM_PARAMETERS_5; \ 211 uint32_t PER_LINE_DELIVERY_PRE; \ 212 uint32_t PER_LINE_DELIVERY; \ 213 uint32_t PREFETCH_SETTINS_C; \ 214 uint32_t PREFETCH_SETTINGS_C; \ 215 uint32_t VBLANK_PARAMETERS_2; \ 216 uint32_t VBLANK_PARAMETERS_4; \ 217 uint32_t NOM_PARAMETERS_2; \ 218 uint32_t NOM_PARAMETERS_3; \ 219 uint32_t NOM_PARAMETERS_6; \ 220 uint32_t NOM_PARAMETERS_7; \ 221 uint32_t DCN_TTU_QOS_WM; \ 222 uint32_t DCN_GLOBAL_TTU_CNTL; \ 223 uint32_t DCN_SURF0_TTU_CNTL0; \ 224 uint32_t DCN_SURF0_TTU_CNTL1; \ 225 uint32_t DCN_SURF1_TTU_CNTL0; \ 226 uint32_t DCN_SURF1_TTU_CNTL1; \ 227 uint32_t DCN_CUR0_TTU_CNTL0; \ 228 uint32_t DCN_CUR0_TTU_CNTL1; \ 229 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB; \ 230 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB; \ 231 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB; \ 232 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB; \ 233 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB; \ 234 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB; \ 235 uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB; \ 236 uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB; \ 237 uint32_t DCN_VM_MX_L1_TLB_CNTL; \ 238 uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; \ 239 uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; \ 240 uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB; \ 241 uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB; \ 242 uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB; \ 243 uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB; \ 244 uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR; \ 245 uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR; \ 246 uint32_t CURSOR_SETTINS; \ 247 uint32_t CURSOR_SETTINGS; \ 248 uint32_t CURSOR_SURFACE_ADDRESS_HIGH; \ 249 uint32_t CURSOR_SURFACE_ADDRESS; \ 250 uint32_t CURSOR_SIZE; \ 251 uint32_t CURSOR_CONTROL; \ 252 uint32_t CURSOR_POSITION; \ 253 uint32_t CURSOR_HOT_SPOT; \ 254 uint32_t CURSOR_DST_OFFSET; \ 255 uint32_t HUBP_CLK_CNTL; \ 256 uint32_t HUBPRET_READ_LINE_VALUE; \ 257 uint32_t HUBP_MEASURE_WIN_CTRL_DCFCLK; \ 258 uint32_t HUBP_MEASURE_WIN_CTRL_DPPCLK; \ 259 uint32_t HUBPRET_INTERRUPT; \ 260 uint32_t HUBPRET_MEM_PWR_CTRL; \ 261 uint32_t HUBPRET_MEM_PWR_STATUS; \ 262 uint32_t HUBPRET_READ_LINE_CTRL0; \ 263 uint32_t HUBPRET_READ_LINE_CTRL1; \ 264 uint32_t HUBPRET_READ_LINE0; \ 265 uint32_t HUBPRET_READ_LINE1; \ 266 uint32_t HUBPREQ_MEM_PWR_CTRL; \ 267 uint32_t HUBPREQ_MEM_PWR_STATUS 268 269 270#define HUBP_SF(reg_name, field_name, post_fix)\ 271 .field_name = reg_name ## __ ## field_name ## post_fix 272 273/* Mask/shift struct generation macro for all ASICs (including those with reduced functionality) */ 274/*1.x, 2.x, and 3.x*/ 275#define HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh)\ 276 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\ 277 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\ 278 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\ 279 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, mask_sh),\ 280 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\ 281 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\ 282 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE, mask_sh),\ 283 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_IN_BLANK, mask_sh),\ 284 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\ 285 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\ 286 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\ 287 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_SE, mask_sh),\ 288 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_RB_PER_SE, mask_sh),\ 289 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\ 290 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\ 291 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\ 292 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\ 293 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\ 294 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\ 295 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\ 296 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\ 297 HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\ 298 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\ 299 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, mask_sh),\ 300 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, mask_sh),\ 301 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\ 302 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\ 303 HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\ 304 HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\ 305 HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\ 306 HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\ 307 HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\ 308 HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\ 309 HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\ 310 HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\ 311 HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\ 312 HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\ 313 HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\ 314 HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\ 315 HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_WIDTH_C, mask_sh),\ 316 HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_HEIGHT_C, mask_sh),\ 317 HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_X_START_C, mask_sh),\ 318 HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_Y_START_C, mask_sh),\ 319 HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\ 320 HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\ 321 HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\ 322 HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\ 323 HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\ 324 HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\ 325 HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\ 326 HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\ 327 HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\ 328 HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\ 329 HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, SECONDARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\ 330 HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C, SECONDARY_SURFACE_ADDRESS_C, mask_sh),\ 331 HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\ 332 HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\ 333 HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, SECONDARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\ 334 HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, SECONDARY_META_SURFACE_ADDRESS_C, mask_sh),\ 335 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\ 336 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\ 337 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\ 338 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\ 339 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\ 340 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\ 341 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\ 342 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\ 343 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\ 344 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ_C, mask_sh),\ 345 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ, mask_sh),\ 346 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ_C, mask_sh),\ 347 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\ 348 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\ 349 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ, mask_sh),\ 350 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ_C, mask_sh),\ 351 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ, mask_sh),\ 352 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ_C, mask_sh),\ 353 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\ 354 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\ 355 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK, mask_sh),\ 356 HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\ 357 HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\ 358 HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\ 359 HUBP_SF(HUBPRET0_HUBPRET_READ_LINE_STATUS, PIPE_READ_VBLANK, mask_sh),\ 360 HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\ 361 HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\ 362 HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\ 363 HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\ 364 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\ 365 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\ 366 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\ 367 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\ 368 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\ 369 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\ 370 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\ 371 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\ 372 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\ 373 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\ 374 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\ 375 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\ 376 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\ 377 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\ 378 HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\ 379 HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\ 380 HUBP_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\ 381 HUBP_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\ 382 HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\ 383 HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\ 384 HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\ 385 HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\ 386 HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\ 387 HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\ 388 HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\ 389 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\ 390 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\ 391 HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\ 392 HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\ 393 HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\ 394 HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\ 395 HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\ 396 HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\ 397 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\ 398 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\ 399 HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\ 400 HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\ 401 HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\ 402 HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\ 403 HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\ 404 HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\ 405 HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ 406 HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\ 407 HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh) 408/*2.x and 1.x only*/ 409#define HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)\ 410 HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\ 411 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\ 412 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\ 413 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh) 414 415/*2.x and 1.x only*/ 416#define HUBP_MASK_SH_LIST_DCN(mask_sh)\ 417 HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh) 418 419/* Mask/shift struct generation macro for ASICs with VM */ 420#define HUBP_MASK_SH_LIST_DCN_VM(mask_sh)\ 421 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\ 422 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\ 423 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\ 424 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\ 425 HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\ 426 HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\ 427 HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\ 428 HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\ 429 HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ 430 HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh) 431 432#define HUBP_MASK_SH_LIST_DCN10(mask_sh)\ 433 HUBP_MASK_SH_LIST_DCN(mask_sh),\ 434 HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ 435 HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\ 436 HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ 437 HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\ 438 HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\ 439 HUBP_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\ 440 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\ 441 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\ 442 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\ 443 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, mask_sh),\ 444 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, mask_sh),\ 445 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\ 446 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\ 447 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, mask_sh),\ 448 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\ 449 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\ 450 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\ 451 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\ 452 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\ 453 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ 454 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ 455 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\ 456 HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \ 457 HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ 458 HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ 459 HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ 460 HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ 461 HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ 462 HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ 463 HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ 464 HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ 465 HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ 466 HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ 467 HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ 468 HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ 469 HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ 470 HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ 471 HUBP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh) 472 473#define DCN_HUBP_REG_FIELD_BASE_LIST(type) \ 474 type HUBP_BLANK_EN;\ 475 type HUBP_DISABLE;\ 476 type HUBP_TTU_DISABLE;\ 477 type HUBP_NO_OUTSTANDING_REQ;\ 478 type HUBP_VTG_SEL;\ 479 type HUBP_UNDERFLOW_STATUS;\ 480 type HUBP_UNDERFLOW_CLEAR;\ 481 type HUBP_IN_BLANK;\ 482 type NUM_PIPES;\ 483 type NUM_BANKS;\ 484 type PIPE_INTERLEAVE;\ 485 type NUM_SE;\ 486 type NUM_RB_PER_SE;\ 487 type MAX_COMPRESSED_FRAGS;\ 488 type SW_MODE;\ 489 type META_LINEAR;\ 490 type RB_ALIGNED;\ 491 type PIPE_ALIGNED;\ 492 type PITCH;\ 493 type META_PITCH;\ 494 type PITCH_C;\ 495 type META_PITCH_C;\ 496 type ROTATION_ANGLE;\ 497 type H_MIRROR_EN;\ 498 type SURFACE_PIXEL_FORMAT;\ 499 type SURFACE_FLIP_TYPE;\ 500 type SURFACE_FLIP_MODE_FOR_STEREOSYNC;\ 501 type SURFACE_FLIP_IN_STEREOSYNC;\ 502 type SURFACE_UPDATE_LOCK;\ 503 type SURFACE_FLIP_PENDING;\ 504 type PRI_VIEWPORT_WIDTH; \ 505 type PRI_VIEWPORT_HEIGHT; \ 506 type PRI_VIEWPORT_X_START; \ 507 type PRI_VIEWPORT_Y_START; \ 508 type SEC_VIEWPORT_WIDTH; \ 509 type SEC_VIEWPORT_HEIGHT; \ 510 type SEC_VIEWPORT_X_START; \ 511 type SEC_VIEWPORT_Y_START; \ 512 type PRI_VIEWPORT_WIDTH_C; \ 513 type PRI_VIEWPORT_HEIGHT_C; \ 514 type PRI_VIEWPORT_X_START_C; \ 515 type PRI_VIEWPORT_Y_START_C; \ 516 type SEC_VIEWPORT_WIDTH_C; \ 517 type SEC_VIEWPORT_HEIGHT_C; \ 518 type SEC_VIEWPORT_X_START_C; \ 519 type SEC_VIEWPORT_Y_START_C; \ 520 type PRIMARY_SURFACE_ADDRESS_HIGH;\ 521 type PRIMARY_SURFACE_ADDRESS;\ 522 type SECONDARY_SURFACE_ADDRESS_HIGH;\ 523 type SECONDARY_SURFACE_ADDRESS;\ 524 type PRIMARY_META_SURFACE_ADDRESS_HIGH;\ 525 type PRIMARY_META_SURFACE_ADDRESS;\ 526 type SECONDARY_META_SURFACE_ADDRESS_HIGH;\ 527 type SECONDARY_META_SURFACE_ADDRESS;\ 528 type PRIMARY_SURFACE_ADDRESS_HIGH_C;\ 529 type PRIMARY_SURFACE_ADDRESS_C;\ 530 type SECONDARY_SURFACE_ADDRESS_HIGH_C;\ 531 type SECONDARY_SURFACE_ADDRESS_C;\ 532 type PRIMARY_META_SURFACE_ADDRESS_HIGH_C;\ 533 type PRIMARY_META_SURFACE_ADDRESS_C;\ 534 type SECONDARY_META_SURFACE_ADDRESS_HIGH_C;\ 535 type SECONDARY_META_SURFACE_ADDRESS_C;\ 536 type SURFACE_INUSE_ADDRESS;\ 537 type SURFACE_INUSE_ADDRESS_HIGH;\ 538 type SURFACE_INUSE_ADDRESS_C;\ 539 type SURFACE_INUSE_ADDRESS_HIGH_C;\ 540 type SURFACE_EARLIEST_INUSE_ADDRESS;\ 541 type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH;\ 542 type SURFACE_EARLIEST_INUSE_ADDRESS_C;\ 543 type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C;\ 544 type PRIMARY_SURFACE_TMZ;\ 545 type PRIMARY_SURFACE_TMZ_C;\ 546 type SECONDARY_SURFACE_TMZ;\ 547 type SECONDARY_SURFACE_TMZ_C;\ 548 type PRIMARY_META_SURFACE_TMZ;\ 549 type PRIMARY_META_SURFACE_TMZ_C;\ 550 type SECONDARY_META_SURFACE_TMZ;\ 551 type SECONDARY_META_SURFACE_TMZ_C;\ 552 type PRIMARY_SURFACE_DCC_EN;\ 553 type PRIMARY_SURFACE_DCC_IND_64B_BLK;\ 554 type SECONDARY_SURFACE_DCC_EN;\ 555 type SECONDARY_SURFACE_DCC_IND_64B_BLK;\ 556 type SURFACE_FLIP_INT_MASK;\ 557 type DET_BUF_PLANE1_BASE_ADDRESS;\ 558 type CROSSBAR_SRC_CB_B;\ 559 type CROSSBAR_SRC_CR_R;\ 560 type PIPE_READ_VBLANK;\ 561 type DRQ_EXPANSION_MODE;\ 562 type PRQ_EXPANSION_MODE;\ 563 type MRQ_EXPANSION_MODE;\ 564 type CRQ_EXPANSION_MODE;\ 565 type CHUNK_SIZE;\ 566 type MIN_CHUNK_SIZE;\ 567 type META_CHUNK_SIZE;\ 568 type MIN_META_CHUNK_SIZE;\ 569 type DPTE_GROUP_SIZE;\ 570 type MPTE_GROUP_SIZE;\ 571 type SWATH_HEIGHT;\ 572 type PTE_ROW_HEIGHT_LINEAR;\ 573 type CHUNK_SIZE_C;\ 574 type MIN_CHUNK_SIZE_C;\ 575 type META_CHUNK_SIZE_C;\ 576 type MIN_META_CHUNK_SIZE_C;\ 577 type DPTE_GROUP_SIZE_C;\ 578 type MPTE_GROUP_SIZE_C;\ 579 type SWATH_HEIGHT_C;\ 580 type PTE_ROW_HEIGHT_LINEAR_C;\ 581 type REFCYC_H_BLANK_END;\ 582 type DLG_V_BLANK_END;\ 583 type MIN_DST_Y_NEXT_START;\ 584 type REFCYC_PER_HTOTAL;\ 585 type REFCYC_X_AFTER_SCALER;\ 586 type DST_Y_AFTER_SCALER;\ 587 type DST_Y_PREFETCH;\ 588 type VRATIO_PREFETCH;\ 589 type DST_Y_PER_VM_VBLANK;\ 590 type DST_Y_PER_ROW_VBLANK;\ 591 type REF_FREQ_TO_PIX_FREQ;\ 592 type REFCYC_PER_PTE_GROUP_VBLANK_L;\ 593 type REFCYC_PER_META_CHUNK_VBLANK_L;\ 594 type DST_Y_PER_PTE_ROW_NOM_L;\ 595 type REFCYC_PER_PTE_GROUP_NOM_L;\ 596 type DST_Y_PER_META_ROW_NOM_L;\ 597 type REFCYC_PER_META_CHUNK_NOM_L;\ 598 type REFCYC_PER_LINE_DELIVERY_PRE_L;\ 599 type REFCYC_PER_LINE_DELIVERY_PRE_C;\ 600 type REFCYC_PER_LINE_DELIVERY_L;\ 601 type REFCYC_PER_LINE_DELIVERY_C;\ 602 type VRATIO_PREFETCH_C;\ 603 type REFCYC_PER_PTE_GROUP_VBLANK_C;\ 604 type REFCYC_PER_META_CHUNK_VBLANK_C;\ 605 type DST_Y_PER_PTE_ROW_NOM_C;\ 606 type REFCYC_PER_PTE_GROUP_NOM_C;\ 607 type DST_Y_PER_META_ROW_NOM_C;\ 608 type REFCYC_PER_META_CHUNK_NOM_C;\ 609 type QoS_LEVEL_LOW_WM;\ 610 type QoS_LEVEL_HIGH_WM;\ 611 type MIN_TTU_VBLANK;\ 612 type QoS_LEVEL_FLIP;\ 613 type REFCYC_PER_REQ_DELIVERY;\ 614 type QoS_LEVEL_FIXED;\ 615 type QoS_RAMP_DISABLE;\ 616 type REFCYC_PER_REQ_DELIVERY_PRE;\ 617 type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB;\ 618 type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB;\ 619 type VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB;\ 620 type VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB;\ 621 type VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB;\ 622 type VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB;\ 623 type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\ 624 type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM;\ 625 type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB;\ 626 type ENABLE_L1_TLB;\ 627 type SYSTEM_ACCESS_MODE;\ 628 type HUBP_CLOCK_ENABLE;\ 629 type MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\ 630 type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\ 631 type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\ 632 type MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB;\ 633 type MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB;\ 634 type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB;\ 635 type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;\ 636 type MC_VM_SYSTEM_APERTURE_LOW_ADDR;\ 637 type MC_VM_SYSTEM_APERTURE_HIGH_ADDR;\ 638 type DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\ 639 type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\ 640 type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\ 641 type PIPE_READ_LINE;\ 642 type HUBP_SEG_ALLOC_ERR_STATUS;\ 643 /* todo: get these from GVM instead of reading registers ourselves */\ 644 type PAGE_DIRECTORY_ENTRY_HI32;\ 645 type PAGE_DIRECTORY_ENTRY_LO32;\ 646 type LOGICAL_PAGE_NUMBER_HI4;\ 647 type LOGICAL_PAGE_NUMBER_LO32;\ 648 type PHYSICAL_PAGE_ADDR_HI4;\ 649 type PHYSICAL_PAGE_ADDR_LO32;\ 650 type PHYSICAL_PAGE_NUMBER_MSB;\ 651 type PHYSICAL_PAGE_NUMBER_LSB;\ 652 type LOGICAL_ADDR;\ 653 type CURSOR0_DST_Y_OFFSET; \ 654 type CURSOR0_CHUNK_HDL_ADJUST; \ 655 type CURSOR_SURFACE_ADDRESS_HIGH; \ 656 type CURSOR_SURFACE_ADDRESS; \ 657 type CURSOR_WIDTH; \ 658 type CURSOR_HEIGHT; \ 659 type CURSOR_MODE; \ 660 type CURSOR_2X_MAGNIFY; \ 661 type CURSOR_PITCH; \ 662 type CURSOR_LINES_PER_CHUNK; \ 663 type CURSOR_ENABLE; \ 664 type CURSOR_X_POSITION; \ 665 type CURSOR_Y_POSITION; \ 666 type CURSOR_HOT_SPOT_X; \ 667 type CURSOR_HOT_SPOT_Y; \ 668 type CURSOR_DST_X_OFFSET; \ 669 type OUTPUT_FP 670 671#define DCN_HUBP_REG_FIELD_LIST(type) \ 672 DCN_HUBP_REG_FIELD_BASE_LIST(type);\ 673 type ALPHA_PLANE_EN 674 675struct dcn_mi_registers { 676 HUBP_COMMON_REG_VARIABLE_LIST; 677}; 678 679struct dcn_mi_shift { 680 DCN_HUBP_REG_FIELD_LIST(uint8_t); 681}; 682 683struct dcn_mi_mask { 684 DCN_HUBP_REG_FIELD_LIST(uint32_t); 685}; 686 687struct dcn_fl_regs_st { 688 uint32_t lut_enable; 689 uint32_t lut_done; 690 uint32_t lut_addr_mode; 691 uint32_t lut_width; 692 uint32_t lut_mpc_width; 693 uint32_t lut_tmz; 694 uint32_t lut_crossbar_sel_r; 695 uint32_t lut_crossbar_sel_g; 696 uint32_t lut_crossbar_sel_b; 697 uint32_t lut_addr_hi; 698 uint32_t lut_addr_lo; 699 uint32_t refcyc_3dlut_group; 700 uint32_t lut_fl_bias; 701 uint32_t lut_fl_scale; 702 uint32_t lut_fl_mode; 703 uint32_t lut_fl_format; 704}; 705struct dcn_hubp_reg_state { 706 uint32_t hubp_cntl; 707 uint32_t mall_config; 708 uint32_t mall_sub_vp; 709 uint32_t hubp_req_size_config; 710 uint32_t hubp_req_size_config_c; 711 uint32_t vmpg_config; 712 uint32_t addr_config; 713 uint32_t pri_viewport_dimension; 714 uint32_t pri_viewport_dimension_c; 715 uint32_t pri_viewport_start; 716 uint32_t pri_viewport_start_c; 717 uint32_t sec_viewport_dimension; 718 uint32_t sec_viewport_dimension_c; 719 uint32_t sec_viewport_start; 720 uint32_t sec_viewport_start_c; 721 uint32_t surface_config; 722 uint32_t tiling_config; 723 uint32_t clk_cntl; 724 uint32_t mall_status; 725 uint32_t measure_win_ctrl_dcfclk; 726 uint32_t measure_win_ctrl_dppclk; 727 728 uint32_t blank_offset_0; 729 uint32_t blank_offset_1; 730 uint32_t cursor_settings; 731 uint32_t dcn_cur0_ttu_cntl0; 732 uint32_t dcn_cur0_ttu_cntl1; 733 uint32_t dcn_cur1_ttu_cntl0; 734 uint32_t dcn_cur1_ttu_cntl1; 735 uint32_t dcn_dmdat_vm_cntl; 736 uint32_t dcn_expansion_mode; 737 uint32_t dcn_global_ttu_cntl; 738 uint32_t dcn_surf0_ttu_cntl0; 739 uint32_t dcn_surf0_ttu_cntl1; 740 uint32_t dcn_surf1_ttu_cntl0; 741 uint32_t dcn_surf1_ttu_cntl1; 742 uint32_t dcn_ttu_qos_wm; 743 uint32_t dcn_vm_mx_l1_tlb_cntl; 744 uint32_t dcn_vm_system_aperture_high_addr; 745 uint32_t dcn_vm_system_aperture_low_addr; 746 uint32_t dcsurf_flip_control; 747 uint32_t dcsurf_flip_control2; 748 uint32_t dcsurf_primary_meta_surface_address; 749 uint32_t dcsurf_primary_meta_surface_address_c; 750 uint32_t dcsurf_primary_meta_surface_address_high; 751 uint32_t dcsurf_primary_meta_surface_address_high_c; 752 uint32_t dcsurf_primary_surface_address; 753 uint32_t dcsurf_primary_surface_address_c; 754 uint32_t dcsurf_primary_surface_address_high; 755 uint32_t dcsurf_primary_surface_address_high_c; 756 uint32_t dcsurf_secondary_meta_surface_address; 757 uint32_t dcsurf_secondary_meta_surface_address_c; 758 uint32_t dcsurf_secondary_meta_surface_address_high; 759 uint32_t dcsurf_secondary_meta_surface_address_high_c; 760 uint32_t dcsurf_secondary_surface_address; 761 uint32_t dcsurf_secondary_surface_address_c; 762 uint32_t dcsurf_secondary_surface_address_high; 763 uint32_t dcsurf_secondary_surface_address_high_c; 764 uint32_t dcsurf_surface_control; 765 uint32_t dcsurf_surface_earliest_inuse; 766 uint32_t dcsurf_surface_earliest_inuse_c; 767 uint32_t dcsurf_surface_earliest_inuse_high; 768 uint32_t dcsurf_surface_earliest_inuse_high_c; 769 uint32_t dcsurf_surface_flip_interrupt; 770 uint32_t dcsurf_surface_inuse; 771 uint32_t dcsurf_surface_inuse_c; 772 uint32_t dcsurf_surface_inuse_high; 773 uint32_t dcsurf_surface_inuse_high_c; 774 uint32_t dcsurf_surface_pitch; 775 uint32_t dcsurf_surface_pitch_c; 776 uint32_t dst_after_scaler; 777 uint32_t dst_dimensions; 778 uint32_t dst_y_delta_drq_limit; 779 uint32_t flip_parameters_0; 780 uint32_t flip_parameters_1; 781 uint32_t flip_parameters_2; 782 uint32_t flip_parameters_3; 783 uint32_t flip_parameters_4; 784 uint32_t flip_parameters_5; 785 uint32_t flip_parameters_6; 786 uint32_t hubpreq_mem_pwr_ctrl; 787 uint32_t hubpreq_mem_pwr_status; 788 uint32_t nom_parameters_0; 789 uint32_t nom_parameters_1; 790 uint32_t nom_parameters_2; 791 uint32_t nom_parameters_3; 792 uint32_t nom_parameters_4; 793 uint32_t nom_parameters_5; 794 uint32_t nom_parameters_6; 795 uint32_t nom_parameters_7; 796 uint32_t per_line_delivery; 797 uint32_t per_line_delivery_pre; 798 uint32_t prefetch_settings; 799 uint32_t prefetch_settings_c; 800 uint32_t ref_freq_to_pix_freq; 801 uint32_t uclk_pstate_force; 802 uint32_t vblank_parameters_0; 803 uint32_t vblank_parameters_1; 804 uint32_t vblank_parameters_2; 805 uint32_t vblank_parameters_3; 806 uint32_t vblank_parameters_4; 807 uint32_t vblank_parameters_5; 808 uint32_t vblank_parameters_6; 809 uint32_t vmid_settings_0; 810 811 uint32_t hubpret_control; 812 uint32_t hubpret_interrupt; 813 uint32_t hubpret_mem_pwr_ctrl; 814 uint32_t hubpret_mem_pwr_status; 815 uint32_t hubpret_read_line_ctrl0; 816 uint32_t hubpret_read_line_ctrl1; 817 uint32_t hubpret_read_line_status; 818 uint32_t hubpret_read_line_value; 819 uint32_t hubpret_read_line0; 820 uint32_t hubpret_read_line1; 821}; 822 823struct dcn_hubp_state { 824 struct _vcs_dpi_display_dlg_regs_st dlg_attr; 825 struct _vcs_dpi_display_ttu_regs_st ttu_attr; 826 struct _vcs_dpi_display_rq_regs_st rq_regs; 827 struct dcn_fl_regs_st fl_regs; 828 uint32_t pixel_format; 829 uint32_t inuse_addr_hi; 830 uint32_t inuse_addr_lo; 831 uint32_t viewport_width; 832 uint32_t viewport_height; 833 uint32_t rotation_angle; 834 uint32_t h_mirror_en; 835 uint32_t sw_mode; 836 uint32_t dcc_en; 837 uint32_t blank_en; 838 uint32_t clock_en; 839 uint32_t underflow_status; 840 uint32_t ttu_disable; 841 uint32_t min_ttu_vblank; 842 uint32_t qos_level_low_wm; 843 uint32_t qos_level_high_wm; 844 uint32_t primary_surface_addr_lo; 845 uint32_t primary_surface_addr_hi; 846 uint32_t primary_meta_addr_lo; 847 uint32_t primary_meta_addr_hi; 848 uint32_t uclk_pstate_force; 849 uint32_t hubp_cntl; 850 uint32_t flip_control; 851}; 852struct dcn10_hubp { 853 struct hubp base; 854 struct dcn_hubp_state state; 855 const struct dcn_mi_registers *hubp_regs; 856 const struct dcn_mi_shift *hubp_shift; 857 const struct dcn_mi_mask *hubp_mask; 858}; 859 860void hubp1_program_surface_config( 861 struct hubp *hubp, 862 enum surface_pixel_format format, 863 struct dc_tiling_info *tiling_info, 864 struct plane_size *plane_size, 865 enum dc_rotation_angle rotation, 866 struct dc_plane_dcc_param *dcc, 867 bool horizontal_mirror, 868 unsigned int compat_level); 869 870void hubp1_program_deadline( 871 struct hubp *hubp, 872 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 873 struct _vcs_dpi_display_ttu_regs_st *ttu_attr); 874 875void hubp1_program_requestor( 876 struct hubp *hubp, 877 struct _vcs_dpi_display_rq_regs_st *rq_regs); 878 879void hubp1_program_pixel_format( 880 struct hubp *hubp, 881 enum surface_pixel_format format); 882 883void hubp1_program_size( 884 struct hubp *hubp, 885 enum surface_pixel_format format, 886 const struct plane_size *plane_size, 887 struct dc_plane_dcc_param *dcc); 888 889void hubp1_program_rotation( 890 struct hubp *hubp, 891 enum dc_rotation_angle rotation, 892 bool horizontal_mirror); 893 894void hubp1_program_tiling( 895 struct hubp *hubp, 896 const struct dc_tiling_info *info, 897 const enum surface_pixel_format pixel_format); 898 899void hubp1_dcc_control(struct hubp *hubp, 900 bool enable, 901 enum hubp_ind_block_size independent_64b_blks); 902 903void hubp_reset(struct hubp *hubp); 904 905bool hubp1_program_surface_flip_and_addr( 906 struct hubp *hubp, 907 const struct dc_plane_address *address, 908 bool flip_immediate); 909 910bool hubp1_is_flip_pending(struct hubp *hubp); 911 912void hubp1_cursor_set_attributes( 913 struct hubp *hubp, 914 const struct dc_cursor_attributes *attr); 915 916void hubp1_cursor_set_position( 917 struct hubp *hubp, 918 const struct dc_cursor_position *pos, 919 const struct dc_cursor_mi_param *param); 920 921void hubp1_set_blank(struct hubp *hubp, bool blank); 922 923void min_set_viewport(struct hubp *hubp, 924 const struct rect *viewport, 925 const struct rect *viewport_c); 926 927void hubp1_clk_cntl(struct hubp *hubp, bool enable); 928void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst); 929 930void dcn10_hubp_construct( 931 struct dcn10_hubp *hubp1, 932 struct dc_context *ctx, 933 uint32_t inst, 934 const struct dcn_mi_registers *hubp_regs, 935 const struct dcn_mi_shift *hubp_shift, 936 const struct dcn_mi_mask *hubp_mask); 937 938void hubp1_read_state(struct hubp *hubp); 939void hubp1_clear_underflow(struct hubp *hubp); 940 941enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch); 942 943void hubp1_vready_workaround(struct hubp *hubp, 944 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); 945 946void hubp1_init(struct hubp *hubp); 947void hubp1_read_state_common(struct hubp *hubp); 948bool hubp1_in_blank(struct hubp *hubp); 949void hubp1_soft_reset(struct hubp *hubp, bool reset); 950 951void hubp1_set_flip_int(struct hubp *hubp); 952 953void hubp1_clear_tiling(struct hubp *hubp); 954 955#endif
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