dcn30_hubbub.c

  1/*
  2 * Copyright 2020 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26
 27#include "dm_services.h"
 28#include "reg_helper.h"
 29#include "dcn30_hubbub.h"
 30
 31
 32#define CTX \
 33	hubbub1->base.ctx
 34#define DC_LOGGER \
 35	hubbub1->base.ctx->logger
 36#define REG(reg)\
 37	hubbub1->regs->reg
 38
 39#undef FN
 40#define FN(reg_name, field_name) \
 41	hubbub1->shifts->field_name, hubbub1->masks->field_name
 42
 43#ifdef NUM_VMID
 44#undef NUM_VMID
 45#endif
 46#define NUM_VMID 16
 47
 48
 49static uint32_t convert_and_clamp(
 50	uint32_t wm_ns,
 51	uint32_t refclk_mhz,
 52	uint32_t clamp_value)
 53{
 54	uint32_t ret_val = 0;
 55	ret_val = wm_ns * refclk_mhz;
 56	ret_val /= 1000;
 57
 58	if (ret_val > clamp_value)
 59		ret_val = clamp_value;
 60
 61	return ret_val;
 62}
 63
 64int hubbub3_init_dchub_sys_ctx(struct hubbub *hubbub,
 65		struct dcn_hubbub_phys_addr_config *pa_config)
 66{
 67	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
 68	struct dcn_vmid_page_table_config phys_config;
 69
 70	REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
 71			FB_BASE, pa_config->system_aperture.fb_base >> 24);
 72	REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
 73			FB_TOP, pa_config->system_aperture.fb_top >> 24);
 74	REG_SET(DCN_VM_FB_OFFSET, 0,
 75			FB_OFFSET, pa_config->system_aperture.fb_offset >> 24);
 76	REG_SET(DCN_VM_AGP_BOT, 0,
 77			AGP_BOT, pa_config->system_aperture.agp_bot >> 24);
 78	REG_SET(DCN_VM_AGP_TOP, 0,
 79			AGP_TOP, pa_config->system_aperture.agp_top >> 24);
 80	REG_SET(DCN_VM_AGP_BASE, 0,
 81			AGP_BASE, pa_config->system_aperture.agp_base >> 24);
 82
 83	if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) {
 84		phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12;
 85		phys_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr >> 12;
 86		phys_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
 87		phys_config.depth = 0;
 88		phys_config.block_size = 0;
 89		// Init VMID 0 based on PA config
 90		dcn20_vmid_setup(&hubbub1->vmid[0], &phys_config);
 91	}
 92
 93	return NUM_VMID;
 94}
 95
 96bool hubbub3_program_watermarks(
 97		struct hubbub *hubbub,
 98		union dcn_watermark_set *watermarks,
 99		unsigned int refclk_mhz,
100		bool safe_to_lower)
101{
102	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
103	bool wm_pending = false;
104
105	if (hubbub21_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
106		wm_pending = true;
107
108	if (hubbub21_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
109		wm_pending = true;
110
111	if (hubbub21_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
112		wm_pending = true;
113
114	/*
115	 * The DCHub arbiter has a mechanism to dynamically rate limit the DCHub request stream to the fabric.
116	 * If the memory controller is fully utilized and the DCHub requestors are
117	 * well ahead of their amortized schedule, then it is safe to prevent the next winner
118	 * from being committed and sent to the fabric.
119	 * The utilization of the memory controller is approximated by ensuring that
120	 * the number of outstanding requests is greater than a threshold specified
121	 * by the ARB_MIN_REQ_OUTSTANDING. To determine that the DCHub requestors are well ahead of the amortized schedule,
122	 * the slack of the next winner is compared with the ARB_SAT_LEVEL in DLG RefClk cycles.
123	 *
124	 * TODO: Revisit request limit after figure out right number. request limit for Renoir isn't decided yet, set maximum value (0x1FF)
125	 * to turn off it for now.
126	 */
127	REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,
128			DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
129	REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
130			DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);
131
132	if (safe_to_lower || hubbub->ctx->dc->debug.disable_stutter)
133		hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
134
135	return wm_pending;
136}
137
138bool hubbub3_dcc_support_swizzle(
139		enum swizzle_mode_values swizzle,
140		unsigned int bytes_per_element,
141		enum segment_order *segment_order_horz,
142		enum segment_order *segment_order_vert)
143{
144	bool standard_swizzle = false;
145	bool display_swizzle = false;
146	bool render_swizzle = false;
147
148	switch (swizzle) {
149	case DC_SW_4KB_S:
150	case DC_SW_64KB_S:
151	case DC_SW_VAR_S:
152	case DC_SW_4KB_S_X:
153	case DC_SW_64KB_S_X:
154	case DC_SW_VAR_S_X:
155		standard_swizzle = true;
156		break;
157	case DC_SW_4KB_R:
158	case DC_SW_64KB_R:
159	case DC_SW_VAR_R:
160	case DC_SW_4KB_R_X:
161	case DC_SW_64KB_R_X:
162	case DC_SW_VAR_R_X:
163		render_swizzle = true;
164		break;
165	case DC_SW_4KB_D:
166	case DC_SW_64KB_D:
167	case DC_SW_VAR_D:
168	case DC_SW_4KB_D_X:
169	case DC_SW_64KB_D_X:
170	case DC_SW_VAR_D_X:
171		display_swizzle = true;
172		break;
173	default:
174		break;
175	}
176
177	if (standard_swizzle) {
178		if (bytes_per_element == 1) {
179			*segment_order_horz = segment_order__contiguous;
180			*segment_order_vert = segment_order__na;
181			return true;
182		}
183		if (bytes_per_element == 2) {
184			*segment_order_horz = segment_order__non_contiguous;
185			*segment_order_vert = segment_order__contiguous;
186			return true;
187		}
188		if (bytes_per_element == 4) {
189			*segment_order_horz = segment_order__non_contiguous;
190			*segment_order_vert = segment_order__contiguous;
191			return true;
192		}
193		if (bytes_per_element == 8) {
194			*segment_order_horz = segment_order__na;
195			*segment_order_vert = segment_order__contiguous;
196			return true;
197		}
198	}
199	if (render_swizzle) {
200		if (bytes_per_element == 1) {
201			*segment_order_horz = segment_order__contiguous;
202			*segment_order_vert = segment_order__na;
203			return true;
204		}
205		if (bytes_per_element == 2) {
206			*segment_order_horz = segment_order__non_contiguous;
207			*segment_order_vert = segment_order__contiguous;
208			return true;
209		}
210		if (bytes_per_element == 4) {
211			*segment_order_horz = segment_order__contiguous;
212			*segment_order_vert = segment_order__non_contiguous;
213			return true;
214		}
215		if (bytes_per_element == 8) {
216			*segment_order_horz = segment_order__contiguous;
217			*segment_order_vert = segment_order__non_contiguous;
218			return true;
219		}
220	}
221	if (display_swizzle && bytes_per_element == 8) {
222		*segment_order_horz = segment_order__contiguous;
223		*segment_order_vert = segment_order__non_contiguous;
224		return true;
225	}
226
227	return false;
228}
229
230static void hubbub3_get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height,
231		unsigned int bytes_per_element)
232{
233	/* copied from DML.  might want to refactor DML to leverage from DML */
234	/* DML : get_blk256_size */
235	if (bytes_per_element == 1) {
236		*blk256_width = 16;
237		*blk256_height = 16;
238	} else if (bytes_per_element == 2) {
239		*blk256_width = 16;
240		*blk256_height = 8;
241	} else if (bytes_per_element == 4) {
242		*blk256_width = 8;
243		*blk256_height = 8;
244	} else if (bytes_per_element == 8) {
245		*blk256_width = 8;
246		*blk256_height = 4;
247	}
248}
249
250static void hubbub3_det_request_size(
251		unsigned int detile_buf_size,
252		unsigned int height,
253		unsigned int width,
254		unsigned int bpe,
255		bool *req128_horz_wc,
256		bool *req128_vert_wc)
257{
258	unsigned int blk256_height = 0;
259	unsigned int blk256_width = 0;
260	unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc;
261
262	hubbub3_get_blk256_size(&blk256_width, &blk256_height, bpe);
263
264	swath_bytes_horz_wc = width * blk256_height * bpe;
265	swath_bytes_vert_wc = height * blk256_width * bpe;
266
267	*req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ?
268			false : /* full 256B request */
269			true; /* half 128b request */
270
271	*req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ?
272			false : /* full 256B request */
273			true; /* half 128b request */
274}
275
276bool hubbub3_get_dcc_compression_cap(struct hubbub *hubbub,
277		const struct dc_dcc_surface_param *input,
278		struct dc_surface_dcc_cap *output)
279{
280	struct dc *dc = hubbub->ctx->dc;
281	/* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */
282	enum dcc_control dcc_control;
283	unsigned int bpe;
284	enum segment_order segment_order_horz, segment_order_vert;
285	bool req128_horz_wc, req128_vert_wc;
286
287	memset(output, 0, sizeof(*output));
288
289	if (dc->debug.disable_dcc == DCC_DISABLE)
290		return false;
291
292	if (!hubbub->funcs->dcc_support_pixel_format(input->format,
293			&bpe))
294		return false;
295
296	if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe,
297			&segment_order_horz, &segment_order_vert))
298		return false;
299
300	hubbub3_det_request_size(TO_DCN20_HUBBUB(hubbub)->detile_buf_size,
301			input->surface_size.height,  input->surface_size.width,
302			bpe, &req128_horz_wc, &req128_vert_wc);
303
304	if (!req128_horz_wc && !req128_vert_wc) {
305		dcc_control = dcc_control__256_256_xxx;
306	} else if (input->scan == SCAN_DIRECTION_HORIZONTAL) {
307		if (!req128_horz_wc)
308			dcc_control = dcc_control__256_256_xxx;
309		else if (segment_order_horz == segment_order__contiguous)
310			dcc_control = dcc_control__128_128_xxx;
311		else
312			dcc_control = dcc_control__256_64_64;
313	} else if (input->scan == SCAN_DIRECTION_VERTICAL) {
314		if (!req128_vert_wc)
315			dcc_control = dcc_control__256_256_xxx;
316		else if (segment_order_vert == segment_order__contiguous)
317			dcc_control = dcc_control__128_128_xxx;
318		else
319			dcc_control = dcc_control__256_64_64;
320	} else {
321		if ((req128_horz_wc &&
322			segment_order_horz == segment_order__non_contiguous) ||
323			(req128_vert_wc &&
324			segment_order_vert == segment_order__non_contiguous))
325			/* access_dir not known, must use most constraining */
326			dcc_control = dcc_control__256_64_64;
327		else
328			/* reg128 is true for either horz and vert
329			 * but segment_order is contiguous
330			 */
331			dcc_control = dcc_control__128_128_xxx;
332	}
333
334	/* Exception for 64KB_R_X */
335	if ((bpe == 2) && (input->swizzle_mode == DC_SW_64KB_R_X))
336		dcc_control = dcc_control__128_128_xxx;
337
338	if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&
339		dcc_control != dcc_control__256_256_xxx)
340		return false;
341
342	switch (dcc_control) {
343	case dcc_control__256_256:
344	case dcc_control__256_256_xxx:
345		output->grph.rgb.max_uncompressed_blk_size = 256;
346		output->grph.rgb.max_compressed_blk_size = 256;
347		output->grph.rgb.independent_64b_blks = false;
348		output->grph.rgb.dcc_controls.dcc_256_256_unconstrained = 1;
349		output->grph.rgb.dcc_controls.dcc_256_128_128 = 1;
350		break;
351	case dcc_control__256_128:
352	case dcc_control__128_128_xxx:
353		output->grph.rgb.max_uncompressed_blk_size = 128;
354		output->grph.rgb.max_compressed_blk_size = 128;
355		output->grph.rgb.independent_64b_blks = false;
356		output->grph.rgb.dcc_controls.dcc_128_128_uncontrained = 1;
357		output->grph.rgb.dcc_controls.dcc_256_128_128 = 1;
358		break;
359	case dcc_control__256_64:
360	case dcc_control__256_64_64:
361		output->grph.rgb.max_uncompressed_blk_size = 256;
362		output->grph.rgb.max_compressed_blk_size = 64;
363		output->grph.rgb.independent_64b_blks = true;
364		output->grph.rgb.dcc_controls.dcc_256_64_64 = 1;
365		break;
366	case dcc_control__256_128_128:
367		output->grph.rgb.max_uncompressed_blk_size = 256;
368		output->grph.rgb.max_compressed_blk_size = 128;
369		output->grph.rgb.independent_64b_blks = false;
370		output->grph.rgb.dcc_controls.dcc_256_128_128 = 1;
371		break;
372	}
373	output->capable = true;
374	output->const_color_support = true;
375
376	return true;
377}
378
379void hubbub3_force_wm_propagate_to_pipes(struct hubbub *hubbub)
380{
381	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
382	uint32_t refclk_mhz = hubbub->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
383	uint32_t prog_wm_value = convert_and_clamp(hubbub1->watermarks.a.urgent_ns,
384			refclk_mhz, 0x1fffff);
385
386	REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,
387			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value,
388			DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A, prog_wm_value);
389}
390
391void hubbub3_force_pstate_change_control(struct hubbub *hubbub,
392		bool force, bool allow)
393{
394	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
395
396	REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
397			DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, allow,
398			DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, force);
399}
400
401/* Copy values from WM set A to all other sets */
402void hubbub3_init_watermarks(struct hubbub *hubbub)
403{
404	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
405	uint32_t reg;
406
407	reg = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
408	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg);
409	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, reg);
410	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, reg);
411
412	reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A);
413	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg);
414	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, reg);
415	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, reg);
416
417	reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A);
418	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg);
419	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, reg);
420	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, reg);
421
422	reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A);
423	REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg);
424	REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, reg);
425	REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, reg);
426
427	reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
428	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, reg);
429	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, reg);
430	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, reg);
431
432	reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
433	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg);
434	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, reg);
435	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, reg);
436
437	reg = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
438	REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, reg);
439	REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, reg);
440	REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, reg);
441}
442
443void hubbub3_read_reg_state(struct hubbub *hubbub, struct dcn_hubbub_reg_state *hubbub_reg_state)
444{
445	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
446
447	hubbub_reg_state->det0_ctrl = REG_READ(DCHUBBUB_DET0_CTRL);
448	hubbub_reg_state->det1_ctrl = REG_READ(DCHUBBUB_DET1_CTRL);
449	hubbub_reg_state->det2_ctrl = REG_READ(DCHUBBUB_DET2_CTRL);
450	hubbub_reg_state->det3_ctrl = REG_READ(DCHUBBUB_DET3_CTRL);
451	hubbub_reg_state->compbuf_ctrl = REG_READ(DCHUBBUB_COMPBUF_CTRL);
452}
453
454static const struct hubbub_funcs hubbub30_funcs = {
455	.update_dchub = hubbub2_update_dchub,
456	.init_dchub_sys_ctx = hubbub3_init_dchub_sys_ctx,
457	.init_vm_ctx = hubbub2_init_vm_ctx,
458	.dcc_support_swizzle = hubbub3_dcc_support_swizzle,
459	.dcc_support_pixel_format = hubbub2_dcc_support_pixel_format,
460	.get_dcc_compression_cap = hubbub3_get_dcc_compression_cap,
461	.wm_read_state = hubbub21_wm_read_state,
462	.get_dchub_ref_freq = hubbub2_get_dchub_ref_freq,
463	.program_watermarks = hubbub3_program_watermarks,
464	.allow_self_refresh_control = hubbub1_allow_self_refresh_control,
465	.is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,
466	.verify_allow_pstate_change_high = hubbub1_verify_allow_pstate_change_high,
467	.force_wm_propagate_to_pipes = hubbub3_force_wm_propagate_to_pipes,
468	.force_pstate_change_control = hubbub3_force_pstate_change_control,
469	.init_watermarks = hubbub3_init_watermarks,
470	.hubbub_read_state = hubbub2_read_state,
471	.hubbub_read_reg_state = hubbub3_read_reg_state
472};
473
474void hubbub3_construct(struct dcn20_hubbub *hubbub3,
475	struct dc_context *ctx,
476	const struct dcn_hubbub_registers *hubbub_regs,
477	const struct dcn_hubbub_shift *hubbub_shift,
478	const struct dcn_hubbub_mask *hubbub_mask)
479{
480	hubbub3->base.ctx = ctx;
481	hubbub3->base.funcs = &hubbub30_funcs;
482	hubbub3->regs = hubbub_regs;
483	hubbub3->shifts = hubbub_shift;
484	hubbub3->masks = hubbub_mask;
485
486	hubbub3->debug_test_index_pstate = 0xB;
487	hubbub3->detile_buf_size = 184 * 1024; /* 184KB for DCN3 */
488}
489