hw_factory_dcn401.c

  1// SPDX-License-Identifier: MIT
  2//
  3// Copyright 2024 Advanced Micro Devices, Inc.
  4
  5#include "dm_services.h"
  6#include "include/gpio_types.h"
  7#include "../hw_factory.h"
  8
  9
 10#include "../hw_gpio.h"
 11#include "../hw_ddc.h"
 12#include "../hw_hpd.h"
 13#include "../hw_generic.h"
 14
 15
 16#include "dcn/dcn_4_1_0_offset.h"
 17#include "dcn/dcn_4_1_0_sh_mask.h"
 18
 19#include "reg_helper.h"
 20#include "../hpd_regs.h"
 21#include "hw_factory_dcn401.h"
 22
 23#define DCN_BASE__INST0_SEG2                       0x000034C0
 24
 25/* begin *********************
 26 * macros to expend register list macro defined in HW object header file */
 27
 28/* DCN */
 29#define block HPD
 30#define reg_num 0
 31
 32#undef BASE_INNER
 33#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 34
 35#define BASE(seg) BASE_INNER(seg)
 36
 37
 38
 39#define REG(reg_name)\
 40		BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
 41
 42#define SF_HPD(reg_name, field_name, post_fix)\
 43	.field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
 44
 45#define REGI(reg_name, block, id)\
 46	BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 47				reg ## block ## id ## _ ## reg_name
 48
 49#define SF(reg_name, field_name, post_fix)\
 50	.field_name = reg_name ## __ ## field_name ## post_fix
 51
 52/* macros to expend register list macro defined in HW object header file
 53 * end *********************/
 54
 55
 56
 57#define hpd_regs(id) \
 58{\
 59	HPD_REG_LIST(id)\
 60}
 61
 62static const struct hpd_registers hpd_regs[] = {
 63	hpd_regs(0),
 64	hpd_regs(1),
 65	hpd_regs(2),
 66	hpd_regs(3),
 67//	hpd_regs(4),
 68};
 69
 70static const struct hpd_sh_mask hpd_shift = {
 71		HPD_MASK_SH_LIST(__SHIFT)
 72};
 73
 74static const struct hpd_sh_mask hpd_mask = {
 75		HPD_MASK_SH_LIST(_MASK)
 76};
 77
 78#include "../ddc_regs.h"
 79
 80 /* set field name */
 81#define SF_DDC(reg_name, field_name, post_fix)\
 82	.field_name = reg_name ## __ ## field_name ## post_fix
 83
 84static const struct ddc_registers ddc_data_regs_dcn[] = {
 85	ddc_data_regs_dcn2(1),
 86	ddc_data_regs_dcn2(2),
 87	ddc_data_regs_dcn2(3),
 88	ddc_data_regs_dcn2(4),
 89	{
 90		// add a dummy entry for cases no such port
 91		{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
 92		.ddc_setup = 0,
 93		.phy_aux_cntl = 0,
 94		.dc_gpio_aux_ctrl_5 = 0
 95	},
 96	{
 97		// add a dummy entry for cases no such port
 98		{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
 99		.ddc_setup = 0,
100		.phy_aux_cntl = 0,
101		.dc_gpio_aux_ctrl_5 = 0
102	},
103	{
104			DDC_GPIO_VGA_REG_LIST(DATA),
105			.ddc_setup = 0,
106			.phy_aux_cntl = 0,
107			.dc_gpio_aux_ctrl_5 = 0
108	}
109};
110
111static const struct ddc_registers ddc_clk_regs_dcn[] = {
112	ddc_clk_regs_dcn2(1),
113	ddc_clk_regs_dcn2(2),
114	ddc_clk_regs_dcn2(3),
115	ddc_clk_regs_dcn2(4),
116	{
117		// add a dummy entry for cases no such port
118		{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
119		.ddc_setup = 0,
120		.phy_aux_cntl = 0,
121		.dc_gpio_aux_ctrl_5 = 0
122	},
123	{
124		// add a dummy entry for cases no such port
125		{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
126		.ddc_setup = 0,
127		.phy_aux_cntl = 0,
128		.dc_gpio_aux_ctrl_5 = 0
129	},
130	{
131			DDC_GPIO_VGA_REG_LIST(CLK),
132			.ddc_setup = 0,
133			.phy_aux_cntl = 0,
134			.dc_gpio_aux_ctrl_5 = 0
135	}
136};
137
138static const struct ddc_sh_mask ddc_shift[] = {
139	DDC_MASK_SH_LIST_DCN2(__SHIFT, 1),
140	DDC_MASK_SH_LIST_DCN2(__SHIFT, 2),
141	DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),
142	DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),
143	DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),
144	DDC_MASK_SH_LIST_DCN2(__SHIFT, 6),
145	DDC_MASK_SH_LIST_DCN2_VGA(__SHIFT)
146};
147
148static const struct ddc_sh_mask ddc_mask[] = {
149	DDC_MASK_SH_LIST_DCN2(_MASK, 1),
150	DDC_MASK_SH_LIST_DCN2(_MASK, 2),
151	DDC_MASK_SH_LIST_DCN2(_MASK, 3),
152	DDC_MASK_SH_LIST_DCN2(_MASK, 4),
153	DDC_MASK_SH_LIST_DCN2(_MASK, 5),
154	DDC_MASK_SH_LIST_DCN2(_MASK, 6),
155	DDC_MASK_SH_LIST_DCN2_VGA(_MASK)
156};
157
158#include "../generic_regs.h"
159
160/* set field name */
161#define SF_GENERIC(reg_name, field_name, post_fix)\
162	.field_name = reg_name ## __ ## field_name ## post_fix
163
164#define generic_regs(id) \
165{\
166	GENERIC_REG_LIST(id)\
167}
168
169static const struct generic_registers generic_regs[] = {
170	generic_regs(A),
171	generic_regs(B),
172};
173
174static const struct generic_sh_mask generic_shift[] = {
175	GENERIC_MASK_SH_LIST(__SHIFT, A),
176	GENERIC_MASK_SH_LIST(__SHIFT, B),
177};
178
179static const struct generic_sh_mask generic_mask[] = {
180	GENERIC_MASK_SH_LIST(_MASK, A),
181	GENERIC_MASK_SH_LIST(_MASK, B),
182};
183
184static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)
185{
186	struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin);
187
188	generic->regs = &generic_regs[en];
189	generic->shifts = &generic_shift[en];
190	generic->masks = &generic_mask[en];
191	generic->base.regs = &generic_regs[en].gpio;
192}
193
194static void define_ddc_registers(
195		struct hw_gpio_pin *pin,
196		uint32_t en)
197{
198	struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
199
200	switch (pin->id) {
201	case GPIO_ID_DDC_DATA:
202		ddc->regs = &ddc_data_regs_dcn[en];
203		ddc->base.regs = &ddc_data_regs_dcn[en].gpio;
204		break;
205	case GPIO_ID_DDC_CLOCK:
206		ddc->regs = &ddc_clk_regs_dcn[en];
207		ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;
208		break;
209	default:
210		ASSERT_CRITICAL(false);
211		return;
212	}
213
214	ddc->shifts = &ddc_shift[en];
215	ddc->masks = &ddc_mask[en];
216
217}
218
219static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
220{
221	struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
222
223	hpd->regs = &hpd_regs[en];
224	hpd->shifts = &hpd_shift;
225	hpd->masks = &hpd_mask;
226	hpd->base.regs = &hpd_regs[en].gpio;
227}
228
229
230/* function table */
231static const struct hw_factory_funcs funcs = {
232	.init_ddc_data = dal_hw_ddc_init,
233	.init_generic = dal_hw_generic_init,
234	.init_hpd = dal_hw_hpd_init,
235	.get_ddc_pin = dal_hw_ddc_get_pin,
236	.get_hpd_pin = dal_hw_hpd_get_pin,
237	.get_generic_pin = dal_hw_generic_get_pin,
238	.define_hpd_registers = define_hpd_registers,
239	.define_ddc_registers = define_ddc_registers,
240	.define_generic_registers = define_generic_registers
241};
242
243/*
244 * dal_hw_factory_dcn401_init
245 *
246 * @brief
247 * Initialize HW factory function pointers and pin info
248 *
249 * @param
250 * struct hw_factory *factory - [out] struct of function pointers
251 */
252void dal_hw_factory_dcn401_init(struct hw_factory *factory)
253{
254	factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
255	factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
256	factory->number_of_pins[GPIO_ID_GENERIC] = 4;
257	factory->number_of_pins[GPIO_ID_HPD] = 5;
258	factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28;
259	factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
260	factory->number_of_pins[GPIO_ID_SYNC] = 0;
261	factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/
262
263	factory->funcs = &funcs;
264}