hw_factory_dcn32.c

  1/*
  2 * Copyright 2022 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25#include "dm_services.h"
 26#include "include/gpio_types.h"
 27#include "../hw_factory.h"
 28
 29
 30#include "../hw_gpio.h"
 31#include "../hw_ddc.h"
 32#include "../hw_hpd.h"
 33#include "../hw_generic.h"
 34
 35#include "hw_factory_dcn32.h"
 36
 37#include "dcn/dcn_3_2_0_offset.h"
 38#include "dcn/dcn_3_2_0_sh_mask.h"
 39
 40#include "reg_helper.h"
 41#include "../hpd_regs.h"
 42
 43#define DCN_BASE__INST0_SEG2                       0x000034C0
 44
 45/* begin *********************
 46 * macros to expend register list macro defined in HW object header file */
 47
 48/* DCN */
 49#define block HPD
 50#define reg_num 0
 51
 52#undef BASE_INNER
 53#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 54
 55#define BASE(seg) BASE_INNER(seg)
 56
 57
 58
 59#define REG(reg_name)\
 60		BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
 61
 62#define SF_HPD(reg_name, field_name, post_fix)\
 63	.field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
 64
 65#define REGI(reg_name, block, id)\
 66	BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 67				reg ## block ## id ## _ ## reg_name
 68
 69#define SF(reg_name, field_name, post_fix)\
 70	.field_name = reg_name ## __ ## field_name ## post_fix
 71
 72/* macros to expend register list macro defined in HW object header file
 73 * end *********************/
 74
 75
 76
 77#define hpd_regs(id) \
 78{\
 79	HPD_REG_LIST(id)\
 80}
 81
 82static const struct hpd_registers hpd_regs[] = {
 83	hpd_regs(0),
 84	hpd_regs(1),
 85	hpd_regs(2),
 86	hpd_regs(3),
 87	hpd_regs(4),
 88};
 89
 90static const struct hpd_sh_mask hpd_shift = {
 91		HPD_MASK_SH_LIST(__SHIFT)
 92};
 93
 94static const struct hpd_sh_mask hpd_mask = {
 95		HPD_MASK_SH_LIST(_MASK)
 96};
 97
 98#include "../ddc_regs.h"
 99
100 /* set field name */
101#define SF_DDC(reg_name, field_name, post_fix)\
102	.field_name = reg_name ## __ ## field_name ## post_fix
103
104static const struct ddc_registers ddc_data_regs_dcn[] = {
105	ddc_data_regs_dcn2(1),
106	ddc_data_regs_dcn2(2),
107	ddc_data_regs_dcn2(3),
108	ddc_data_regs_dcn2(4),
109	ddc_data_regs_dcn2(5),
110	{
111		// add a dummy entry for cases no such port
112		{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
113		.ddc_setup = 0,
114		.phy_aux_cntl = 0,
115		.dc_gpio_aux_ctrl_5 = 0
116	},
117	{
118			DDC_GPIO_VGA_REG_LIST(DATA),
119			.ddc_setup = 0,
120			.phy_aux_cntl = 0,
121			.dc_gpio_aux_ctrl_5 = 0
122	}
123};
124
125static const struct ddc_registers ddc_clk_regs_dcn[] = {
126	ddc_clk_regs_dcn2(1),
127	ddc_clk_regs_dcn2(2),
128	ddc_clk_regs_dcn2(3),
129	ddc_clk_regs_dcn2(4),
130	ddc_clk_regs_dcn2(5),
131	{
132		// add a dummy entry for cases no such port
133		{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
134		.ddc_setup = 0,
135		.phy_aux_cntl = 0,
136		.dc_gpio_aux_ctrl_5 = 0
137	},
138	{
139			DDC_GPIO_VGA_REG_LIST(CLK),
140			.ddc_setup = 0,
141			.phy_aux_cntl = 0,
142			.dc_gpio_aux_ctrl_5 = 0
143	}
144};
145
146static const struct ddc_sh_mask ddc_shift[] = {
147	DDC_MASK_SH_LIST_DCN2(__SHIFT, 1),
148	DDC_MASK_SH_LIST_DCN2(__SHIFT, 2),
149	DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),
150	DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),
151	DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),
152	DDC_MASK_SH_LIST_DCN2(__SHIFT, 6),
153	DDC_MASK_SH_LIST_DCN2_VGA(__SHIFT)
154};
155
156static const struct ddc_sh_mask ddc_mask[] = {
157	DDC_MASK_SH_LIST_DCN2(_MASK, 1),
158	DDC_MASK_SH_LIST_DCN2(_MASK, 2),
159	DDC_MASK_SH_LIST_DCN2(_MASK, 3),
160	DDC_MASK_SH_LIST_DCN2(_MASK, 4),
161	DDC_MASK_SH_LIST_DCN2(_MASK, 5),
162	DDC_MASK_SH_LIST_DCN2(_MASK, 6),
163	DDC_MASK_SH_LIST_DCN2_VGA(_MASK)
164};
165
166#include "../generic_regs.h"
167
168/* set field name */
169#define SF_GENERIC(reg_name, field_name, post_fix)\
170	.field_name = reg_name ## __ ## field_name ## post_fix
171
172#define generic_regs(id) \
173{\
174	GENERIC_REG_LIST(id)\
175}
176
177static const struct generic_registers generic_regs[] = {
178	generic_regs(A),
179	generic_regs(B),
180};
181
182static const struct generic_sh_mask generic_shift[] = {
183	GENERIC_MASK_SH_LIST(__SHIFT, A),
184	GENERIC_MASK_SH_LIST(__SHIFT, B),
185};
186
187static const struct generic_sh_mask generic_mask[] = {
188	GENERIC_MASK_SH_LIST(_MASK, A),
189	GENERIC_MASK_SH_LIST(_MASK, B),
190};
191
192static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)
193{
194	struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin);
195
196	generic->regs = &generic_regs[en];
197	generic->shifts = &generic_shift[en];
198	generic->masks = &generic_mask[en];
199	generic->base.regs = &generic_regs[en].gpio;
200}
201
202static void define_ddc_registers(
203		struct hw_gpio_pin *pin,
204		uint32_t en)
205{
206	struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
207
208	switch (pin->id) {
209	case GPIO_ID_DDC_DATA:
210		ddc->regs = &ddc_data_regs_dcn[en];
211		ddc->base.regs = &ddc_data_regs_dcn[en].gpio;
212		break;
213	case GPIO_ID_DDC_CLOCK:
214		ddc->regs = &ddc_clk_regs_dcn[en];
215		ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;
216		break;
217	default:
218		ASSERT_CRITICAL(false);
219		return;
220	}
221
222	ddc->shifts = &ddc_shift[en];
223	ddc->masks = &ddc_mask[en];
224
225}
226
227static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
228{
229	struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
230
231	hpd->regs = &hpd_regs[en];
232	hpd->shifts = &hpd_shift;
233	hpd->masks = &hpd_mask;
234	hpd->base.regs = &hpd_regs[en].gpio;
235}
236
237
238/* fucntion table */
239static const struct hw_factory_funcs funcs = {
240	.init_ddc_data = dal_hw_ddc_init,
241	.init_generic = dal_hw_generic_init,
242	.init_hpd = dal_hw_hpd_init,
243	.get_ddc_pin = dal_hw_ddc_get_pin,
244	.get_hpd_pin = dal_hw_hpd_get_pin,
245	.get_generic_pin = dal_hw_generic_get_pin,
246	.define_hpd_registers = define_hpd_registers,
247	.define_ddc_registers = define_ddc_registers,
248	.define_generic_registers = define_generic_registers
249};
250/*
251 * dal_hw_factory_dcn32_init
252 *
253 * @brief
254 * Initialize HW factory function pointers and pin info
255 *
256 * @param
257 * struct hw_factory *factory - [out] struct of function pointers
258 */
259void dal_hw_factory_dcn32_init(struct hw_factory *factory)
260{
261	factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
262	factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
263	factory->number_of_pins[GPIO_ID_GENERIC] = 4;
264	factory->number_of_pins[GPIO_ID_HPD] = 5;
265	factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28;
266	factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
267	factory->number_of_pins[GPIO_ID_SYNC] = 0;
268	factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/
269
270	factory->funcs = &funcs;
271}