hw_factory_dcn21.c

  1/*
  2 * Copyright 2013-15 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25#include "dm_services.h"
 26#include "include/gpio_types.h"
 27#include "../hw_factory.h"
 28
 29
 30#include "../hw_gpio.h"
 31#include "../hw_ddc.h"
 32#include "../hw_hpd.h"
 33#include "../hw_generic.h"
 34
 35#include "hw_factory_dcn21.h"
 36
 37#include "dcn/dcn_2_1_0_offset.h"
 38#include "dcn/dcn_2_1_0_sh_mask.h"
 39#include "renoir_ip_offset.h"
 40
 41#include "reg_helper.h"
 42#include "../hpd_regs.h"
 43/* begin *********************
 44 * macros to expend register list macro defined in HW object header file */
 45
 46/* DCN */
 47#define block HPD
 48#define reg_num 0
 49
 50#undef BASE_INNER
 51#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
 52
 53#define BASE(seg) BASE_INNER(seg)
 54
 55
 56
 57#define REG(reg_name)\
 58		BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
 59
 60#define SF_HPD(reg_name, field_name, post_fix)\
 61	.field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
 62
 63#define REGI(reg_name, block, id)\
 64	BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 65				mm ## block ## id ## _ ## reg_name
 66
 67#define SF(reg_name, field_name, post_fix)\
 68	.field_name = reg_name ## __ ## field_name ## post_fix
 69
 70/* macros to expend register list macro defined in HW object header file
 71 * end *********************/
 72
 73
 74
 75#define hpd_regs(id) \
 76{\
 77	HPD_REG_LIST(id)\
 78}
 79
 80static const struct hpd_registers hpd_regs[] = {
 81	hpd_regs(0),
 82	hpd_regs(1),
 83	hpd_regs(2),
 84	hpd_regs(3),
 85	hpd_regs(4),
 86};
 87
 88static const struct hpd_sh_mask hpd_shift = {
 89		HPD_MASK_SH_LIST(__SHIFT)
 90};
 91
 92static const struct hpd_sh_mask hpd_mask = {
 93		HPD_MASK_SH_LIST(_MASK)
 94};
 95
 96#include "../ddc_regs.h"
 97
 98 /* set field name */
 99#define SF_DDC(reg_name, field_name, post_fix)\
100	.field_name = reg_name ## __ ## field_name ## post_fix
101
102static const struct ddc_registers ddc_data_regs_dcn[] = {
103	ddc_data_regs_dcn2(1),
104	ddc_data_regs_dcn2(2),
105	ddc_data_regs_dcn2(3),
106	ddc_data_regs_dcn2(4),
107	ddc_data_regs_dcn2(5),
108};
109
110static const struct ddc_registers ddc_clk_regs_dcn[] = {
111	ddc_clk_regs_dcn2(1),
112	ddc_clk_regs_dcn2(2),
113	ddc_clk_regs_dcn2(3),
114	ddc_clk_regs_dcn2(4),
115	ddc_clk_regs_dcn2(5),
116};
117
118static const struct ddc_sh_mask ddc_shift[] = {
119	DDC_MASK_SH_LIST_DCN2(__SHIFT, 1),
120	DDC_MASK_SH_LIST_DCN2(__SHIFT, 2),
121	DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),
122	DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),
123	DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),
124	DDC_MASK_SH_LIST_DCN2(__SHIFT, 6)
125};
126
127static const struct ddc_sh_mask ddc_mask[] = {
128	DDC_MASK_SH_LIST_DCN2(_MASK, 1),
129	DDC_MASK_SH_LIST_DCN2(_MASK, 2),
130	DDC_MASK_SH_LIST_DCN2(_MASK, 3),
131	DDC_MASK_SH_LIST_DCN2(_MASK, 4),
132	DDC_MASK_SH_LIST_DCN2(_MASK, 5),
133	DDC_MASK_SH_LIST_DCN2(_MASK, 6)
134};
135
136#include "../generic_regs.h"
137
138/* set field name */
139#define SF_GENERIC(reg_name, field_name, post_fix)\
140	.field_name = reg_name ## __ ## field_name ## post_fix
141
142#define generic_regs(id) \
143{\
144	GENERIC_REG_LIST(id)\
145}
146
147static const struct generic_registers generic_regs[] = {
148	generic_regs(A),
149};
150
151static const struct generic_sh_mask generic_shift[] = {
152	GENERIC_MASK_SH_LIST(__SHIFT, A),
153};
154
155static const struct generic_sh_mask generic_mask[] = {
156	GENERIC_MASK_SH_LIST(_MASK, A),
157};
158
159static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)
160{
161	struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin);
162
163	generic->regs = &generic_regs[en];
164	generic->shifts = &generic_shift[en];
165	generic->masks = &generic_mask[en];
166	generic->base.regs = &generic_regs[en].gpio;
167}
168
169static void define_ddc_registers(
170		struct hw_gpio_pin *pin,
171		uint32_t en)
172{
173	struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
174
175	switch (pin->id) {
176	case GPIO_ID_DDC_DATA:
177		ddc->regs = &ddc_data_regs_dcn[en];
178		ddc->base.regs = &ddc_data_regs_dcn[en].gpio;
179		break;
180	case GPIO_ID_DDC_CLOCK:
181		ddc->regs = &ddc_clk_regs_dcn[en];
182		ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;
183		break;
184	default:
185		ASSERT_CRITICAL(false);
186		return;
187	}
188
189	ddc->shifts = &ddc_shift[en];
190	ddc->masks = &ddc_mask[en];
191
192}
193
194static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
195{
196	struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
197
198	hpd->regs = &hpd_regs[en];
199	hpd->shifts = &hpd_shift;
200	hpd->masks = &hpd_mask;
201	hpd->base.regs = &hpd_regs[en].gpio;
202}
203
204
205/* function table */
206static const struct hw_factory_funcs funcs = {
207	.init_ddc_data = dal_hw_ddc_init,
208	.init_generic = dal_hw_generic_init,
209	.init_hpd = dal_hw_hpd_init,
210	.get_ddc_pin = dal_hw_ddc_get_pin,
211	.get_hpd_pin = dal_hw_hpd_get_pin,
212	.get_generic_pin = dal_hw_generic_get_pin,
213	.define_hpd_registers = define_hpd_registers,
214	.define_ddc_registers = define_ddc_registers,
215	.define_generic_registers = define_generic_registers
216};
217/*
218 * dal_hw_factory_dcn10_init
219 *
220 * @brief
221 * Initialize HW factory function pointers and pin info
222 *
223 * @param
224 * struct hw_factory *factory - [out] struct of function pointers
225 */
226void dal_hw_factory_dcn21_init(struct hw_factory *factory)
227{
228	/*TODO check ASIC CAPs*/
229	factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
230	factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
231	factory->number_of_pins[GPIO_ID_GENERIC] = 4;
232	factory->number_of_pins[GPIO_ID_HPD] = 6;
233	factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28;
234	factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
235	factory->number_of_pins[GPIO_ID_SYNC] = 0;
236	factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/
237
238	factory->funcs = &funcs;
239}
240