FILE
dcn401_dsc.h
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linux-6.19.14/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
1// SPDX-License-Identifier: MIT 2// 3// Copyright 2024 Advanced Micro Devices, Inc. 4 5#ifndef __DCN401_DSC_H__ 6#define __DCN401_DSC_H__ 7 8#include "dsc.h" 9#include "dsc/dscc_types.h" 10#include "dcn20/dcn20_dsc.h" 11#include <drm/display/drm_dsc.h> 12 13#define TO_DCN401_DSC(dsc)\ 14 container_of(dsc, struct dcn401_dsc, base) 15 16#define DSC_REG_LIST_SH_MASK_DCN401(mask_sh)\ 17 DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_CLOCK_EN, mask_sh), \ 18 DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DISPCLK_R_GATE_DIS, mask_sh), \ 19 DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DSCCLK_R_GATE_DIS, mask_sh), \ 20 DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_FGCG_REP_DIS, mask_sh), \ 21 DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_DBG_EN, mask_sh), \ 22 DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_TEST_CLOCK_MUX_SEL, mask_sh), \ 23 DSC_SF(DSCC0_DSCC_CONFIG0, ICH_RESET_AT_END_OF_LINE, mask_sh), \ 24 DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_PER_LINE, mask_sh), \ 25 DSC_SF(DSCC0_DSCC_CONFIG0, ALTERNATE_ICH_ENCODING_EN, mask_sh), \ 26 DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, mask_sh), \ 27 DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, mask_sh), \ 28 /*DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_DISABLE_ICH, mask_sh),*/ \ 29 DSC_SF(DSCC0_DSCC_STATUS, DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \ 30 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0, mask_sh), \ 31 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1, mask_sh), \ 32 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2, mask_sh), \ 33 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3, mask_sh), \ 34 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0, mask_sh), \ 35 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1, mask_sh), \ 36 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2, mask_sh), \ 37 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3, mask_sh), \ 38 DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0, mask_sh), \ 39 DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1, mask_sh), \ 40 DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2, mask_sh), \ 41 DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3, mask_sh), \ 42 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0, mask_sh), \ 43 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1, mask_sh), \ 44 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2, mask_sh), \ 45 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3, mask_sh), \ 46 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0, mask_sh), \ 47 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1, mask_sh), \ 48 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2, mask_sh), \ 49 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3, mask_sh), \ 50 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED, mask_sh), \ 51 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0, mask_sh), \ 52 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1, mask_sh), \ 53 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2, mask_sh), \ 54 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3, mask_sh), \ 55 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0, mask_sh), \ 56 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1, mask_sh), \ 57 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2, mask_sh), \ 58 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3, mask_sh), \ 59 DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_END_OF_FRAME_NOT_REACHED_CLEAR, mask_sh), \ 60 DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0, mask_sh), \ 61 DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1, mask_sh), \ 62 DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2, mask_sh), \ 63 DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3, mask_sh), \ 64 DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0, mask_sh), \ 65 DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1, mask_sh), \ 66 DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2, mask_sh), \ 67 DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3, mask_sh), \ 68 DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN, mask_sh), \ 69 DSC_SF(DSCC0_DSCC_PPS_CONFIG0, DSC_VERSION_MINOR, mask_sh), \ 70 DSC_SF(DSCC0_DSCC_PPS_CONFIG0, DSC_VERSION_MAJOR, mask_sh), \ 71 DSC_SF(DSCC0_DSCC_PPS_CONFIG0, PPS_IDENTIFIER, mask_sh), \ 72 DSC_SF(DSCC0_DSCC_PPS_CONFIG0, LINEBUF_DEPTH, mask_sh), \ 73 DSC2_SF(DSCC0, DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, mask_sh), \ 74 DSC_SF(DSCC0_DSCC_PPS_CONFIG1, BITS_PER_PIXEL, mask_sh), \ 75 DSC_SF(DSCC0_DSCC_PPS_CONFIG1, VBR_ENABLE, mask_sh), \ 76 DSC_SF(DSCC0_DSCC_PPS_CONFIG1, SIMPLE_422, mask_sh), \ 77 DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CONVERT_RGB, mask_sh), \ 78 DSC_SF(DSCC0_DSCC_PPS_CONFIG1, BLOCK_PRED_ENABLE, mask_sh), \ 79 DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_422, mask_sh), \ 80 DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_420, mask_sh), \ 81 DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CHUNK_SIZE, mask_sh), \ 82 DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_WIDTH, mask_sh), \ 83 DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_HEIGHT, mask_sh), \ 84 DSC_SF(DSCC0_DSCC_PPS_CONFIG3, SLICE_WIDTH, mask_sh), \ 85 DSC_SF(DSCC0_DSCC_PPS_CONFIG3, SLICE_HEIGHT, mask_sh), \ 86 DSC_SF(DSCC0_DSCC_PPS_CONFIG4, INITIAL_XMIT_DELAY, mask_sh), \ 87 DSC_SF(DSCC0_DSCC_PPS_CONFIG4, INITIAL_DEC_DELAY, mask_sh), \ 88 DSC_SF(DSCC0_DSCC_PPS_CONFIG5, INITIAL_SCALE_VALUE, mask_sh), \ 89 DSC_SF(DSCC0_DSCC_PPS_CONFIG5, SCALE_INCREMENT_INTERVAL, mask_sh), \ 90 DSC_SF(DSCC0_DSCC_PPS_CONFIG6, SCALE_DECREMENT_INTERVAL, mask_sh), \ 91 DSC_SF(DSCC0_DSCC_PPS_CONFIG6, FIRST_LINE_BPG_OFFSET, mask_sh), \ 92 DSC_SF(DSCC0_DSCC_PPS_CONFIG6, SECOND_LINE_BPG_OFFSET, mask_sh), \ 93 DSC_SF(DSCC0_DSCC_PPS_CONFIG7, NFL_BPG_OFFSET, mask_sh), \ 94 DSC_SF(DSCC0_DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, mask_sh), \ 95 DSC_SF(DSCC0_DSCC_PPS_CONFIG8, NSL_BPG_OFFSET, mask_sh), \ 96 DSC_SF(DSCC0_DSCC_PPS_CONFIG8, SECOND_LINE_OFFSET_ADJ, mask_sh), \ 97 DSC_SF(DSCC0_DSCC_PPS_CONFIG9, INITIAL_OFFSET, mask_sh), \ 98 DSC_SF(DSCC0_DSCC_PPS_CONFIG9, FINAL_OFFSET, mask_sh), \ 99 DSC_SF(DSCC0_DSCC_PPS_CONFIG10, FLATNESS_MIN_QP, mask_sh), \ 100 DSC_SF(DSCC0_DSCC_PPS_CONFIG10, FLATNESS_MAX_QP, mask_sh), \ 101 DSC_SF(DSCC0_DSCC_PPS_CONFIG10, RC_MODEL_SIZE, mask_sh), \ 102 DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_EDGE_FACTOR, mask_sh), \ 103 DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_QUANT_INCR_LIMIT0, mask_sh), \ 104 DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_QUANT_INCR_LIMIT1, mask_sh), \ 105 DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_TGT_OFFSET_LO, mask_sh), \ 106 DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_TGT_OFFSET_HI, mask_sh), \ 107 DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH0, mask_sh), \ 108 DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH1, mask_sh), \ 109 DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH2, mask_sh), \ 110 DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH3, mask_sh), \ 111 DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH4, mask_sh), \ 112 DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH5, mask_sh), \ 113 DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH6, mask_sh), \ 114 DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH7, mask_sh), \ 115 DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH8, mask_sh), \ 116 DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH9, mask_sh), \ 117 DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH10, mask_sh), \ 118 DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH11, mask_sh), \ 119 DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RC_BUF_THRESH12, mask_sh), \ 120 DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RC_BUF_THRESH13, mask_sh), \ 121 DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_MIN_QP0, mask_sh), \ 122 DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_MAX_QP0, mask_sh), \ 123 DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_BPG_OFFSET0, mask_sh), \ 124 DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MIN_QP1, mask_sh), \ 125 DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MAX_QP1, mask_sh), \ 126 DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_BPG_OFFSET1, mask_sh), \ 127 DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MIN_QP2, mask_sh), \ 128 DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MAX_QP2, mask_sh), \ 129 DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_BPG_OFFSET2, mask_sh), \ 130 DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MIN_QP3, mask_sh), \ 131 DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MAX_QP3, mask_sh), \ 132 DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_BPG_OFFSET3, mask_sh), \ 133 DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MIN_QP4, mask_sh), \ 134 DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MAX_QP4, mask_sh), \ 135 DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_BPG_OFFSET4, mask_sh), \ 136 DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MIN_QP5, mask_sh), \ 137 DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MAX_QP5, mask_sh), \ 138 DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_BPG_OFFSET5, mask_sh), \ 139 DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MIN_QP6, mask_sh), \ 140 DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MAX_QP6, mask_sh), \ 141 DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_BPG_OFFSET6, mask_sh), \ 142 DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MIN_QP7, mask_sh), \ 143 DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MAX_QP7, mask_sh), \ 144 DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_BPG_OFFSET7, mask_sh), \ 145 DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MIN_QP8, mask_sh), \ 146 DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MAX_QP8, mask_sh), \ 147 DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_BPG_OFFSET8, mask_sh), \ 148 DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MIN_QP9, mask_sh), \ 149 DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MAX_QP9, mask_sh), \ 150 DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_BPG_OFFSET9, mask_sh), \ 151 DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MIN_QP10, mask_sh), \ 152 DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MAX_QP10, mask_sh), \ 153 DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_BPG_OFFSET10, mask_sh), \ 154 DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MIN_QP11, mask_sh), \ 155 DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MAX_QP11, mask_sh), \ 156 DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_BPG_OFFSET11, mask_sh), \ 157 DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MIN_QP12, mask_sh), \ 158 DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MAX_QP12, mask_sh), \ 159 DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_BPG_OFFSET12, mask_sh), \ 160 DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MIN_QP13, mask_sh), \ 161 DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MAX_QP13, mask_sh), \ 162 DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_BPG_OFFSET13, mask_sh), \ 163 DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MIN_QP14, mask_sh), \ 164 DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MAX_QP14, mask_sh), \ 165 DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_BPG_OFFSET14, mask_sh), \ 166 DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL0, DSCC_DEFAULT_MEM_LOW_POWER_STATE, mask_sh), \ 167 DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL0, DSCC_MEM_PWR_FORCE, mask_sh), \ 168 DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL0, DSCC_MEM_PWR_DIS, mask_sh), \ 169 DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL0, DSCC_MEM_PWR_STATE, mask_sh), \ 170 DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL1, DSCC_DEFAULT_MEM_LOW_POWER_STATE, mask_sh), \ 171 DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL1, DSCC_MEM_PWR_FORCE, mask_sh), \ 172 DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL1, DSCC_MEM_PWR_DIS, mask_sh), \ 173 DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL1, DSCC_MEM_PWR_STATE, mask_sh), \ 174 DSC_SF(DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC_R_Y_SQUARED_ERROR_LOWER, mask_sh), \ 175 DSC_SF(DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC_R_Y_SQUARED_ERROR_UPPER, mask_sh), \ 176 DSC_SF(DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC_G_CB_SQUARED_ERROR_LOWER, mask_sh), \ 177 DSC_SF(DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC_G_CB_SQUARED_ERROR_UPPER, mask_sh), \ 178 DSC_SF(DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC_B_CR_SQUARED_ERROR_LOWER, mask_sh), \ 179 DSC_SF(DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC_B_CR_SQUARED_ERROR_UPPER, mask_sh), \ 180 DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR0, DSCC_R_Y_MAX_ABS_ERROR, mask_sh), \ 181 DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR0, DSCC_G_CB_MAX_ABS_ERROR, mask_sh), \ 182 DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR1, DSCC_B_CR_MAX_ABS_ERROR, mask_sh), \ 183 DSC_SF(DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0, DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0, mask_sh), \ 184 DSC_SF(DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1, DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1, mask_sh), \ 185 DSC_SF(DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2, DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2, mask_sh), \ 186 DSC_SF(DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3, DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3, mask_sh), \ 187 DSC_SF(DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0, DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0, mask_sh), \ 188 DSC_SF(DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1, DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1, mask_sh), \ 189 DSC_SF(DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2, DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2, mask_sh), \ 190 DSC_SF(DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3, DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3, mask_sh), \ 191 DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS0_ROTATE, mask_sh), \ 192 DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS1_ROTATE, mask_sh), \ 193 DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS2_ROTATE, mask_sh), \ 194 DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS3_ROTATE, mask_sh), \ 195 DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_PIXEL_FORMAT, mask_sh), \ 196 DSC2_SF(DSCCIF0, DSCCIF_CONFIG0__BITS_PER_COMPONENT, mask_sh), \ 197 DSC_SF(DSCCIF0_DSCCIF_CONFIG0, DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \ 198 DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, mask_sh), \ 199 DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh), \ 200 DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, mask_sh) 201 202struct dcn401_dsc_registers { 203 uint32_t DSC_TOP_CONTROL; 204 uint32_t DSC_DEBUG_CONTROL; 205 uint32_t DSCC_CONFIG0; 206 uint32_t DSCC_CONFIG1; 207 uint32_t DSCC_STATUS; 208 uint32_t DSCC_INTERRUPT_CONTROL0; 209 uint32_t DSCC_INTERRUPT_CONTROL1; 210 uint32_t DSCC_INTERRUPT_STATUS0; 211 uint32_t DSCC_INTERRUPT_STATUS1; 212 uint32_t DSCC_PPS_CONFIG0; 213 uint32_t DSCC_PPS_CONFIG1; 214 uint32_t DSCC_PPS_CONFIG2; 215 uint32_t DSCC_PPS_CONFIG3; 216 uint32_t DSCC_PPS_CONFIG4; 217 uint32_t DSCC_PPS_CONFIG5; 218 uint32_t DSCC_PPS_CONFIG6; 219 uint32_t DSCC_PPS_CONFIG7; 220 uint32_t DSCC_PPS_CONFIG8; 221 uint32_t DSCC_PPS_CONFIG9; 222 uint32_t DSCC_PPS_CONFIG10; 223 uint32_t DSCC_PPS_CONFIG11; 224 uint32_t DSCC_PPS_CONFIG12; 225 uint32_t DSCC_PPS_CONFIG13; 226 uint32_t DSCC_PPS_CONFIG14; 227 uint32_t DSCC_PPS_CONFIG15; 228 uint32_t DSCC_PPS_CONFIG16; 229 uint32_t DSCC_PPS_CONFIG17; 230 uint32_t DSCC_PPS_CONFIG18; 231 uint32_t DSCC_PPS_CONFIG19; 232 uint32_t DSCC_PPS_CONFIG20; 233 uint32_t DSCC_PPS_CONFIG21; 234 uint32_t DSCC_PPS_CONFIG22; 235 uint32_t DSCC_MEM_POWER_CONTROL0; 236 uint32_t DSCC_MEM_POWER_CONTROL1; 237 uint32_t DSCC_R_Y_SQUARED_ERROR_LOWER; 238 uint32_t DSCC_R_Y_SQUARED_ERROR_UPPER; 239 uint32_t DSCC_G_CB_SQUARED_ERROR_LOWER; 240 uint32_t DSCC_G_CB_SQUARED_ERROR_UPPER; 241 uint32_t DSCC_B_CR_SQUARED_ERROR_LOWER; 242 uint32_t DSCC_B_CR_SQUARED_ERROR_UPPER; 243 uint32_t DSCC_MAX_ABS_ERROR0; 244 uint32_t DSCC_MAX_ABS_ERROR1; 245 uint32_t DSCC_TEST_DEBUG_BUS_ROTATE; 246 uint32_t DSCCIF_CONFIG0; 247 uint32_t DSCRM_DSC_FORWARD_CONFIG; 248 uint32_t DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0; 249 uint32_t DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1; 250 uint32_t DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2; 251 uint32_t DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3; 252 uint32_t DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0; 253 uint32_t DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1; 254 uint32_t DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2; 255 uint32_t DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3; 256}; 257 258#define DSC_FIELD_LIST_DCN401(type)\ 259 DSC_FIELD_LIST_DCN20(type); \ 260 type DSC_FGCG_REP_DIS; \ 261 type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0; \ 262 type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1; \ 263 type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2; \ 264 type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3; \ 265 type DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0; \ 266 type DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1; \ 267 type DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2; \ 268 type DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3; \ 269 type DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0; \ 270 type DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1; \ 271 type DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2; \ 272 type DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3; \ 273 type DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED; \ 274 type DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0; \ 275 type DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1; \ 276 type DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2; \ 277 type DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3; \ 278 type DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0; \ 279 type DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1; \ 280 type DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2; \ 281 type DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3; \ 282 type DSCC_END_OF_FRAME_NOT_REACHED_CLEAR; \ 283 type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0; \ 284 type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1; \ 285 type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2; \ 286 type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3; \ 287 type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0; \ 288 type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1; \ 289 type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2; \ 290 type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3; \ 291 type DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0; \ 292 type DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1; \ 293 type DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2; \ 294 type DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3; \ 295 type DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0; \ 296 type DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1; \ 297 type DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2; \ 298 type DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3; \ 299 type DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN; \ 300 type DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0; \ 301 type DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1; \ 302 type DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2; \ 303 type DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3; \ 304 type DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0; \ 305 type DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1; \ 306 type DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2; \ 307 type DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 308 309struct dcn401_dsc_shift { 310 DSC_FIELD_LIST_DCN401(uint8_t); 311}; 312 313struct dcn401_dsc_mask { 314 DSC_FIELD_LIST_DCN401(uint32_t); 315}; 316 317struct dcn401_dsc { 318 struct display_stream_compressor base; 319 const struct dcn401_dsc_registers *dsc_regs; 320 const struct dcn401_dsc_shift *dsc_shift; 321 const struct dcn401_dsc_mask *dsc_mask; 322 323 struct dsc_reg_values reg_vals; 324 325 int max_image_width; 326}; 327 328void dsc401_construct(struct dcn401_dsc *dsc, 329 struct dc_context *ctx, 330 int inst, 331 const struct dcn401_dsc_registers *dsc_regs, 332 const struct dcn401_dsc_shift *dsc_shift, 333 const struct dcn401_dsc_mask *dsc_mask); 334 335void dsc401_set_fgcg(struct dcn401_dsc *dsc401, bool enable); 336 337void dsc401_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s); 338bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg); 339void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 340 struct dsc_optc_config *dsc_optc_cfg); 341void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe); 342void dsc401_disable(struct display_stream_compressor *dsc); 343void dsc401_disconnect(struct display_stream_compressor *dsc); 344void dsc401_wait_disconnect_pending_clear(struct display_stream_compressor *dsc); 345#endif 346
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