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dcn401_dpp_dscl.c
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linux-6.19.14/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#include "dm_services.h" 27 28#include "core_types.h" 29 30#include "reg_helper.h" 31#include "dcn401/dcn401_dpp.h" 32#include "basics/conversion.h" 33 34 35#define NUM_PHASES 64 36#define HORZ_MAX_TAPS 8 37#define VERT_MAX_TAPS 8 38#define NUM_LEVELS 32 39#define BLACK_OFFSET_RGB_Y 0x0 40#define BLACK_OFFSET_CBCR 0x8000 41 42 43#define REG(reg)\ 44 dpp->tf_regs->reg 45 46#define CTX \ 47 dpp->base.ctx 48 49#undef FN 50#define FN(reg_name, field_name) \ 51 dpp->tf_shift->field_name, dpp->tf_mask->field_name 52 53enum dcn401_coef_filter_type_sel { 54 SCL_COEF_LUMA_VERT_FILTER = 0, 55 SCL_COEF_LUMA_HORZ_FILTER = 1, 56 SCL_COEF_CHROMA_VERT_FILTER = 2, 57 SCL_COEF_CHROMA_HORZ_FILTER = 3, 58 SCL_COEF_ALPHA_VERT_FILTER = 4, 59 SCL_COEF_ALPHA_HORZ_FILTER = 5, 60 SCL_COEF_VERTICAL_BLUR_SCALE = SCL_COEF_ALPHA_VERT_FILTER, 61 SCL_COEF_HORIZONTAL_BLUR_SCALE = SCL_COEF_ALPHA_HORZ_FILTER 62}; 63 64enum dscl_autocal_mode { 65 AUTOCAL_MODE_OFF = 0, 66 67 /* Autocal calculate the scaling ratio and initial phase and the 68 * DSCL_MODE_SEL must be set to 1 69 */ 70 AUTOCAL_MODE_AUTOSCALE = 1, 71 /* Autocal perform auto centering without replication and the 72 * DSCL_MODE_SEL must be set to 0 73 */ 74 AUTOCAL_MODE_AUTOCENTER = 2, 75 /* Autocal perform auto centering and auto replication and the 76 * DSCL_MODE_SEL must be set to 0 77 */ 78 AUTOCAL_MODE_AUTOREPLICATE = 3 79}; 80 81static int dpp401_dscl_get_pixel_depth_val(enum lb_pixel_depth depth) 82{ 83 if (depth == LB_PIXEL_DEPTH_30BPP) 84 return 0; /* 10 bpc */ 85 else if (depth == LB_PIXEL_DEPTH_24BPP) 86 return 1; /* 8 bpc */ 87 else if (depth == LB_PIXEL_DEPTH_18BPP) 88 return 2; /* 6 bpc */ 89 else if (depth == LB_PIXEL_DEPTH_36BPP) 90 return 3; /* 12 bpc */ 91 else { 92 ASSERT(0); 93 return -1; /* Unsupported */ 94 } 95} 96 97static bool dpp401_dscl_is_video_format(enum pixel_format format) 98{ 99 if (format >= PIXEL_FORMAT_VIDEO_BEGIN 100 && format <= PIXEL_FORMAT_VIDEO_END) 101 return true; 102 else 103 return false; 104} 105 106static bool dpp401_dscl_is_420_format(enum pixel_format format) 107{ 108 if (format == PIXEL_FORMAT_420BPP8 || 109 format == PIXEL_FORMAT_420BPP10) 110 return true; 111 else 112 return false; 113} 114 115static enum dcn401_dscl_mode_sel dpp401_dscl_get_dscl_mode( 116 struct dpp *dpp_base, 117 const struct scaler_data *data, 118 bool dbg_always_scale) 119{ 120 const long long one = dc_fixpt_one.value; 121 122 if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { 123 /* DSCL is processing data in fixed format */ 124 if (data->format == PIXEL_FORMAT_FP16) 125 return DCN401_DSCL_MODE_DSCL_BYPASS; 126 } 127 128 if (data->ratios.horz.value == one 129 && data->ratios.vert.value == one 130 && data->ratios.horz_c.value == one 131 && data->ratios.vert_c.value == one 132 && !dbg_always_scale) 133 return DCN401_DSCL_MODE_SCALING_444_BYPASS; 134 135 if (!dpp401_dscl_is_420_format(data->format)) { 136 if (dpp401_dscl_is_video_format(data->format)) 137 return DCN401_DSCL_MODE_SCALING_444_YCBCR_ENABLE; 138 else 139 return DCN401_DSCL_MODE_SCALING_444_RGB_ENABLE; 140 } 141 if (data->ratios.horz.value == one && data->ratios.vert.value == one) 142 return DCN401_DSCL_MODE_SCALING_420_LUMA_BYPASS; 143 if (data->ratios.horz_c.value == one && data->ratios.vert_c.value == one) 144 return DCN401_DSCL_MODE_SCALING_420_CHROMA_BYPASS; 145 146 return DCN401_DSCL_MODE_SCALING_420_YCBCR_ENABLE; 147} 148 149static void dpp401_power_on_dscl( 150 struct dpp *dpp_base, 151 bool power_on) 152{ 153 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); 154 155 if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) { 156 if (power_on) { 157 REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, 0); 158 REG_WAIT(DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, 0, 1, 5); 159 } else { 160 if (dpp->base.ctx->dc->debug.enable_mem_low_power.bits.dscl) { 161 dpp->base.ctx->dc->optimized_required = true; 162 dpp->base.deferred_reg_writes.bits.disable_dscl = true; 163 } else { 164 REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, 3); 165 } 166 } 167 } 168} 169 170 171static void dpp401_dscl_set_lb( 172 struct dcn401_dpp *dpp, 173 const struct line_buffer_params *lb_params, 174 enum lb_memory_config mem_size_config) 175{ 176 uint32_t max_partitions = 63; /* Currently hardcoded on all ASICs before DCN 3.2 */ 177 178 /* LB */ 179 if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { 180 /* DSCL caps: pixel data processed in fixed format */ 181 uint32_t pixel_depth = dpp401_dscl_get_pixel_depth_val(lb_params->depth); 182 uint32_t dyn_pix_depth = lb_params->dynamic_pixel_depth; 183 184 REG_SET_7(LB_DATA_FORMAT, 0, 185 PIXEL_DEPTH, pixel_depth, /* Pixel depth stored in LB */ 186 PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode, /* Pixel expansion mode */ 187 PIXEL_REDUCE_MODE, 1, /* Pixel reduction mode: Rounding */ 188 DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, /* Dynamic expansion pixel depth */ 189 DITHER_EN, 0, /* Dithering enable: Disabled */ 190 INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */ 191 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ 192 } else { 193 /* DSCL caps: pixel data processed in float format */ 194 REG_SET_2(LB_DATA_FORMAT, 0, 195 INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */ 196 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ 197 } 198 199 if (dpp->base.caps->max_lb_partitions == 31) 200 max_partitions = 31; 201 202 REG_SET_2(LB_MEMORY_CTRL, 0, 203 MEMORY_CONFIG, mem_size_config, 204 LB_MAX_PARTITIONS, max_partitions); 205} 206 207static const uint16_t *dpp401_dscl_get_filter_coeffs_64p(int taps, struct fixed31_32 ratio) 208{ 209 if (taps == 8) 210 return get_filter_8tap_64p(ratio); 211 else if (taps == 7) 212 return get_filter_7tap_64p(ratio); 213 else if (taps == 6) 214 return get_filter_6tap_64p(ratio); 215 else if (taps == 5) 216 return get_filter_5tap_64p(ratio); 217 else if (taps == 4) 218 return get_filter_4tap_64p(ratio); 219 else if (taps == 3) 220 return get_filter_3tap_64p(ratio); 221 else if (taps == 2) 222 return get_filter_2tap_64p(); 223 else if (taps == 1) 224 return NULL; 225 else { 226 /* should never happen, bug */ 227 BREAK_TO_DEBUGGER(); 228 return NULL; 229 } 230} 231 232static void dpp401_dscl_set_scaler_filter( 233 struct dcn401_dpp *dpp, 234 uint32_t taps, 235 enum dcn401_coef_filter_type_sel filter_type, 236 const uint16_t *filter) 237{ 238 const int tap_pairs = (taps + 1) / 2; 239 int phase; 240 int pair; 241 uint16_t odd_coef, even_coef; 242 243 REG_SET_3(SCL_COEF_RAM_TAP_SELECT, 0, 244 SCL_COEF_RAM_TAP_PAIR_IDX, 0, 245 SCL_COEF_RAM_PHASE, 0, 246 SCL_COEF_RAM_FILTER_TYPE, filter_type); 247 248 for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) { 249 for (pair = 0; pair < tap_pairs; pair++) { 250 even_coef = filter[phase * taps + 2 * pair]; 251 if ((pair * 2 + 1) < taps) 252 odd_coef = filter[phase * taps + 2 * pair + 1]; 253 else 254 odd_coef = 0; 255 256 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0, 257 /* Even tap coefficient (bits 1:0 fixed to 0) */ 258 SCL_COEF_RAM_EVEN_TAP_COEF, even_coef, 259 /* Write/read control for even coefficient */ 260 SCL_COEF_RAM_EVEN_TAP_COEF_EN, 1, 261 /* Odd tap coefficient (bits 1:0 fixed to 0) */ 262 SCL_COEF_RAM_ODD_TAP_COEF, odd_coef, 263 /* Write/read control for odd coefficient */ 264 SCL_COEF_RAM_ODD_TAP_COEF_EN, 1); 265 } 266 } 267 268} 269 270static void dpp401_dscl_set_scl_filter( 271 struct dcn401_dpp *dpp, 272 const struct scaler_data *scl_data, 273 bool chroma_coef_mode, 274 bool force_coeffs_update) 275{ 276 bool h_2tap_hardcode_coef_en = false; 277 bool v_2tap_hardcode_coef_en = false; 278 bool h_2tap_sharp_en = false; 279 bool v_2tap_sharp_en = false; 280 uint32_t h_2tap_sharp_factor = scl_data->sharpness.horz; 281 uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert; 282 bool coef_ram_current; 283 const uint16_t *filter_h = NULL; 284 const uint16_t *filter_v = NULL; 285 const uint16_t *filter_h_c = NULL; 286 const uint16_t *filter_v_c = NULL; 287 288 if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) { 289 filter_h = scl_data->dscl_prog_data.filter_h; 290 filter_v = scl_data->dscl_prog_data.filter_v; 291 if (chroma_coef_mode) { 292 filter_h_c = scl_data->dscl_prog_data.filter_h_c; 293 filter_v_c = scl_data->dscl_prog_data.filter_v_c; 294 } 295 } else { 296 filter_h = dpp401_dscl_get_filter_coeffs_64p( 297 scl_data->taps.h_taps, scl_data->ratios.horz); 298 filter_v = dpp401_dscl_get_filter_coeffs_64p( 299 scl_data->taps.v_taps, scl_data->ratios.vert); 300 if (chroma_coef_mode) { 301 filter_h_c = dpp401_dscl_get_filter_coeffs_64p( 302 scl_data->taps.h_taps_c, scl_data->ratios.horz_c); 303 filter_v_c = dpp401_dscl_get_filter_coeffs_64p( 304 scl_data->taps.v_taps_c, scl_data->ratios.vert_c); 305 } 306 } 307 308 h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3 309 && scl_data->taps.h_taps_c < 3 310 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1); 311 v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3 312 && scl_data->taps.v_taps_c < 3 313 && (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1); 314 315 h_2tap_sharp_en = h_2tap_hardcode_coef_en && h_2tap_sharp_factor != 0; 316 v_2tap_sharp_en = v_2tap_hardcode_coef_en && v_2tap_sharp_factor != 0; 317 318 REG_UPDATE_6(DSCL_2TAP_CONTROL, 319 SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en, 320 SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en, 321 SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor, 322 SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en, 323 SCL_V_2TAP_SHARP_EN, v_2tap_sharp_en, 324 SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor); 325 326 if (!v_2tap_hardcode_coef_en || !h_2tap_hardcode_coef_en) { 327 bool filter_updated = false; 328 329 filter_updated = (filter_h && (filter_h != dpp->filter_h)) 330 || (filter_v && (filter_v != dpp->filter_v)); 331 332 if (chroma_coef_mode) { 333 filter_updated = filter_updated || (filter_h_c && (filter_h_c != dpp->filter_h_c)) 334 || (filter_v_c && (filter_v_c != dpp->filter_v_c)); 335 } 336 337 if ((filter_updated) || (force_coeffs_update)) { 338 uint32_t scl_mode = REG_READ(SCL_MODE); 339 340 if (!h_2tap_hardcode_coef_en && filter_h) { 341 dpp401_dscl_set_scaler_filter( 342 dpp, scl_data->taps.h_taps, 343 SCL_COEF_LUMA_HORZ_FILTER, filter_h); 344 } 345 dpp->filter_h = filter_h; 346 if (!v_2tap_hardcode_coef_en && filter_v) { 347 dpp401_dscl_set_scaler_filter( 348 dpp, scl_data->taps.v_taps, 349 SCL_COEF_LUMA_VERT_FILTER, filter_v); 350 } 351 dpp->filter_v = filter_v; 352 if (chroma_coef_mode) { 353 if (!h_2tap_hardcode_coef_en && filter_h_c) { 354 dpp401_dscl_set_scaler_filter( 355 dpp, scl_data->taps.h_taps_c, 356 SCL_COEF_CHROMA_HORZ_FILTER, filter_h_c); 357 } 358 if (!v_2tap_hardcode_coef_en && filter_v_c) { 359 dpp401_dscl_set_scaler_filter( 360 dpp, scl_data->taps.v_taps_c, 361 SCL_COEF_CHROMA_VERT_FILTER, filter_v_c); 362 } 363 } 364 dpp->filter_h_c = filter_h_c; 365 dpp->filter_v_c = filter_v_c; 366 367 coef_ram_current = get_reg_field_value_ex( 368 scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT, 369 dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT); 370 371 /* Swap coefficient RAM and set chroma coefficient mode */ 372 REG_SET_2(SCL_MODE, scl_mode, 373 SCL_COEF_RAM_SELECT, !coef_ram_current, 374 SCL_CHROMA_COEF_MODE, chroma_coef_mode); 375 } 376 } 377} 378 379// TODO: Fix defined but not used error 380//static int dpp401_dscl_get_lb_depth_bpc(enum lb_pixel_depth depth) 381//{ 382// if (depth == LB_PIXEL_DEPTH_30BPP) 383// return 10; 384// else if (depth == LB_PIXEL_DEPTH_24BPP) 385// return 8; 386// else if (depth == LB_PIXEL_DEPTH_18BPP) 387// return 6; 388// else if (depth == LB_PIXEL_DEPTH_36BPP) 389// return 12; 390// else { 391// BREAK_TO_DEBUGGER(); 392// return -1; /* Unsupported */ 393// } 394//} 395 396// TODO: Fix defined but not used error 397//void dpp401_dscl_calc_lb_num_partitions( 398// const struct scaler_data *scl_data, 399// enum lb_memory_config lb_config, 400// int *num_part_y, 401// int *num_part_c) 402//{ 403// int lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a, 404// lb_bpc, memory_line_size_y, memory_line_size_c, memory_line_size_a; 405// 406// int line_size = scl_data->viewport.width < scl_data->recout.width ? 407// scl_data->viewport.width : scl_data->recout.width; 408// int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ? 409// scl_data->viewport_c.width : scl_data->recout.width; 410// 411// if (line_size == 0) 412// line_size = 1; 413// 414// if (line_size_c == 0) 415// line_size_c = 1; 416// 417// 418// lb_bpc = dpp401_dscl_get_lb_depth_bpc(scl_data->lb_params.depth); 419// memory_line_size_y = (line_size * lb_bpc + 71) / 72; /* +71 to ceil */ 420// memory_line_size_c = (line_size_c * lb_bpc + 71) / 72; /* +71 to ceil */ 421// memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */ 422// 423// if (lb_config == LB_MEMORY_CONFIG_1) { 424// lb_memory_size = 816; 425// lb_memory_size_c = 816; 426// lb_memory_size_a = 984; 427// } else if (lb_config == LB_MEMORY_CONFIG_2) { 428// lb_memory_size = 1088; 429// lb_memory_size_c = 1088; 430// lb_memory_size_a = 1312; 431// } else if (lb_config == LB_MEMORY_CONFIG_3) { 432// /* 420 mode: using 3rd mem from Y, Cr and Cb */ 433// lb_memory_size = 816 + 1088 + 848 + 848 + 848; 434// lb_memory_size_c = 816 + 1088; 435// lb_memory_size_a = 984 + 1312 + 456; 436// } else { 437// lb_memory_size = 816 + 1088 + 848; 438// lb_memory_size_c = 816 + 1088 + 848; 439// lb_memory_size_a = 984 + 1312 + 456; 440// } 441// *num_part_y = lb_memory_size / memory_line_size_y; 442// *num_part_c = lb_memory_size_c / memory_line_size_c; 443// num_partitions_a = lb_memory_size_a / memory_line_size_a; 444// 445// if (scl_data->lb_params.alpha_en 446// && (num_partitions_a < *num_part_y)) 447// *num_part_y = num_partitions_a; 448// 449// if (*num_part_y > 64) 450// *num_part_y = 64; 451// if (*num_part_c > 64) 452// *num_part_c = 64; 453// 454//} 455 456static bool dpp401_dscl_is_lb_conf_valid(int ceil_vratio, int num_partitions, int vtaps) 457{ 458 if (ceil_vratio > 2) 459 return vtaps <= (num_partitions - ceil_vratio + 2); 460 else 461 return vtaps <= num_partitions; 462} 463 464/*find first match configuration which meets the min required lb size*/ 465static enum lb_memory_config dpp401_dscl_find_lb_memory_config(struct dcn401_dpp *dpp, 466 const struct scaler_data *scl_data) 467{ 468 int num_part_y, num_part_c; 469 int vtaps = scl_data->taps.v_taps; 470 int vtaps_c = scl_data->taps.v_taps_c; 471 int ceil_vratio = dc_fixpt_ceil(scl_data->ratios.vert); 472 int ceil_vratio_c = dc_fixpt_ceil(scl_data->ratios.vert_c); 473 474 if (dpp->base.ctx->dc->debug.use_max_lb) { 475 if (scl_data->format == PIXEL_FORMAT_420BPP8 476 || scl_data->format == PIXEL_FORMAT_420BPP10) 477 return LB_MEMORY_CONFIG_3; 478 return LB_MEMORY_CONFIG_0; 479 } 480 481 dpp->base.caps->dscl_calc_lb_num_partitions( 482 scl_data, LB_MEMORY_CONFIG_1, &num_part_y, &num_part_c); 483 484 if (dpp401_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) 485 && dpp401_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c)) 486 return LB_MEMORY_CONFIG_1; 487 488 dpp->base.caps->dscl_calc_lb_num_partitions( 489 scl_data, LB_MEMORY_CONFIG_2, &num_part_y, &num_part_c); 490 491 if (dpp401_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) 492 && dpp401_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c)) 493 return LB_MEMORY_CONFIG_2; 494 495 if (scl_data->format == PIXEL_FORMAT_420BPP8 496 || scl_data->format == PIXEL_FORMAT_420BPP10) { 497 dpp->base.caps->dscl_calc_lb_num_partitions( 498 scl_data, LB_MEMORY_CONFIG_3, &num_part_y, &num_part_c); 499 500 if (dpp401_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) 501 && dpp401_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c)) 502 return LB_MEMORY_CONFIG_3; 503 } 504 505 dpp->base.caps->dscl_calc_lb_num_partitions( 506 scl_data, LB_MEMORY_CONFIG_0, &num_part_y, &num_part_c); 507 508 /*Ensure we can support the requested number of vtaps*/ 509 ASSERT(dpp401_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) 510 && dpp401_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c)); 511 512 return LB_MEMORY_CONFIG_0; 513} 514 515 516static void dpp401_dscl_set_manual_ratio_init( 517 struct dcn401_dpp *dpp, const struct scaler_data *data) 518{ 519 uint32_t init_frac = 0; 520 uint32_t init_int = 0; 521 if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) { 522 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0, 523 SCL_H_SCALE_RATIO, data->dscl_prog_data.ratios.h_scale_ratio); 524 525 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0, 526 SCL_V_SCALE_RATIO, data->dscl_prog_data.ratios.v_scale_ratio); 527 528 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0, 529 SCL_H_SCALE_RATIO_C, data->dscl_prog_data.ratios.h_scale_ratio_c); 530 531 REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0, 532 SCL_V_SCALE_RATIO_C, data->dscl_prog_data.ratios.v_scale_ratio_c); 533 534 REG_SET_2(SCL_HORZ_FILTER_INIT, 0, 535 SCL_H_INIT_FRAC, data->dscl_prog_data.init.h_filter_init_frac, 536 SCL_H_INIT_INT, data->dscl_prog_data.init.h_filter_init_int); 537 538 REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0, 539 SCL_H_INIT_FRAC_C, data->dscl_prog_data.init.h_filter_init_frac_c, 540 SCL_H_INIT_INT_C, data->dscl_prog_data.init.h_filter_init_int_c); 541 542 REG_SET_2(SCL_VERT_FILTER_INIT, 0, 543 SCL_V_INIT_FRAC, data->dscl_prog_data.init.v_filter_init_frac, 544 SCL_V_INIT_INT, data->dscl_prog_data.init.v_filter_init_int); 545 546 if (REG(SCL_VERT_FILTER_INIT_BOT)) { 547 REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0, 548 SCL_V_INIT_FRAC_BOT, data->dscl_prog_data.init.v_filter_init_bot_frac, 549 SCL_V_INIT_INT_BOT, data->dscl_prog_data.init.v_filter_init_bot_int); 550 } 551 552 REG_SET_2(SCL_VERT_FILTER_INIT_C, 0, 553 SCL_V_INIT_FRAC_C, data->dscl_prog_data.init.v_filter_init_frac_c, 554 SCL_V_INIT_INT_C, data->dscl_prog_data.init.v_filter_init_int_c); 555 556 if (REG(SCL_VERT_FILTER_INIT_BOT_C)) { 557 REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0, 558 SCL_V_INIT_FRAC_BOT_C, data->dscl_prog_data.init.v_filter_init_bot_frac_c, 559 SCL_V_INIT_INT_BOT_C, data->dscl_prog_data.init.v_filter_init_bot_int_c); 560 } 561 return; 562 } 563 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0, 564 SCL_H_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.horz) << 5); 565 566 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0, 567 SCL_V_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.vert) << 5); 568 569 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0, 570 SCL_H_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.horz_c) << 5); 571 572 REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0, 573 SCL_V_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.vert_c) << 5); 574 575 /* 576 * 0.24 format for fraction, first five bits zeroed 577 */ 578 init_frac = dc_fixpt_u0d19(data->inits.h) << 5; 579 init_int = dc_fixpt_floor(data->inits.h); 580 REG_SET_2(SCL_HORZ_FILTER_INIT, 0, 581 SCL_H_INIT_FRAC, init_frac, 582 SCL_H_INIT_INT, init_int); 583 584 init_frac = dc_fixpt_u0d19(data->inits.h_c) << 5; 585 init_int = dc_fixpt_floor(data->inits.h_c); 586 REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0, 587 SCL_H_INIT_FRAC_C, init_frac, 588 SCL_H_INIT_INT_C, init_int); 589 590 init_frac = dc_fixpt_u0d19(data->inits.v) << 5; 591 init_int = dc_fixpt_floor(data->inits.v); 592 REG_SET_2(SCL_VERT_FILTER_INIT, 0, 593 SCL_V_INIT_FRAC, init_frac, 594 SCL_V_INIT_INT, init_int); 595 596 if (REG(SCL_VERT_FILTER_INIT_BOT)) { 597 struct fixed31_32 bot = dc_fixpt_add(data->inits.v, data->ratios.vert); 598 599 init_frac = dc_fixpt_u0d19(bot) << 5; 600 init_int = dc_fixpt_floor(bot); 601 REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0, 602 SCL_V_INIT_FRAC_BOT, init_frac, 603 SCL_V_INIT_INT_BOT, init_int); 604 } 605 606 init_frac = dc_fixpt_u0d19(data->inits.v_c) << 5; 607 init_int = dc_fixpt_floor(data->inits.v_c); 608 REG_SET_2(SCL_VERT_FILTER_INIT_C, 0, 609 SCL_V_INIT_FRAC_C, init_frac, 610 SCL_V_INIT_INT_C, init_int); 611 612 if (REG(SCL_VERT_FILTER_INIT_BOT_C)) { 613 struct fixed31_32 bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c); 614 615 init_frac = dc_fixpt_u0d19(bot) << 5; 616 init_int = dc_fixpt_floor(bot); 617 REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0, 618 SCL_V_INIT_FRAC_BOT_C, init_frac, 619 SCL_V_INIT_INT_BOT_C, init_int); 620 } 621} 622 623/** 624 * dpp401_dscl_set_recout - Set the first pixel of RECOUT in the OTG active area 625 * 626 * @dpp: DPP data struct 627 * @recout: Rectangle information 628 * 629 * This function sets the MPC RECOUT_START and RECOUT_SIZE registers based on 630 * the values specified in the recount parameter. 631 * 632 * Note: This function only have effect if AutoCal is disabled. 633 */ 634static void dpp401_dscl_set_recout(struct dcn401_dpp *dpp, 635 const struct rect *recout) 636{ 637 REG_SET_2(RECOUT_START, 0, 638 /* First pixel of RECOUT in the active OTG area */ 639 RECOUT_START_X, recout->x, 640 /* First line of RECOUT in the active OTG area */ 641 RECOUT_START_Y, recout->y); 642 643 REG_SET_2(RECOUT_SIZE, 0, 644 /* Number of RECOUT horizontal pixels */ 645 RECOUT_WIDTH, recout->width, 646 /* Number of RECOUT vertical lines */ 647 RECOUT_HEIGHT, recout->height); 648} 649/** 650 * dpp401_dscl_program_easf_v - Program EASF_V 651 * 652 * @dpp_base: High level DPP struct 653 * @scl_data: scalaer_data info 654 * 655 * This is the primary function to program vertical EASF registers 656 * 657 */ 658static void dpp401_dscl_program_easf_v(struct dpp *dpp_base, const struct scaler_data *scl_data) 659{ 660 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); 661 662 PERF_TRACE(); 663 /* DSCL_EASF_V_MODE */ 664 REG_SET_3(DSCL_EASF_V_MODE, 0, 665 SCL_EASF_V_EN, scl_data->dscl_prog_data.easf_v_en, 666 SCL_EASF_V_2TAP_SHARP_FACTOR, scl_data->dscl_prog_data.easf_v_sharp_factor, 667 SCL_EASF_V_RINGEST_FORCE_EN, scl_data->dscl_prog_data.easf_v_ring); 668 669 if (!scl_data->dscl_prog_data.easf_v_en) { 670 PERF_TRACE(); 671 return; 672 } 673 674 /* DSCL_EASF_V_BF_CNTL */ 675 REG_SET_6(DSCL_EASF_V_BF_CNTL, 0, 676 SCL_EASF_V_BF1_EN, scl_data->dscl_prog_data.easf_v_bf1_en, 677 SCL_EASF_V_BF2_MODE, scl_data->dscl_prog_data.easf_v_bf2_mode, 678 SCL_EASF_V_BF3_MODE, scl_data->dscl_prog_data.easf_v_bf3_mode, 679 SCL_EASF_V_BF2_FLAT1_GAIN, scl_data->dscl_prog_data.easf_v_bf2_flat1_gain, 680 SCL_EASF_V_BF2_FLAT2_GAIN, scl_data->dscl_prog_data.easf_v_bf2_flat2_gain, 681 SCL_EASF_V_BF2_ROC_GAIN, scl_data->dscl_prog_data.easf_v_bf2_roc_gain); 682 /* DSCL_EASF_V_RINGEST_3TAP_CNTLn */ 683 REG_SET_2(DSCL_EASF_V_RINGEST_3TAP_CNTL1, 0, 684 SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT, scl_data->dscl_prog_data.easf_v_ringest_3tap_dntilt_uptilt, 685 SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt_max); 686 REG_SET_2(DSCL_EASF_V_RINGEST_3TAP_CNTL2, 0, 687 SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE, scl_data->dscl_prog_data.easf_v_ringest_3tap_dntilt_slope, 688 SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt1_slope); 689 REG_SET_2(DSCL_EASF_V_RINGEST_3TAP_CNTL3, 0, 690 SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt2_slope, 691 SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt2_offset); 692 /* DSCL_EASF_V_RINGEST_EVENTAP_REDUCE */ 693 REG_SET_2(DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, 0, 694 SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1, scl_data->dscl_prog_data.easf_v_ringest_eventap_reduceg1, 695 SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2, scl_data->dscl_prog_data.easf_v_ringest_eventap_reduceg2); 696 /* DSCL_EASF_V_RINGEST_EVENTAP_GAIN */ 697 REG_SET_2(DSCL_EASF_V_RINGEST_EVENTAP_GAIN, 0, 698 SCL_EASF_V_RINGEST_EVENTAP_GAIN1, scl_data->dscl_prog_data.easf_v_ringest_eventap_gain1, 699 SCL_EASF_V_RINGEST_EVENTAP_GAIN2, scl_data->dscl_prog_data.easf_v_ringest_eventap_gain2); 700 /* DSCL_EASF_V_BF_FINAL_MAX_MIN */ 701 REG_SET_4(DSCL_EASF_V_BF_FINAL_MAX_MIN, 0, 702 SCL_EASF_V_BF_MAXA, scl_data->dscl_prog_data.easf_v_bf_maxa, 703 SCL_EASF_V_BF_MAXB, scl_data->dscl_prog_data.easf_v_bf_maxb, 704 SCL_EASF_V_BF_MINA, scl_data->dscl_prog_data.easf_v_bf_mina, 705 SCL_EASF_V_BF_MINB, scl_data->dscl_prog_data.easf_v_bf_minb); 706 /* DSCL_EASF_V_BF1_PWL_SEGn */ 707 REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG0, 0, 708 SCL_EASF_V_BF1_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg0, 709 SCL_EASF_V_BF1_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg0, 710 SCL_EASF_V_BF1_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg0); 711 REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG1, 0, 712 SCL_EASF_V_BF1_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg1, 713 SCL_EASF_V_BF1_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg1, 714 SCL_EASF_V_BF1_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg1); 715 REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG2, 0, 716 SCL_EASF_V_BF1_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg2, 717 SCL_EASF_V_BF1_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg2, 718 SCL_EASF_V_BF1_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg2); 719 REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG3, 0, 720 SCL_EASF_V_BF1_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg3, 721 SCL_EASF_V_BF1_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg3, 722 SCL_EASF_V_BF1_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg3); 723 REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG4, 0, 724 SCL_EASF_V_BF1_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg4, 725 SCL_EASF_V_BF1_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg4, 726 SCL_EASF_V_BF1_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg4); 727 REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG5, 0, 728 SCL_EASF_V_BF1_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg5, 729 SCL_EASF_V_BF1_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg5, 730 SCL_EASF_V_BF1_PWL_SLOPE_SEG5, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg5); 731 REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG6, 0, 732 SCL_EASF_V_BF1_PWL_IN_SEG6, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg6, 733 SCL_EASF_V_BF1_PWL_BASE_SEG6, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg6, 734 SCL_EASF_V_BF1_PWL_SLOPE_SEG6, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg6); 735 REG_SET_2(DSCL_EASF_V_BF1_PWL_SEG7, 0, 736 SCL_EASF_V_BF1_PWL_IN_SEG7, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg7, 737 SCL_EASF_V_BF1_PWL_BASE_SEG7, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg7); 738 /* DSCL_EASF_V_BF3_PWL_SEGn */ 739 REG_SET_3(DSCL_EASF_V_BF3_PWL_SEG0, 0, 740 SCL_EASF_V_BF3_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set0, 741 SCL_EASF_V_BF3_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set0, 742 SCL_EASF_V_BF3_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set0); 743 REG_SET_3(DSCL_EASF_V_BF3_PWL_SEG1, 0, 744 SCL_EASF_V_BF3_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set1, 745 SCL_EASF_V_BF3_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set1, 746 SCL_EASF_V_BF3_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set1); 747 REG_SET_3(DSCL_EASF_V_BF3_PWL_SEG2, 0, 748 SCL_EASF_V_BF3_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set2, 749 SCL_EASF_V_BF3_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set2, 750 SCL_EASF_V_BF3_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set2); 751 REG_SET_3(DSCL_EASF_V_BF3_PWL_SEG3, 0, 752 SCL_EASF_V_BF3_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set3, 753 SCL_EASF_V_BF3_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set3, 754 SCL_EASF_V_BF3_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set3); 755 REG_SET_3(DSCL_EASF_V_BF3_PWL_SEG4, 0, 756 SCL_EASF_V_BF3_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set4, 757 SCL_EASF_V_BF3_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set4, 758 SCL_EASF_V_BF3_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set4); 759 REG_SET_2(DSCL_EASF_V_BF3_PWL_SEG5, 0, 760 SCL_EASF_V_BF3_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set5, 761 SCL_EASF_V_BF3_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set5); 762 PERF_TRACE(); 763} 764/** 765 * dpp401_dscl_program_easf_h - Program EASF_H 766 * 767 * @dpp_base: High level DPP struct 768 * @scl_data: scalaer_data info 769 * 770 * This is the primary function to program horizontal EASF registers 771 * 772 */ 773static void dpp401_dscl_program_easf_h(struct dpp *dpp_base, const struct scaler_data *scl_data) 774{ 775 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); 776 777 PERF_TRACE(); 778 /* DSCL_EASF_H_MODE */ 779 REG_SET_3(DSCL_EASF_H_MODE, 0, 780 SCL_EASF_H_EN, scl_data->dscl_prog_data.easf_h_en, 781 SCL_EASF_H_2TAP_SHARP_FACTOR, scl_data->dscl_prog_data.easf_h_sharp_factor, 782 SCL_EASF_H_RINGEST_FORCE_EN, scl_data->dscl_prog_data.easf_h_ring); 783 784 if (!scl_data->dscl_prog_data.easf_h_en) { 785 PERF_TRACE(); 786 return; 787 } 788 789 /* DSCL_EASF_H_BF_CNTL */ 790 REG_SET_6(DSCL_EASF_H_BF_CNTL, 0, 791 SCL_EASF_H_BF1_EN, scl_data->dscl_prog_data.easf_h_bf1_en, 792 SCL_EASF_H_BF2_MODE, scl_data->dscl_prog_data.easf_h_bf2_mode, 793 SCL_EASF_H_BF3_MODE, scl_data->dscl_prog_data.easf_h_bf3_mode, 794 SCL_EASF_H_BF2_FLAT1_GAIN, scl_data->dscl_prog_data.easf_h_bf2_flat1_gain, 795 SCL_EASF_H_BF2_FLAT2_GAIN, scl_data->dscl_prog_data.easf_h_bf2_flat2_gain, 796 SCL_EASF_H_BF2_ROC_GAIN, scl_data->dscl_prog_data.easf_h_bf2_roc_gain); 797 /* DSCL_EASF_H_RINGEST_EVENTAP_REDUCE */ 798 REG_SET_2(DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, 0, 799 SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1, scl_data->dscl_prog_data.easf_h_ringest_eventap_reduceg1, 800 SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2, scl_data->dscl_prog_data.easf_h_ringest_eventap_reduceg2); 801 /* DSCL_EASF_H_RINGEST_EVENTAP_GAIN */ 802 REG_SET_2(DSCL_EASF_H_RINGEST_EVENTAP_GAIN, 0, 803 SCL_EASF_H_RINGEST_EVENTAP_GAIN1, scl_data->dscl_prog_data.easf_h_ringest_eventap_gain1, 804 SCL_EASF_H_RINGEST_EVENTAP_GAIN2, scl_data->dscl_prog_data.easf_h_ringest_eventap_gain2); 805 /* DSCL_EASF_H_BF_FINAL_MAX_MIN */ 806 REG_SET_4(DSCL_EASF_H_BF_FINAL_MAX_MIN, 0, 807 SCL_EASF_H_BF_MAXA, scl_data->dscl_prog_data.easf_h_bf_maxa, 808 SCL_EASF_H_BF_MAXB, scl_data->dscl_prog_data.easf_h_bf_maxb, 809 SCL_EASF_H_BF_MINA, scl_data->dscl_prog_data.easf_h_bf_mina, 810 SCL_EASF_H_BF_MINB, scl_data->dscl_prog_data.easf_h_bf_minb); 811 /* DSCL_EASF_H_BF1_PWL_SEGn */ 812 REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG0, 0, 813 SCL_EASF_H_BF1_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg0, 814 SCL_EASF_H_BF1_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg0, 815 SCL_EASF_H_BF1_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg0); 816 REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG1, 0, 817 SCL_EASF_H_BF1_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg1, 818 SCL_EASF_H_BF1_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg1, 819 SCL_EASF_H_BF1_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg1); 820 REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG2, 0, 821 SCL_EASF_H_BF1_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg2, 822 SCL_EASF_H_BF1_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg2, 823 SCL_EASF_H_BF1_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg2); 824 REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG3, 0, 825 SCL_EASF_H_BF1_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg3, 826 SCL_EASF_H_BF1_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg3, 827 SCL_EASF_H_BF1_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg3); 828 REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG4, 0, 829 SCL_EASF_H_BF1_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg4, 830 SCL_EASF_H_BF1_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg4, 831 SCL_EASF_H_BF1_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg4); 832 REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG5, 0, 833 SCL_EASF_H_BF1_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg5, 834 SCL_EASF_H_BF1_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg5, 835 SCL_EASF_H_BF1_PWL_SLOPE_SEG5, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg5); 836 REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG6, 0, 837 SCL_EASF_H_BF1_PWL_IN_SEG6, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg6, 838 SCL_EASF_H_BF1_PWL_BASE_SEG6, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg6, 839 SCL_EASF_H_BF1_PWL_SLOPE_SEG6, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg6); 840 REG_SET_2(DSCL_EASF_H_BF1_PWL_SEG7, 0, 841 SCL_EASF_H_BF1_PWL_IN_SEG7, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg7, 842 SCL_EASF_H_BF1_PWL_BASE_SEG7, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg7); 843 /* DSCL_EASF_H_BF3_PWL_SEGn */ 844 REG_SET_3(DSCL_EASF_H_BF3_PWL_SEG0, 0, 845 SCL_EASF_H_BF3_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set0, 846 SCL_EASF_H_BF3_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set0, 847 SCL_EASF_H_BF3_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set0); 848 REG_SET_3(DSCL_EASF_H_BF3_PWL_SEG1, 0, 849 SCL_EASF_H_BF3_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set1, 850 SCL_EASF_H_BF3_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set1, 851 SCL_EASF_H_BF3_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set1); 852 REG_SET_3(DSCL_EASF_H_BF3_PWL_SEG2, 0, 853 SCL_EASF_H_BF3_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set2, 854 SCL_EASF_H_BF3_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set2, 855 SCL_EASF_H_BF3_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set2); 856 REG_SET_3(DSCL_EASF_H_BF3_PWL_SEG3, 0, 857 SCL_EASF_H_BF3_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set3, 858 SCL_EASF_H_BF3_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set3, 859 SCL_EASF_H_BF3_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set3); 860 REG_SET_3(DSCL_EASF_H_BF3_PWL_SEG4, 0, 861 SCL_EASF_H_BF3_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set4, 862 SCL_EASF_H_BF3_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set4, 863 SCL_EASF_H_BF3_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set4); 864 REG_SET_2(DSCL_EASF_H_BF3_PWL_SEG5, 0, 865 SCL_EASF_H_BF3_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set5, 866 SCL_EASF_H_BF3_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set5); 867 PERF_TRACE(); 868} 869/** 870 * dpp401_dscl_program_easf - Program EASF 871 * 872 * @dpp_base: High level DPP struct 873 * @scl_data: scalaer_data info 874 * 875 * This is the primary function to program EASF 876 * 877 */ 878static void dpp401_dscl_program_easf(struct dpp *dpp_base, const struct scaler_data *scl_data) 879{ 880 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); 881 882 PERF_TRACE(); 883 /* DSCL_SC_MODE */ 884 REG_SET_2(DSCL_SC_MODE, 0, 885 SCL_SC_MATRIX_MODE, scl_data->dscl_prog_data.easf_matrix_mode, 886 SCL_SC_LTONL_EN, scl_data->dscl_prog_data.easf_ltonl_en); 887 /* DSCL_EASF_SC_MATRIX_C0C1, DSCL_EASF_SC_MATRIX_C2C3 */ 888 REG_SET_2(DSCL_SC_MATRIX_C0C1, 0, 889 SCL_SC_MATRIX_C0, scl_data->dscl_prog_data.easf_matrix_c0, 890 SCL_SC_MATRIX_C1, scl_data->dscl_prog_data.easf_matrix_c1); 891 REG_SET_2(DSCL_SC_MATRIX_C2C3, 0, 892 SCL_SC_MATRIX_C2, scl_data->dscl_prog_data.easf_matrix_c2, 893 SCL_SC_MATRIX_C3, scl_data->dscl_prog_data.easf_matrix_c3); 894 dpp401_dscl_program_easf_v(dpp_base, scl_data); 895 dpp401_dscl_program_easf_h(dpp_base, scl_data); 896 PERF_TRACE(); 897} 898/** 899 * dpp401_dscl_disable_easf - Disable EASF when no scaling (1:1) 900 * 901 * @dpp_base: High level DPP struct 902 * @scl_data: scalaer_data info 903 * 904 * When we have 1:1 scaling, we need to disable EASF 905 * 906 */ 907static void dpp401_dscl_disable_easf(struct dpp *dpp_base, const struct scaler_data *scl_data) 908{ 909 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); 910 911 PERF_TRACE(); 912 /* DSCL_EASF_V_MODE */ 913 REG_UPDATE(DSCL_EASF_V_MODE, 914 SCL_EASF_V_EN, scl_data->dscl_prog_data.easf_v_en); 915 /* DSCL_EASF_H_MODE */ 916 REG_UPDATE(DSCL_EASF_H_MODE, 917 SCL_EASF_H_EN, scl_data->dscl_prog_data.easf_h_en); 918 PERF_TRACE(); 919} 920static void dpp401_dscl_set_isharp_filter( 921 struct dcn401_dpp *dpp, const uint32_t *filter) 922{ 923 int level; 924 uint32_t filter_data; 925 if (filter == NULL) 926 return; 927 928 REG_UPDATE(ISHARP_DELTA_CTRL, 929 ISHARP_DELTA_LUT_HOST_SELECT, 0); 930 /* LUT data write is auto-indexed. Write index once */ 931 REG_SET(ISHARP_DELTA_INDEX, 0, 932 ISHARP_DELTA_INDEX, 0); 933 for (level = 0; level < NUM_LEVELS; level++) { 934 filter_data = filter[level]; 935 REG_SET(ISHARP_DELTA_DATA, 0, 936 ISHARP_DELTA_DATA, filter_data); 937 } 938} // dpp401_dscl_set_isharp_filter 939/** 940 * dpp401_dscl_program_isharp - Program isharp 941 * 942 * @dpp_base: High level DPP struct 943 * @scl_data: scalaer_data info 944 * @program_isharp_1dlut: flag to program isharp 1D LUT 945 * @bs_coeffs_updated: Blur and Scale Coefficients update flag 946 * 947 * This is the primary function to program isharp 948 * 949 */ 950static void dpp401_dscl_program_isharp(struct dpp *dpp_base, 951 const struct scaler_data *scl_data, 952 bool program_isharp_1dlut, 953 bool *bs_coeffs_updated) 954{ 955 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); 956 *bs_coeffs_updated = false; 957 958 PERF_TRACE(); 959 /* ISHARP_MODE */ 960 REG_SET_6(ISHARP_MODE, 0, 961 ISHARP_EN, scl_data->dscl_prog_data.isharp_en, 962 ISHARP_NOISEDET_EN, scl_data->dscl_prog_data.isharp_noise_det.enable, 963 ISHARP_NOISEDET_MODE, scl_data->dscl_prog_data.isharp_noise_det.mode, 964 ISHARP_LBA_MODE, scl_data->dscl_prog_data.isharp_lba.mode, 965 ISHARP_FMT_MODE, scl_data->dscl_prog_data.isharp_fmt.mode, 966 ISHARP_FMT_NORM, scl_data->dscl_prog_data.isharp_fmt.norm); 967 968 /* Skip remaining register programming if ISHARP is disabled */ 969 if (!scl_data->dscl_prog_data.isharp_en) { 970 PERF_TRACE(); 971 return; 972 } 973 974 /* ISHARP_NOISEDET_THRESHOLD */ 975 REG_SET_2(ISHARP_NOISEDET_THRESHOLD, 0, 976 ISHARP_NOISEDET_UTHRE, scl_data->dscl_prog_data.isharp_noise_det.uthreshold, 977 ISHARP_NOISEDET_DTHRE, scl_data->dscl_prog_data.isharp_noise_det.dthreshold); 978 979 /* ISHARP_NOISE_GAIN_PWL */ 980 REG_SET_3(ISHARP_NOISE_GAIN_PWL, 0, 981 ISHARP_NOISEDET_PWL_START_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_start_in, 982 ISHARP_NOISEDET_PWL_END_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_end_in, 983 ISHARP_NOISEDET_PWL_SLOPE, scl_data->dscl_prog_data.isharp_noise_det.pwl_slope); 984 985 /* ISHARP_LBA: IN_SEG, BASE_SEG, SLOPE_SEG */ 986 REG_SET_3(ISHARP_LBA_PWL_SEG0, 0, 987 ISHARP_LBA_PWL_IN_SEG0, scl_data->dscl_prog_data.isharp_lba.in_seg[0], 988 ISHARP_LBA_PWL_BASE_SEG0, scl_data->dscl_prog_data.isharp_lba.base_seg[0], 989 ISHARP_LBA_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.isharp_lba.slope_seg[0]); 990 REG_SET_3(ISHARP_LBA_PWL_SEG1, 0, 991 ISHARP_LBA_PWL_IN_SEG1, scl_data->dscl_prog_data.isharp_lba.in_seg[1], 992 ISHARP_LBA_PWL_BASE_SEG1, scl_data->dscl_prog_data.isharp_lba.base_seg[1], 993 ISHARP_LBA_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.isharp_lba.slope_seg[1]); 994 REG_SET_3(ISHARP_LBA_PWL_SEG2, 0, 995 ISHARP_LBA_PWL_IN_SEG2, scl_data->dscl_prog_data.isharp_lba.in_seg[2], 996 ISHARP_LBA_PWL_BASE_SEG2, scl_data->dscl_prog_data.isharp_lba.base_seg[2], 997 ISHARP_LBA_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.isharp_lba.slope_seg[2]); 998 REG_SET_3(ISHARP_LBA_PWL_SEG3, 0, 999 ISHARP_LBA_PWL_IN_SEG3, scl_data->dscl_prog_data.isharp_lba.in_seg[3], 1000 ISHARP_LBA_PWL_BASE_SEG3, scl_data->dscl_prog_data.isharp_lba.base_seg[3], 1001 ISHARP_LBA_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.isharp_lba.slope_seg[3]); 1002 REG_SET_3(ISHARP_LBA_PWL_SEG4, 0, 1003 ISHARP_LBA_PWL_IN_SEG4, scl_data->dscl_prog_data.isharp_lba.in_seg[4], 1004 ISHARP_LBA_PWL_BASE_SEG4, scl_data->dscl_prog_data.isharp_lba.base_seg[4], 1005 ISHARP_LBA_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.isharp_lba.slope_seg[4]); 1006 REG_SET_2(ISHARP_LBA_PWL_SEG5, 0, 1007 ISHARP_LBA_PWL_IN_SEG5, scl_data->dscl_prog_data.isharp_lba.in_seg[5], 1008 ISHARP_LBA_PWL_BASE_SEG5, scl_data->dscl_prog_data.isharp_lba.base_seg[5]); 1009 1010 /* ISHARP_DELTA_LUT */ 1011 if (!program_isharp_1dlut) 1012 dpp401_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta); 1013 1014 /* ISHARP_NLDELTA_SOFT_CLIP */ 1015 REG_SET_6(ISHARP_NLDELTA_SOFT_CLIP, 0, 1016 ISHARP_NLDELTA_SCLIP_EN_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_p, 1017 ISHARP_NLDELTA_SCLIP_PIVOT_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_p, 1018 ISHARP_NLDELTA_SCLIP_SLOPE_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_p, 1019 ISHARP_NLDELTA_SCLIP_EN_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_n, 1020 ISHARP_NLDELTA_SCLIP_PIVOT_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_n, 1021 ISHARP_NLDELTA_SCLIP_SLOPE_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_n); 1022 1023 /* Blur and Scale Coefficients - SCL_COEF_RAM_TAP_SELECT */ 1024 if (scl_data->dscl_prog_data.isharp_en) { 1025 if (scl_data->dscl_prog_data.filter_blur_scale_v) { 1026 dpp401_dscl_set_scaler_filter( 1027 dpp, scl_data->taps.v_taps, 1028 SCL_COEF_VERTICAL_BLUR_SCALE, 1029 scl_data->dscl_prog_data.filter_blur_scale_v); 1030 *bs_coeffs_updated = true; 1031 } 1032 if (scl_data->dscl_prog_data.filter_blur_scale_h) { 1033 dpp401_dscl_set_scaler_filter( 1034 dpp, scl_data->taps.h_taps, 1035 SCL_COEF_HORIZONTAL_BLUR_SCALE, 1036 scl_data->dscl_prog_data.filter_blur_scale_h); 1037 *bs_coeffs_updated = true; 1038 } 1039 } 1040 PERF_TRACE(); 1041} // dpp401_dscl_program_isharp 1042/** 1043 * dpp401_dscl_set_scaler_manual_scale - Manually program scaler and line buffer 1044 * 1045 * @dpp_base: High level DPP struct 1046 * @scl_data: scalaer_data info 1047 * 1048 * This is the primary function to program scaler and line buffer in manual 1049 * scaling mode. To execute the required operations for manual scale, we need 1050 * to disable AutoCal first. 1051 */ 1052void dpp401_dscl_set_scaler_manual_scale(struct dpp *dpp_base, 1053 const struct scaler_data *scl_data) 1054{ 1055 enum lb_memory_config lb_config; 1056 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); 1057 const struct rect *rect = &scl_data->recout; 1058 uint32_t mpc_width = scl_data->h_active; 1059 uint32_t mpc_height = scl_data->v_active; 1060 uint32_t v_num_taps = scl_data->taps.v_taps - 1; 1061 uint32_t v_num_taps_c = scl_data->taps.v_taps_c - 1; 1062 uint32_t h_num_taps = scl_data->taps.h_taps - 1; 1063 uint32_t h_num_taps_c = scl_data->taps.h_taps_c - 1; 1064 enum dcn401_dscl_mode_sel dscl_mode = dpp401_dscl_get_dscl_mode( 1065 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale); 1066 bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN 1067 && scl_data->format <= PIXEL_FORMAT_VIDEO_END; 1068 bool program_isharp_1dlut = false; 1069 bool bs_coeffs_updated = false; 1070 1071 1072 if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0) 1073 return; 1074 1075 PERF_TRACE(); 1076 1077 /* If only sharpness has changed, then only update 1dlut, then return */ 1078 if (scl_data->dscl_prog_data.isharp_en && 1079 (dpp->scl_data.dscl_prog_data.sharpness_level 1080 != scl_data->dscl_prog_data.sharpness_level)) { 1081 /* ISHARP_DELTA_LUT */ 1082 dpp401_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta); 1083 dpp->scl_data.dscl_prog_data.sharpness_level = scl_data->dscl_prog_data.sharpness_level; 1084 memcpy(dpp->scl_data.dscl_prog_data.isharp_delta, scl_data->dscl_prog_data.isharp_delta, 1085 sizeof(uint32_t) * ISHARP_LUT_TABLE_SIZE); 1086 1087 if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0) 1088 return; 1089 program_isharp_1dlut = true; 1090 } 1091 1092 dpp->scl_data = *scl_data; 1093 1094 if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) { 1095 dscl_mode = (enum dcn401_dscl_mode_sel) scl_data->dscl_prog_data.dscl_mode; 1096 rect = (struct rect *)&scl_data->dscl_prog_data.recout; 1097 mpc_width = scl_data->dscl_prog_data.mpc_size.width; 1098 mpc_height = scl_data->dscl_prog_data.mpc_size.height; 1099 v_num_taps = scl_data->dscl_prog_data.taps.v_taps; 1100 v_num_taps_c = scl_data->dscl_prog_data.taps.v_taps_c; 1101 h_num_taps = scl_data->dscl_prog_data.taps.h_taps; 1102 h_num_taps_c = scl_data->dscl_prog_data.taps.h_taps_c; 1103 } 1104 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) { 1105 if (dscl_mode != DCN401_DSCL_MODE_DSCL_BYPASS) 1106 dpp401_power_on_dscl(dpp_base, true); 1107 } 1108 1109 /* Autocal off */ 1110 REG_SET_3(DSCL_AUTOCAL, 0, 1111 AUTOCAL_MODE, AUTOCAL_MODE_OFF, 1112 AUTOCAL_NUM_PIPE, 0, 1113 AUTOCAL_PIPE_ID, 0); 1114 1115 /*clean scaler boundary mode when Autocal off*/ 1116 REG_SET(DSCL_CONTROL, 0, 1117 SCL_BOUNDARY_MODE, 0); 1118 1119 /* Recout */ 1120 dpp401_dscl_set_recout(dpp, rect); 1121 1122 /* MPC Size */ 1123 REG_SET_2(MPC_SIZE, 0, 1124 /* Number of horizontal pixels of MPC */ 1125 MPC_WIDTH, mpc_width, 1126 /* Number of vertical lines of MPC */ 1127 MPC_HEIGHT, mpc_height); 1128 1129 /* SCL mode */ 1130 REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode); 1131 1132 if (dscl_mode == DCN401_DSCL_MODE_DSCL_BYPASS) { 1133 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) 1134 dpp401_power_on_dscl(dpp_base, false); 1135 return; 1136 } 1137 1138 /* LB */ 1139 lb_config = dpp401_dscl_find_lb_memory_config(dpp, scl_data); 1140 dpp401_dscl_set_lb(dpp, &scl_data->lb_params, lb_config); 1141 1142 if (dscl_mode == DCN401_DSCL_MODE_SCALING_444_BYPASS) { 1143 if (dpp->base.ctx->dc->config.prefer_easf) 1144 dpp401_dscl_disable_easf(dpp_base, scl_data); 1145 dpp401_dscl_program_isharp(dpp_base, scl_data, program_isharp_1dlut, &bs_coeffs_updated); 1146 return; 1147 } 1148 1149 /* Black offsets */ 1150 if (REG(SCL_BLACK_OFFSET)) { 1151 if (ycbcr) 1152 REG_SET_2(SCL_BLACK_OFFSET, 0, 1153 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y, 1154 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR); 1155 else 1156 1157 REG_SET_2(SCL_BLACK_OFFSET, 0, 1158 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y, 1159 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y); 1160 } 1161 1162 /* Manually calculate scale ratio and init values */ 1163 dpp401_dscl_set_manual_ratio_init(dpp, scl_data); 1164 1165 /* HTaps/VTaps */ 1166 REG_SET_4(SCL_TAP_CONTROL, 0, 1167 SCL_V_NUM_TAPS, v_num_taps, 1168 SCL_H_NUM_TAPS, h_num_taps, 1169 SCL_V_NUM_TAPS_C, v_num_taps_c, 1170 SCL_H_NUM_TAPS_C, h_num_taps_c); 1171 1172 /* ISharp configuration 1173 * - B&S coeffs are written to same coeff RAM as WB scaler coeffs 1174 * - coeff RAM toggle is in EASF programming 1175 * - if we are only programming B&S coeffs, then need to reprogram 1176 * WB scaler coeffs and toggle coeff RAM together 1177 */ 1178 //if (dpp->base.ctx->dc->config.prefer_easf) 1179 dpp401_dscl_program_isharp(dpp_base, scl_data, program_isharp_1dlut, &bs_coeffs_updated); 1180 1181 dpp401_dscl_set_scl_filter(dpp, scl_data, ycbcr, bs_coeffs_updated); 1182 /* Edge adaptive scaler function configuration */ 1183 if (dpp->base.ctx->dc->config.prefer_easf) 1184 dpp401_dscl_program_easf(dpp_base, scl_data); 1185 PERF_TRACE(); 1186}
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