dcn401_dpp_cm.c

  1/*
  2 * Copyright 2016 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#include "dm_services.h"
 27
 28#include "core_types.h"
 29
 30#include "reg_helper.h"
 31#include "dcn401/dcn401_dpp.h"
 32#include "basics/conversion.h"
 33#include "dcn10/dcn10_cm_common.h"
 34
 35#define NUM_PHASES    64
 36#define HORZ_MAX_TAPS 8
 37#define VERT_MAX_TAPS 8
 38
 39#define BLACK_OFFSET_RGB_Y 0x0
 40#define BLACK_OFFSET_CBCR  0x8000
 41
 42#define REG(reg)\
 43	dpp->tf_regs->reg
 44
 45#define CTX \
 46	dpp->base.ctx
 47
 48#undef FN
 49#define FN(reg_name, field_name) \
 50	dpp->tf_shift->field_name, dpp->tf_mask->field_name
 51
 52#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
 53
 54
 55enum dcn401_coef_filter_type_sel {
 56	SCL_COEF_LUMA_VERT_FILTER = 0,
 57	SCL_COEF_LUMA_HORZ_FILTER = 1,
 58	SCL_COEF_CHROMA_VERT_FILTER = 2,
 59	SCL_COEF_CHROMA_HORZ_FILTER = 3,
 60	SCL_COEF_SC_VERT_FILTER = 4,
 61	SCL_COEF_SC_HORZ_FILTER = 5
 62};
 63
 64enum dscl_autocal_mode {
 65	AUTOCAL_MODE_OFF = 0,
 66
 67	/* Autocal calculate the scaling ratio and initial phase and the
 68	 * DSCL_MODE_SEL must be set to 1
 69	 */
 70	AUTOCAL_MODE_AUTOSCALE = 1,
 71	/* Autocal perform auto centering without replication and the
 72	 * DSCL_MODE_SEL must be set to 0
 73	 */
 74	AUTOCAL_MODE_AUTOCENTER = 2,
 75	/* Autocal perform auto centering and auto replication and the
 76	 * DSCL_MODE_SEL must be set to 0
 77	 */
 78	AUTOCAL_MODE_AUTOREPLICATE = 3
 79};
 80
 81enum dscl_mode_sel {
 82	DSCL_MODE_SCALING_444_BYPASS = 0,
 83	DSCL_MODE_SCALING_444_RGB_ENABLE = 1,
 84	DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
 85	DSCL_MODE_SCALING_YCBCR_ENABLE = 3,
 86	DSCL_MODE_LUMA_SCALING_BYPASS = 4,
 87	DSCL_MODE_CHROMA_SCALING_BYPASS = 5,
 88	DSCL_MODE_DSCL_BYPASS = 6
 89};
 90
 91void dpp401_set_cursor_attributes(
 92	struct dpp *dpp_base,
 93	struct dc_cursor_attributes *cursor_attributes)
 94{
 95	struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);
 96	enum dc_cursor_color_format color_format = cursor_attributes->color_format;
 97	int cur_rom_en = 0;
 98
 99	if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
100		color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {
101		if (cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) {
102			cur_rom_en = 1;
103		}
104	}
105
106	if (!dpp_base->cursor_offload)
107		REG_UPDATE_3(CURSOR0_CONTROL,
108			CUR0_MODE, color_format,
109			CUR0_EXPANSION_MODE, 0,
110			CUR0_ROM_EN, cur_rom_en);
111
112	if (color_format == CURSOR_MODE_MONO) {
113		/* todo: clarify what to program these to */
114
115		if (!dpp_base->cursor_offload) {
116			REG_UPDATE(CURSOR0_COLOR0,
117				CUR0_COLOR0, 0x00000000);
118			REG_UPDATE(CURSOR0_COLOR1,
119				CUR0_COLOR1, 0xFFFFFFFF);
120		}
121	}
122
123	dpp_base->att.cur0_ctl.bits.expansion_mode = 0;
124	dpp_base->att.cur0_ctl.bits.cur0_rom_en = cur_rom_en;
125	dpp_base->att.cur0_ctl.bits.mode = color_format;
126}
127
128void dpp401_set_cursor_position(
129	struct dpp *dpp_base,
130	const struct dc_cursor_position *pos,
131	const struct dc_cursor_mi_param *param,
132	uint32_t width,
133	uint32_t height)
134{
135	struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);
136	uint32_t cur_en = pos->enable ? 1 : 0;
137
138	if (dpp_base->pos.cur0_ctl.bits.cur0_enable != cur_en) {
139		if (!dpp_base->cursor_offload)
140			REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, cur_en);
141	}
142
143	dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en;
144	dpp_base->att.cur0_ctl.bits.cur0_enable = cur_en;
145}
146
147void dpp401_set_optional_cursor_attributes(
148	struct dpp *dpp_base,
149	struct dpp_cursor_attributes *attr)
150{
151	struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);
152
153	if (attr) {
154		if (!dpp_base->cursor_offload) {
155			REG_UPDATE(CURSOR0_FP_SCALE_BIAS_G_Y, CUR0_FP_BIAS_G_Y, attr->bias);
156			REG_UPDATE(CURSOR0_FP_SCALE_BIAS_G_Y, CUR0_FP_SCALE_G_Y, attr->scale);
157			REG_UPDATE(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CUR0_FP_BIAS_RB_CRCB, attr->bias);
158			REG_UPDATE(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CUR0_FP_SCALE_RB_CRCB, attr->scale);
159		}
160
161		dpp_base->att.fp_scale_bias_g_y.bits.fp_bias_g_y = attr->bias;
162		dpp_base->att.fp_scale_bias_g_y.bits.fp_scale_g_y = attr->scale;
163		dpp_base->att.fp_scale_bias_rb_crcb.bits.fp_bias_rb_crcb = attr->bias;
164		dpp_base->att.fp_scale_bias_rb_crcb.bits.fp_scale_rb_crcb = attr->scale;
165	}
166}
167
168/* Program Cursor matrix block in DPP CM */
169static void dpp401_program_cursor_csc(
170	struct dpp *dpp_base,
171	enum dc_color_space color_space,
172	const struct dpp_input_csc_matrix *tbl_entry)
173{
174	struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);
175	uint32_t mode_select = 0;
176	struct color_matrices_reg cur_matrix_regs;
177	unsigned int i;
178	const uint16_t *regval = NULL;
179	int arr_size = sizeof(dpp_input_csc_matrix) / sizeof(struct dpp_input_csc_matrix);
180
181	if (color_space < COLOR_SPACE_YCBCR601) {
182		REG_SET(CUR0_MATRIX_MODE, 0, CUR0_MATRIX_MODE, CUR_MATRIX_BYPASS);
183		return;
184	}
185
186	/* If adjustments not provided use hardcoded table for color space conversion */
187	if (tbl_entry == NULL) {
188
189		for (i = 0; i < arr_size; i++)
190			if (dpp_input_csc_matrix[i].color_space == color_space) {
191				regval = dpp_input_csc_matrix[i].regval;
192				break;
193			}
194
195		if (regval == NULL) {
196			BREAK_TO_DEBUGGER();
197			REG_SET(CUR0_MATRIX_MODE, 0, CUR0_MATRIX_MODE, CUR_MATRIX_BYPASS);
198			return;
199		}
200	} else {
201		regval = tbl_entry->regval;
202	}
203
204	REG_GET(CUR0_MATRIX_MODE, CUR0_MATRIX_MODE_CURRENT, &mode_select);
205
206	//If current set in use not set A, then use set A, otherwise use set B
207	if (mode_select != CUR_MATRIX_SET_A)
208		mode_select = CUR_MATRIX_SET_A;
209	else
210		mode_select = CUR_MATRIX_SET_B;
211
212	cur_matrix_regs.shifts.csc_c11 = dpp->tf_shift->CUR0_MATRIX_C11_A;
213	cur_matrix_regs.masks.csc_c11 = dpp->tf_mask->CUR0_MATRIX_C11_A;
214	cur_matrix_regs.shifts.csc_c12 = dpp->tf_shift->CUR0_MATRIX_C12_A;
215	cur_matrix_regs.masks.csc_c12 = dpp->tf_mask->CUR0_MATRIX_C12_A;
216
217	if (mode_select == CUR_MATRIX_SET_A) {
218		cur_matrix_regs.csc_c11_c12 = REG(CUR0_MATRIX_C11_C12_A);
219		cur_matrix_regs.csc_c33_c34 = REG(CUR0_MATRIX_C33_C34_A);
220	} else {
221		cur_matrix_regs.csc_c11_c12 = REG(CUR0_MATRIX_C11_C12_B);
222		cur_matrix_regs.csc_c33_c34 = REG(CUR0_MATRIX_C33_C34_B);
223	}
224
225	cm_helper_program_color_matrices(
226		dpp->base.ctx,
227		regval,
228		&cur_matrix_regs);
229
230	//select coefficient set to use
231	REG_SET(CUR0_MATRIX_MODE, 0, CUR0_MATRIX_MODE, mode_select);
232}
233
234/* Program Cursor matrix block in DPP CM */
235void dpp401_set_cursor_matrix(
236	struct dpp *dpp_base,
237	enum dc_color_space color_space,
238	struct dc_csc_transform cursor_csc_color_matrix)
239{
240	//Since we don't have cursor matrix information, force bypass mode by passing in unknown color space
241	dpp401_program_cursor_csc(dpp_base, COLOR_SPACE_UNKNOWN, NULL);
242}