dcn201_dpp.c

  1/*
  2 * Copyright 2016 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#include "dm_services.h"
 27
 28#include "core_types.h"
 29
 30#include "reg_helper.h"
 31#include "dcn201/dcn201_dpp.h"
 32#include "basics/conversion.h"
 33
 34#define REG(reg)\
 35	dpp->tf_regs->reg
 36
 37#define CTX \
 38	dpp->base.ctx
 39
 40#undef FN
 41#define FN(reg_name, field_name) \
 42	dpp->tf_shift->field_name, dpp->tf_mask->field_name
 43
 44static void dpp201_cnv_setup(
 45		struct dpp *dpp_base,
 46		enum surface_pixel_format format,
 47		enum expansion_mode mode,
 48		struct dc_csc_transform input_csc_color_matrix,
 49		enum dc_color_space input_color_space,
 50		struct cnv_alpha_2bit_lut *alpha_2bit_lut)
 51{
 52	struct dcn201_dpp *dpp = TO_DCN201_DPP(dpp_base);
 53	uint32_t pixel_format = 0;
 54	uint32_t alpha_en = 1;
 55	enum dc_color_space color_space = COLOR_SPACE_SRGB;
 56	enum dcn10_input_csc_select select = INPUT_CSC_SELECT_BYPASS;
 57	bool force_disable_cursor = false;
 58	uint32_t is_2bit = 0;
 59
 60	REG_SET_2(FORMAT_CONTROL, 0,
 61		CNVC_BYPASS, 0,
 62		FORMAT_EXPANSION_MODE, mode);
 63
 64	/*
 65	 * hardcode default
 66	 * FORMAT_CONTROL. FORMAT_CNV16				default 0: U0.16/S.1.15;	1: U1.15/ S.1.14
 67	 * FORMAT_CONTROL. CNVC_BYPASS_MSB_ALIGN		default 0: disabled			1: enabled
 68	 * FORMAT_CONTROL. CLAMP_POSITIVE			default 0: disabled			1: enabled
 69	 * FORMAT_CONTROL. CLAMP_POSITIVE_C			default 0: disabled			1: enabled
 70	 */
 71	REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);
 72	REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);
 73	REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);
 74	REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);
 75
 76	switch (format) {
 77	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
 78		pixel_format = 1;
 79		break;
 80	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 81		pixel_format = 3;
 82		alpha_en = 0;
 83		break;
 84	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 85	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 86		pixel_format = 8;
 87		break;
 88	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 89	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 90		pixel_format = 10;
 91		is_2bit = 1;
 92		break;
 93	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 94		force_disable_cursor = false;
 95		pixel_format = 65;
 96		color_space = COLOR_SPACE_YCBCR709;
 97		select = INPUT_CSC_SELECT_ICSC;
 98		break;
 99	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
100		force_disable_cursor = true;
101		pixel_format = 64;
102		color_space = COLOR_SPACE_YCBCR709;
103		select = INPUT_CSC_SELECT_ICSC;
104		break;
105	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
106		force_disable_cursor = true;
107		pixel_format = 67;
108		color_space = COLOR_SPACE_YCBCR709;
109		select = INPUT_CSC_SELECT_ICSC;
110		break;
111	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
112		force_disable_cursor = true;
113		pixel_format = 66;
114		color_space = COLOR_SPACE_YCBCR709;
115		select = INPUT_CSC_SELECT_ICSC;
116		break;
117	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
118		pixel_format = 22;
119		break;
120	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
121		pixel_format = 24;
122		break;
123	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
124		pixel_format = 25;
125		break;
126	case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
127		pixel_format = 12;
128		color_space = COLOR_SPACE_YCBCR709;
129		select = INPUT_CSC_SELECT_ICSC;
130		break;
131	case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
132		pixel_format = 112;
133		alpha_en = 0;
134		break;
135	case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
136		pixel_format = 113;
137		alpha_en = 0;
138		break;
139	case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
140		pixel_format = 114;
141		color_space = COLOR_SPACE_YCBCR709;
142		select = INPUT_CSC_SELECT_ICSC;
143		is_2bit = 1;
144		break;
145	case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102:
146		pixel_format = 115;
147		color_space = COLOR_SPACE_YCBCR709;
148		select = INPUT_CSC_SELECT_ICSC;
149		is_2bit = 1;
150		break;
151	case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
152		pixel_format = 118;
153		alpha_en = 0;
154		break;
155	case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
156		pixel_format = 119;
157		alpha_en = 0;
158		break;
159	default:
160		break;
161	}
162
163	/* Set default color space based on format if none is given. */
164	color_space = input_color_space ? input_color_space : color_space;
165
166	if (is_2bit == 1 && alpha_2bit_lut != NULL) {
167		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
168		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
169		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2);
170		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3);
171	}
172
173	REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
174			CNVC_SURFACE_PIXEL_FORMAT, pixel_format);
175	REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
176
177	dpp1_program_input_csc(dpp_base, color_space, select, NULL);
178
179	if (force_disable_cursor) {
180		REG_UPDATE(CURSOR_CONTROL,
181				CURSOR_ENABLE, 0);
182		REG_UPDATE(CURSOR0_CONTROL,
183				CUR0_ENABLE, 0);
184	}
185	dpp2_power_on_obuf(dpp_base, true);
186}
187
188#define IDENTITY_RATIO(ratio) (dc_fixpt_u3d19(ratio) == (1 << 19))
189
190static bool dpp201_get_optimal_number_of_taps(
191		struct dpp *dpp,
192		struct scaler_data *scl_data,
193		const struct scaling_taps *in_taps)
194{
195	/* Some ASICs does not support  FP16 scaling, so we reject modes require this*/
196	if (scl_data->viewport.width  != scl_data->h_active &&
197		scl_data->viewport.height != scl_data->v_active &&
198		dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
199		scl_data->format == PIXEL_FORMAT_FP16)
200		return false;
201
202	if (scl_data->viewport.width > scl_data->h_active &&
203		dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
204		scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
205		return false;
206
207	/* No support for programming ratio of 8, drop to 7.99999.. */
208	if (scl_data->ratios.horz.value == (8ll << 32))
209		scl_data->ratios.horz.value--;
210	if (scl_data->ratios.vert.value == (8ll << 32))
211		scl_data->ratios.vert.value--;
212	if (scl_data->ratios.horz_c.value == (8ll << 32))
213		scl_data->ratios.horz_c.value--;
214	if (scl_data->ratios.vert_c.value == (8ll << 32))
215		scl_data->ratios.vert_c.value--;
216
217	/* Set default taps if none are provided */
218	if (in_taps->h_taps == 0) {
219		if (dc_fixpt_ceil(scl_data->ratios.horz) > 4)
220			scl_data->taps.h_taps = 8;
221		else
222			scl_data->taps.h_taps = 4;
223	} else
224		scl_data->taps.h_taps = in_taps->h_taps;
225
226	if (in_taps->v_taps == 0) {
227		if (dc_fixpt_ceil(scl_data->ratios.vert) > 4)
228			scl_data->taps.v_taps = 8;
229		else
230			scl_data->taps.v_taps = 4;
231	} else
232		scl_data->taps.v_taps = in_taps->v_taps;
233	if (in_taps->v_taps_c == 0) {
234		if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 4)
235			scl_data->taps.v_taps_c = 4;
236		else
237			scl_data->taps.v_taps_c = 2;
238	} else
239		scl_data->taps.v_taps_c = in_taps->v_taps_c;
240	if (in_taps->h_taps_c == 0) {
241		if (dc_fixpt_ceil(scl_data->ratios.horz_c) > 4)
242			scl_data->taps.h_taps_c = 4;
243		else
244			scl_data->taps.h_taps_c = 2;
245	} else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
246		/* Only 1 and even h_taps_c are supported by hw */
247		scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
248	else
249		scl_data->taps.h_taps_c = in_taps->h_taps_c;
250
251	if (!dpp->ctx->dc->debug.always_scale) {
252		if (IDENTITY_RATIO(scl_data->ratios.horz))
253			scl_data->taps.h_taps = 1;
254		if (IDENTITY_RATIO(scl_data->ratios.vert))
255			scl_data->taps.v_taps = 1;
256		if (IDENTITY_RATIO(scl_data->ratios.horz_c))
257			scl_data->taps.h_taps_c = 1;
258		if (IDENTITY_RATIO(scl_data->ratios.vert_c))
259			scl_data->taps.v_taps_c = 1;
260	}
261
262	return true;
263}
264
265static struct dpp_funcs dcn201_dpp_funcs = {
266	.dpp_read_state = dpp20_read_state,
267	.dpp_reset = dpp_reset,
268	.dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
269	.dpp_get_optimal_number_of_taps = dpp201_get_optimal_number_of_taps,
270	.dpp_set_gamut_remap = dpp1_cm_set_gamut_remap,
271	.dpp_set_csc_adjustment = NULL,
272	.dpp_set_csc_default = NULL,
273	.dpp_program_regamma_pwl = oppn20_dummy_program_regamma_pwl,
274	.dpp_set_degamma = dpp2_set_degamma,
275	.dpp_program_input_lut = dpp2_dummy_program_input_lut,
276	.dpp_full_bypass = dpp1_full_bypass,
277	.dpp_setup = dpp201_cnv_setup,
278	.dpp_program_degamma_pwl = dpp2_set_degamma_pwl,
279	.dpp_program_blnd_lut = dpp20_program_blnd_lut,
280	.dpp_program_shaper_lut = dpp20_program_shaper,
281	.dpp_program_3dlut = dpp20_program_3dlut,
282	.dpp_program_bias_and_scale = NULL,
283	.dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer,
284	.set_cursor_attributes = dpp2_set_cursor_attributes,
285	.set_cursor_position = dpp1_set_cursor_position,
286	.set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
287	.dpp_dppclk_control = dpp1_dppclk_control,
288	.dpp_set_hdr_multiplier = dpp2_set_hdr_multiplier,
289	.dpp_get_gamut_remap = dpp2_cm_get_gamut_remap,
290};
291
292static struct dpp_caps dcn201_dpp_cap = {
293	.dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT,
294	.dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions,
295};
296
297bool dpp201_construct(
298	struct dcn201_dpp *dpp,
299	struct dc_context *ctx,
300	uint32_t inst,
301	const struct dcn201_dpp_registers *tf_regs,
302	const struct dcn201_dpp_shift *tf_shift,
303	const struct dcn201_dpp_mask *tf_mask)
304{
305	dpp->base.ctx = ctx;
306
307	dpp->base.inst = inst;
308	dpp->base.funcs = &dcn201_dpp_funcs;
309	dpp->base.caps = &dcn201_dpp_cap;
310
311	dpp->tf_regs = tf_regs;
312	dpp->tf_shift = tf_shift;
313	dpp->tf_mask = tf_mask;
314
315	dpp->lb_pixel_depth_supported =
316		LB_PIXEL_DEPTH_18BPP |
317		LB_PIXEL_DEPTH_24BPP |
318		LB_PIXEL_DEPTH_30BPP;
319
320	dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
321	dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
322
323	return true;
324}