dcn10_dpp.c

  1/*
  2 * Copyright 2016 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#include "dm_services.h"
 27
 28#include "core_types.h"
 29
 30#include "reg_helper.h"
 31#include "dcn10/dcn10_dpp.h"
 32#include "basics/conversion.h"
 33
 34#define NUM_PHASES    64
 35#define HORZ_MAX_TAPS 8
 36#define VERT_MAX_TAPS 8
 37
 38#define BLACK_OFFSET_RGB_Y 0x0
 39#define BLACK_OFFSET_CBCR  0x8000
 40
 41#define REG(reg)\
 42	dpp->tf_regs->reg
 43
 44#define CTX \
 45	dpp->base.ctx
 46
 47#undef FN
 48#define FN(reg_name, field_name) \
 49	dpp->tf_shift->field_name, dpp->tf_mask->field_name
 50
 51enum pixel_format_description {
 52	PIXEL_FORMAT_FIXED = 0,
 53	PIXEL_FORMAT_FIXED16,
 54	PIXEL_FORMAT_FLOAT
 55
 56};
 57
 58enum dcn10_coef_filter_type_sel {
 59	SCL_COEF_LUMA_VERT_FILTER = 0,
 60	SCL_COEF_LUMA_HORZ_FILTER = 1,
 61	SCL_COEF_CHROMA_VERT_FILTER = 2,
 62	SCL_COEF_CHROMA_HORZ_FILTER = 3,
 63	SCL_COEF_ALPHA_VERT_FILTER = 4,
 64	SCL_COEF_ALPHA_HORZ_FILTER = 5
 65};
 66
 67enum dscl_autocal_mode {
 68	AUTOCAL_MODE_OFF = 0,
 69
 70	/* Autocal calculate the scaling ratio and initial phase and the
 71	 * DSCL_MODE_SEL must be set to 1
 72	 */
 73	AUTOCAL_MODE_AUTOSCALE = 1,
 74	/* Autocal perform auto centering without replication and the
 75	 * DSCL_MODE_SEL must be set to 0
 76	 */
 77	AUTOCAL_MODE_AUTOCENTER = 2,
 78	/* Autocal perform auto centering and auto replication and the
 79	 * DSCL_MODE_SEL must be set to 0
 80	 */
 81	AUTOCAL_MODE_AUTOREPLICATE = 3
 82};
 83
 84enum dscl_mode_sel {
 85	DSCL_MODE_SCALING_444_BYPASS = 0,
 86	DSCL_MODE_SCALING_444_RGB_ENABLE = 1,
 87	DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
 88	DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3,
 89	DSCL_MODE_SCALING_420_LUMA_BYPASS = 4,
 90	DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5,
 91	DSCL_MODE_DSCL_BYPASS = 6
 92};
 93
 94void dpp_read_state(struct dpp *dpp_base,
 95		struct dcn_dpp_state *s)
 96{
 97	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 98
 99	REG_GET(DPP_CONTROL,
100			DPP_CLOCK_ENABLE, &s->is_enabled);
101	REG_GET(CM_IGAM_CONTROL,
102			CM_IGAM_LUT_MODE, &s->igam_lut_mode);
103	REG_GET(CM_IGAM_CONTROL,
104			CM_IGAM_INPUT_FORMAT, &s->igam_input_format);
105	REG_GET(CM_DGAM_CONTROL,
106			CM_DGAM_LUT_MODE, &s->dgam_lut_mode);
107	REG_GET(CM_RGAM_CONTROL,
108			CM_RGAM_LUT_MODE, &s->rgam_lut_mode);
109	REG_GET(CM_GAMUT_REMAP_CONTROL,
110			CM_GAMUT_REMAP_MODE, &s->gamut_remap_mode);
111
112	if (s->gamut_remap_mode) {
113		s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12);
114		s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14);
115		s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22);
116		s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24);
117		s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32);
118		s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34);
119	}
120}
121
122#define IDENTITY_RATIO(ratio) (dc_fixpt_u2d19(ratio) == (1 << 19))
123
124bool dpp1_get_optimal_number_of_taps(
125		struct dpp *dpp,
126		struct scaler_data *scl_data,
127		const struct scaling_taps *in_taps)
128{
129	/* Some ASICs does not support  FP16 scaling, so we reject modes require this*/
130	if (scl_data->format == PIXEL_FORMAT_FP16 &&
131		dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
132		scl_data->ratios.horz.value != dc_fixpt_one.value &&
133		scl_data->ratios.vert.value != dc_fixpt_one.value)
134		return false;
135
136	if (scl_data->viewport.width > scl_data->h_active &&
137		dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
138		scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
139		return false;
140
141	/* TODO: add lb check */
142
143	/* No support for programming ratio of 4, drop to 3.99999.. */
144	if (scl_data->ratios.horz.value == (4ll << 32))
145		scl_data->ratios.horz.value--;
146	if (scl_data->ratios.vert.value == (4ll << 32))
147		scl_data->ratios.vert.value--;
148	if (scl_data->ratios.horz_c.value == (4ll << 32))
149		scl_data->ratios.horz_c.value--;
150	if (scl_data->ratios.vert_c.value == (4ll << 32))
151		scl_data->ratios.vert_c.value--;
152
153	/* Set default taps if none are provided */
154	if (in_taps->h_taps == 0)
155		scl_data->taps.h_taps = 4;
156	else
157		scl_data->taps.h_taps = in_taps->h_taps;
158	if (in_taps->v_taps == 0)
159		scl_data->taps.v_taps = 4;
160	else
161		scl_data->taps.v_taps = in_taps->v_taps;
162	if (in_taps->v_taps_c == 0)
163		scl_data->taps.v_taps_c = 2;
164	else
165		scl_data->taps.v_taps_c = in_taps->v_taps_c;
166	if (in_taps->h_taps_c == 0)
167		scl_data->taps.h_taps_c = 2;
168	/* Only 1 and even h_taps_c are supported by hw */
169	else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
170		scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
171	else
172		scl_data->taps.h_taps_c = in_taps->h_taps_c;
173
174	if (!dpp->ctx->dc->debug.always_scale) {
175		if (IDENTITY_RATIO(scl_data->ratios.horz))
176			scl_data->taps.h_taps = 1;
177		if (IDENTITY_RATIO(scl_data->ratios.vert))
178			scl_data->taps.v_taps = 1;
179		if (IDENTITY_RATIO(scl_data->ratios.horz_c))
180			scl_data->taps.h_taps_c = 1;
181		if (IDENTITY_RATIO(scl_data->ratios.vert_c))
182			scl_data->taps.v_taps_c = 1;
183	}
184
185	return true;
186}
187
188void dpp_reset(struct dpp *dpp_base)
189{
190	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
191
192	dpp->filter_h_c = NULL;
193	dpp->filter_v_c = NULL;
194	dpp->filter_h = NULL;
195	dpp->filter_v = NULL;
196
197	memset(&dpp_base->pos, 0, sizeof(dpp_base->pos));
198	memset(&dpp_base->att, 0, sizeof(dpp_base->att));
199
200	memset(&dpp->scl_data, 0, sizeof(dpp->scl_data));
201	memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data));
202
203	dpp_base->cursor_offload = false;
204}
205
206
207
208static void dpp1_cm_set_regamma_pwl(
209	struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode)
210{
211	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
212	uint32_t re_mode = 0;
213
214	switch (mode) {
215	case OPP_REGAMMA_BYPASS:
216		re_mode = 0;
217		break;
218	case OPP_REGAMMA_SRGB:
219		re_mode = 1;
220		break;
221	case OPP_REGAMMA_XVYCC:
222		re_mode = 2;
223		break;
224	case OPP_REGAMMA_USER:
225		re_mode = dpp->is_write_to_ram_a_safe ? 4 : 3;
226		if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0)
227			break;
228
229		dpp1_cm_power_on_regamma_lut(dpp_base, true);
230		dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe);
231
232		if (dpp->is_write_to_ram_a_safe)
233			dpp1_cm_program_regamma_luta_settings(dpp_base, params);
234		else
235			dpp1_cm_program_regamma_lutb_settings(dpp_base, params);
236
237		dpp1_cm_program_regamma_lut(dpp_base, params->rgb_resulted,
238					    params->hw_points_num);
239		dpp->pwl_data = *params;
240
241		re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4;
242		dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe;
243		break;
244	default:
245		break;
246	}
247	REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode);
248}
249
250static void dpp1_setup_format_flags(enum surface_pixel_format input_format,\
251						enum pixel_format_description *fmt)
252{
253
254	if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F ||
255		input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F)
256		*fmt = PIXEL_FORMAT_FLOAT;
257	else if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ||
258		input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616)
259		*fmt = PIXEL_FORMAT_FIXED16;
260	else
261		*fmt = PIXEL_FORMAT_FIXED;
262}
263
264static void dpp1_set_degamma_format_float(
265		struct dpp *dpp_base,
266		bool is_float)
267{
268	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
269
270	if (is_float) {
271		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3);
272		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1);
273	} else {
274		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2);
275		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0);
276	}
277}
278
279void dpp1_cnv_setup (
280		struct dpp *dpp_base,
281		enum surface_pixel_format format,
282		enum expansion_mode mode,
283		struct dc_csc_transform input_csc_color_matrix,
284		enum dc_color_space input_color_space,
285		struct cnv_alpha_2bit_lut *alpha_2bit_lut)
286{
287	uint32_t pixel_format;
288	uint32_t alpha_en;
289	enum pixel_format_description fmt ;
290	enum dc_color_space color_space;
291	enum dcn10_input_csc_select select;
292	bool is_float;
293	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
294	bool force_disable_cursor = false;
295	struct out_csc_color_matrix tbl_entry;
296	int i = 0;
297
298	dpp1_setup_format_flags(format, &fmt);
299	alpha_en = 1;
300	pixel_format = 0;
301	color_space = COLOR_SPACE_SRGB;
302	select = INPUT_CSC_SELECT_BYPASS;
303	is_float = false;
304
305	switch (fmt) {
306	case PIXEL_FORMAT_FIXED:
307	case PIXEL_FORMAT_FIXED16:
308	/*when output is float then FORMAT_CONTROL__OUTPUT_FP=1*/
309		REG_SET_3(FORMAT_CONTROL, 0,
310			CNVC_BYPASS, 0,
311			FORMAT_EXPANSION_MODE, mode,
312			OUTPUT_FP, 0);
313		break;
314	case PIXEL_FORMAT_FLOAT:
315		REG_SET_3(FORMAT_CONTROL, 0,
316			CNVC_BYPASS, 0,
317			FORMAT_EXPANSION_MODE, mode,
318			OUTPUT_FP, 1);
319		is_float = true;
320		break;
321	default:
322
323		break;
324	}
325
326	dpp1_set_degamma_format_float(dpp_base, is_float);
327
328	switch (format) {
329	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
330		pixel_format = 1;
331		break;
332	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
333		pixel_format = 3;
334		alpha_en = 0;
335		break;
336	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
337	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
338		pixel_format = 8;
339		break;
340	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
341	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
342		pixel_format = 10;
343		break;
344	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
345		force_disable_cursor = false;
346		pixel_format = 65;
347		color_space = COLOR_SPACE_YCBCR709;
348		select = INPUT_CSC_SELECT_ICSC;
349		break;
350	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
351		force_disable_cursor = true;
352		pixel_format = 64;
353		color_space = COLOR_SPACE_YCBCR709;
354		select = INPUT_CSC_SELECT_ICSC;
355		break;
356	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
357		force_disable_cursor = true;
358		pixel_format = 67;
359		color_space = COLOR_SPACE_YCBCR709;
360		select = INPUT_CSC_SELECT_ICSC;
361		break;
362	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
363		force_disable_cursor = true;
364		pixel_format = 66;
365		color_space = COLOR_SPACE_YCBCR709;
366		select = INPUT_CSC_SELECT_ICSC;
367		break;
368	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
369	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
370		pixel_format = 26; /* ARGB16161616_UNORM */
371		break;
372	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
373		pixel_format = 24;
374		break;
375	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
376		pixel_format = 25;
377		break;
378	default:
379		break;
380	}
381
382	/* Set default color space based on format if none is given. */
383	color_space = input_color_space ? input_color_space : color_space;
384
385	REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
386			CNVC_SURFACE_PIXEL_FORMAT, pixel_format);
387	REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
388
389	// if input adjustments exist, program icsc with those values
390
391	if (input_csc_color_matrix.enable_adjustment
392				== true) {
393		for (i = 0; i < 12; i++)
394			tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
395
396		tbl_entry.color_space = color_space;
397
398		if (color_space >= COLOR_SPACE_YCBCR601)
399			select = INPUT_CSC_SELECT_ICSC;
400		else
401			select = INPUT_CSC_SELECT_BYPASS;
402
403		dpp1_program_input_csc(dpp_base, color_space, select, &tbl_entry);
404	} else
405		dpp1_program_input_csc(dpp_base, color_space, select, NULL);
406
407	if (force_disable_cursor) {
408		REG_UPDATE(CURSOR_CONTROL,
409				CURSOR_ENABLE, 0);
410		REG_UPDATE(CURSOR0_CONTROL,
411				CUR0_ENABLE, 0);
412	}
413}
414
415void dpp1_set_cursor_attributes(
416		struct dpp *dpp_base,
417		struct dc_cursor_attributes *cursor_attributes)
418{
419	enum dc_cursor_color_format color_format = cursor_attributes->color_format;
420	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
421
422	REG_UPDATE_2(CURSOR0_CONTROL,
423			CUR0_MODE, color_format,
424			CUR0_EXPANSION_MODE, 0);
425
426	if (color_format == CURSOR_MODE_MONO) {
427		/* todo: clarify what to program these to */
428		REG_UPDATE(CURSOR0_COLOR0,
429				CUR0_COLOR0, 0x00000000);
430		REG_UPDATE(CURSOR0_COLOR1,
431				CUR0_COLOR1, 0xFFFFFFFF);
432	}
433}
434
435
436void dpp1_set_cursor_position(
437		struct dpp *dpp_base,
438		const struct dc_cursor_position *pos,
439		const struct dc_cursor_mi_param *param,
440		uint32_t width,
441		uint32_t height)
442{
443	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
444	int x_pos = pos->x - param->viewport.x;
445	int y_pos = pos->y - param->viewport.y;
446	int x_hotspot = pos->x_hotspot;
447	int y_hotspot = pos->y_hotspot;
448	int src_x_offset = x_pos - pos->x_hotspot;
449	int src_y_offset = y_pos - pos->y_hotspot;
450	int cursor_height = (int)height;
451	int cursor_width = (int)width;
452	uint32_t cur_en = pos->enable ? 1 : 0;
453
454	// Transform cursor width / height and hotspots for offset calculations
455	if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
456		swap(cursor_height, cursor_width);
457		swap(x_hotspot, y_hotspot);
458
459		if (param->rotation == ROTATION_ANGLE_90) {
460			// hotspot = (-y, x)
461			src_x_offset = x_pos - (cursor_width - x_hotspot);
462			src_y_offset = y_pos - y_hotspot;
463		} else if (param->rotation == ROTATION_ANGLE_270) {
464			// hotspot = (y, -x)
465			src_x_offset = x_pos - x_hotspot;
466			src_y_offset = y_pos - (cursor_height - y_hotspot);
467		}
468	} else if (param->rotation == ROTATION_ANGLE_180) {
469		// hotspot = (-x, -y)
470		if (!param->mirror)
471			src_x_offset = x_pos - (cursor_width - x_hotspot);
472
473		src_y_offset = y_pos - (cursor_height - y_hotspot);
474	}
475
476	if (src_x_offset >= (int)param->viewport.width)
477		cur_en = 0;  /* not visible beyond right edge*/
478
479	if (src_x_offset + cursor_width <= 0)
480		cur_en = 0;  /* not visible beyond left edge*/
481
482	if (src_y_offset >= (int)param->viewport.height)
483		cur_en = 0;  /* not visible beyond bottom edge*/
484
485	if (src_y_offset + cursor_height <= 0)
486		cur_en = 0;  /* not visible beyond top edge*/
487
488	if (dpp_base->pos.cur0_ctl.bits.cur0_enable != cur_en) {
489		if (!dpp_base->cursor_offload)
490			REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, cur_en);
491	}
492
493	dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en;
494	dpp_base->att.cur0_ctl.bits.cur0_enable = cur_en;
495}
496
497void dpp1_cnv_set_optional_cursor_attributes(
498		struct dpp *dpp_base,
499		struct dpp_cursor_attributes *attr)
500{
501	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
502
503	if (attr) {
504		if (!dpp_base->cursor_offload) {
505			REG_UPDATE(CURSOR0_FP_SCALE_BIAS,  CUR0_FP_BIAS,  attr->bias);
506			REG_UPDATE(CURSOR0_FP_SCALE_BIAS,  CUR0_FP_SCALE, attr->scale);
507		}
508
509		dpp_base->att.fp_scale_bias.bits.fp_bias = attr->bias;
510		dpp_base->att.fp_scale_bias.bits.fp_scale = attr->scale;
511	}
512}
513
514void dpp1_dppclk_control(
515		struct dpp *dpp_base,
516		bool dppclk_div,
517		bool enable)
518{
519	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
520
521	if (enable) {
522		if (dpp->tf_mask->DPPCLK_RATE_CONTROL)
523			REG_UPDATE_2(DPP_CONTROL,
524				DPPCLK_RATE_CONTROL, dppclk_div,
525				DPP_CLOCK_ENABLE, 1);
526		else
527			REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1);
528	} else
529		REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 0);
530}
531
532void dpp_force_disable_cursor(struct dpp *dpp_base)
533{
534	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
535
536	/* Force disable cursor */
537	REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, 0);
538	dpp_base->pos.cur0_ctl.bits.cur0_enable = 0;
539}
540
541static const struct dpp_funcs dcn10_dpp_funcs = {
542		.dpp_read_state = dpp_read_state,
543		.dpp_reset = dpp_reset,
544		.dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
545		.dpp_get_optimal_number_of_taps = dpp1_get_optimal_number_of_taps,
546		.dpp_set_gamut_remap = dpp1_cm_set_gamut_remap,
547		.dpp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment,
548		.dpp_set_csc_default = dpp1_cm_set_output_csc_default,
549		.dpp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut,
550		.dpp_program_regamma_lut = dpp1_cm_program_regamma_lut,
551		.dpp_configure_regamma_lut = dpp1_cm_configure_regamma_lut,
552		.dpp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings,
553		.dpp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings,
554		.dpp_program_regamma_pwl = dpp1_cm_set_regamma_pwl,
555		.dpp_program_bias_and_scale = dpp1_program_bias_and_scale,
556		.dpp_set_degamma = dpp1_set_degamma,
557		.dpp_program_input_lut		= dpp1_program_input_lut,
558		.dpp_program_degamma_pwl	= dpp1_set_degamma_pwl,
559		.dpp_setup			= dpp1_cnv_setup,
560		.dpp_full_bypass		= dpp1_full_bypass,
561		.set_cursor_attributes = dpp1_set_cursor_attributes,
562		.set_cursor_position = dpp1_set_cursor_position,
563		.set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
564		.dpp_dppclk_control = dpp1_dppclk_control,
565		.dpp_set_hdr_multiplier = dpp1_set_hdr_multiplier,
566		.dpp_program_blnd_lut = NULL,
567		.dpp_program_shaper_lut = NULL,
568		.dpp_program_3dlut = NULL,
569		.dpp_get_gamut_remap = dpp1_cm_get_gamut_remap,
570};
571
572static struct dpp_caps dcn10_dpp_cap = {
573	.dscl_data_proc_format = DSCL_DATA_PRCESSING_FIXED_FORMAT,
574	.dscl_calc_lb_num_partitions = dpp1_dscl_calc_lb_num_partitions,
575};
576
577/*****************************************/
578/* Constructor, Destructor               */
579/*****************************************/
580
581void dpp1_construct(
582	struct dcn10_dpp *dpp,
583	struct dc_context *ctx,
584	uint32_t inst,
585	const struct dcn_dpp_registers *tf_regs,
586	const struct dcn_dpp_shift *tf_shift,
587	const struct dcn_dpp_mask *tf_mask)
588{
589	dpp->base.ctx = ctx;
590
591	dpp->base.inst = inst;
592	dpp->base.funcs = &dcn10_dpp_funcs;
593	dpp->base.caps = &dcn10_dpp_cap;
594
595	dpp->tf_regs = tf_regs;
596	dpp->tf_shift = tf_shift;
597	dpp->tf_mask = tf_mask;
598
599	dpp->lb_pixel_depth_supported =
600		LB_PIXEL_DEPTH_18BPP |
601		LB_PIXEL_DEPTH_24BPP |
602		LB_PIXEL_DEPTH_30BPP |
603		LB_PIXEL_DEPTH_36BPP;
604
605	dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
606	dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
607}