dml2_translation_helper.c

   1/* SPDX-License-Identifier: MIT */
   2/*
   3 * Copyright 2023 Advanced Micro Devices, Inc.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21 * OTHER DEALINGS IN THE SOFTWARE.
  22 *
  23 * Authors: AMD
  24 *
  25 */
  26
  27#include "display_mode_core.h"
  28#include "dml2_internal_types.h"
  29#include "dml2_translation_helper.h"
  30
  31#define NUM_DCFCLK_STAS 5
  32#define NUM_DCFCLK_STAS_NEW 8
  33
  34void dml2_init_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out)
  35{
  36	switch (dml2->v20.dml_core_ctx.project) {
  37	case dml_project_dcn32:
  38	case dml_project_dcn321:
  39	default:
  40		// Hardcoded values for DCN32x
  41		out->vblank_nom_default_us = 600;
  42		out->rob_buffer_size_kbytes = 128;
  43		out->config_return_buffer_size_in_kbytes = 1280;
  44		out->config_return_buffer_segment_size_in_kbytes = 64;
  45		out->compressed_buffer_segment_size_in_kbytes = 64;
  46		out->meta_fifo_size_in_kentries = 22;
  47		out->zero_size_buffer_entries = 512;
  48		out->dpte_buffer_size_in_pte_reqs_luma = 68;
  49		out->dpte_buffer_size_in_pte_reqs_chroma = 36;
  50		out->dcc_meta_buffer_size_bytes = 6272;
  51		out->gpuvm_max_page_table_levels = 4;
  52		out->hostvm_max_page_table_levels = 0;
  53		out->pixel_chunk_size_kbytes = 8;
  54		//out->alpha_pixel_chunk_size_kbytes;
  55		out->min_pixel_chunk_size_bytes = 1024;
  56		out->meta_chunk_size_kbytes = 2;
  57		out->min_meta_chunk_size_bytes = 256;
  58		out->writeback_chunk_size_kbytes = 8;
  59		out->line_buffer_size_bits = 1171920;
  60		out->max_line_buffer_lines = 32;
  61		out->writeback_interface_buffer_size_kbytes = 90;
  62		//Number of pipes after DCN Pipe harvesting
  63		out->max_num_dpp = dml2->config.dcn_pipe_count;
  64		out->max_num_otg = dml2->config.dcn_pipe_count;
  65		out->max_num_wb = 1;
  66		out->max_dchub_pscl_bw_pix_per_clk = 4;
  67		out->max_pscl_lb_bw_pix_per_clk = 2;
  68		out->max_lb_vscl_bw_pix_per_clk = 4;
  69		out->max_vscl_hscl_bw_pix_per_clk = 4;
  70		out->max_hscl_ratio = 6;
  71		out->max_vscl_ratio = 6;
  72		out->max_hscl_taps = 8;
  73		out->max_vscl_taps = 8;
  74		out->dispclk_ramp_margin_percent = 1;
  75		out->dppclk_delay_subtotal = 47;
  76		out->dppclk_delay_scl = 50;
  77		out->dppclk_delay_scl_lb_only = 16;
  78		out->dppclk_delay_cnvc_formatter = 28;
  79		out->dppclk_delay_cnvc_cursor = 6;
  80		out->cursor_buffer_size = 16;
  81		out->cursor_chunk_size = 2;
  82		out->dispclk_delay_subtotal = 125;
  83		out->max_inter_dcn_tile_repeaters = 8;
  84		out->writeback_max_hscl_ratio = 1;
  85		out->writeback_max_vscl_ratio = 1;
  86		out->writeback_min_hscl_ratio = 1;
  87		out->writeback_min_vscl_ratio = 1;
  88		out->writeback_max_hscl_taps = 1;
  89		out->writeback_max_vscl_taps = 1;
  90		out->writeback_line_buffer_buffer_size = 0;
  91		out->num_dsc = 4;
  92		out->maximum_dsc_bits_per_component = 12;
  93		out->maximum_pixels_per_line_per_dsc_unit = 6016;
  94		out->dsc422_native_support = true;
  95		out->dcc_supported = true;
  96		out->ptoi_supported = false;
  97
  98		out->gpuvm_enable = false;
  99		out->hostvm_enable = false;
 100		out->cursor_64bpp_support = false;
 101		out->dynamic_metadata_vm_enabled = false;
 102
 103		out->max_num_hdmi_frl_outputs = 1;
 104		out->max_num_dp2p0_outputs = 2;
 105		out->max_num_dp2p0_streams = 4;
 106		break;
 107
 108	case dml_project_dcn35:
 109	case dml_project_dcn351:
 110	case dml_project_dcn36:
 111		out->rob_buffer_size_kbytes = 64;
 112		out->config_return_buffer_size_in_kbytes = 1792;
 113		out->compressed_buffer_segment_size_in_kbytes = 64;
 114		out->meta_fifo_size_in_kentries = 32;
 115		out->zero_size_buffer_entries = 512;
 116		out->pixel_chunk_size_kbytes = 8;
 117		out->alpha_pixel_chunk_size_kbytes = 4;
 118		out->min_pixel_chunk_size_bytes = 1024;
 119		out->meta_chunk_size_kbytes = 2;
 120		out->min_meta_chunk_size_bytes = 256;
 121		out->writeback_chunk_size_kbytes = 8;
 122		out->dpte_buffer_size_in_pte_reqs_luma = 68;
 123		out->dpte_buffer_size_in_pte_reqs_chroma = 36;
 124		out->dcc_meta_buffer_size_bytes = 6272;
 125		out->gpuvm_enable = 1;
 126		out->hostvm_enable = 1;
 127		out->gpuvm_max_page_table_levels = 1;
 128		out->hostvm_max_page_table_levels = 2;
 129		out->num_dsc = 4;
 130		out->maximum_dsc_bits_per_component = 12;
 131		out->maximum_pixels_per_line_per_dsc_unit = 6016;
 132		out->dsc422_native_support = 1;
 133		out->line_buffer_size_bits = 986880;
 134		out->dcc_supported = 1;
 135		out->max_line_buffer_lines = 32;
 136		out->writeback_interface_buffer_size_kbytes = 90;
 137		out->max_num_dpp = 4;
 138		out->max_num_otg = 4;
 139		out->max_num_hdmi_frl_outputs = 1;
 140		out->max_num_dp2p0_outputs = 2;
 141		out->max_num_dp2p0_streams = 4;
 142		out->max_num_wb = 1;
 143
 144		out->max_dchub_pscl_bw_pix_per_clk = 4;
 145		out->max_pscl_lb_bw_pix_per_clk = 2;
 146		out->max_lb_vscl_bw_pix_per_clk = 4;
 147		out->max_vscl_hscl_bw_pix_per_clk = 4;
 148		out->max_hscl_ratio = 6;
 149		out->max_vscl_ratio = 6;
 150		out->max_hscl_taps = 8;
 151		out->max_vscl_taps = 8;
 152		out->dispclk_ramp_margin_percent = 1.11;
 153
 154		out->dppclk_delay_subtotal = 47;
 155		out->dppclk_delay_scl = 50;
 156		out->dppclk_delay_scl_lb_only = 16;
 157		out->dppclk_delay_cnvc_formatter = 28;
 158		out->dppclk_delay_cnvc_cursor = 6;
 159		out->dispclk_delay_subtotal = 125;
 160
 161		out->dynamic_metadata_vm_enabled = false;
 162		out->max_inter_dcn_tile_repeaters = 8;
 163		out->cursor_buffer_size = 16; // kBytes
 164		out->cursor_chunk_size = 2; // kBytes
 165
 166		out->writeback_line_buffer_buffer_size = 0;
 167		out->writeback_max_hscl_ratio = 1;
 168		out->writeback_max_vscl_ratio = 1;
 169		out->writeback_min_hscl_ratio = 1;
 170		out->writeback_min_vscl_ratio = 1;
 171		out->writeback_max_hscl_taps  = 1;
 172		out->writeback_max_vscl_taps  = 1;
 173		out->ptoi_supported	= 0;
 174
 175		out->vblank_nom_default_us = 668; /*not in dml, but in programming guide, hard coded in dml2_translate_ip_params*/
 176		out->config_return_buffer_segment_size_in_kbytes = 64; /*required, but not exist,, hard coded in dml2_translate_ip_params*/
 177		break;
 178
 179	case dml_project_dcn401:
 180		// Hardcoded values for DCN4m
 181		out->vblank_nom_default_us = 668;	//600;
 182		out->rob_buffer_size_kbytes = 192;	//128;
 183		out->config_return_buffer_size_in_kbytes = 1344;	//1280;
 184		out->config_return_buffer_segment_size_in_kbytes = 64;
 185		out->compressed_buffer_segment_size_in_kbytes = 64;
 186		out->meta_fifo_size_in_kentries = 22;
 187		out->dpte_buffer_size_in_pte_reqs_luma = 68;
 188		out->dpte_buffer_size_in_pte_reqs_chroma = 36;
 189		out->gpuvm_max_page_table_levels = 4;
 190		out->pixel_chunk_size_kbytes = 8;
 191		out->alpha_pixel_chunk_size_kbytes = 4;
 192		out->min_pixel_chunk_size_bytes = 1024;
 193		out->writeback_chunk_size_kbytes = 8;
 194		out->line_buffer_size_bits = 1171920;
 195		out->max_line_buffer_lines = 32;
 196		out->writeback_interface_buffer_size_kbytes = 90;
 197		//Number of pipes after DCN Pipe harvesting
 198		out->max_num_dpp = dml2->config.dcn_pipe_count;
 199		out->max_num_otg = dml2->config.dcn_pipe_count;
 200		out->max_num_wb = 1;
 201		out->max_dchub_pscl_bw_pix_per_clk = 4;
 202		out->max_pscl_lb_bw_pix_per_clk = 2;
 203		out->max_lb_vscl_bw_pix_per_clk = 4;
 204		out->max_vscl_hscl_bw_pix_per_clk = 4;
 205		out->max_hscl_ratio = 6;
 206		out->max_vscl_ratio = 6;
 207		out->max_hscl_taps = 8;
 208		out->max_vscl_taps = 8;
 209		out->dispclk_ramp_margin_percent = 1;
 210		out->dppclk_delay_subtotal = 47;
 211		out->dppclk_delay_scl = 50;
 212		out->dppclk_delay_scl_lb_only = 16;
 213		out->dppclk_delay_cnvc_formatter = 28;
 214		out->dppclk_delay_cnvc_cursor = 6;
 215		out->dispclk_delay_subtotal = 125;
 216		out->cursor_buffer_size = 24;	//16
 217		out->cursor_chunk_size = 2;
 218		out->max_inter_dcn_tile_repeaters = 8;
 219		out->writeback_max_hscl_ratio = 1;
 220		out->writeback_max_vscl_ratio = 1;
 221		out->writeback_min_hscl_ratio = 1;
 222		out->writeback_min_vscl_ratio = 1;
 223		out->writeback_max_hscl_taps = 1;
 224		out->writeback_max_vscl_taps = 1;
 225		out->writeback_line_buffer_buffer_size = 0;
 226		out->num_dsc = 4;
 227		out->maximum_dsc_bits_per_component = 12;
 228		out->maximum_pixels_per_line_per_dsc_unit = 5760;
 229		out->dsc422_native_support = true;
 230		out->dcc_supported = true;
 231		out->ptoi_supported = false;
 232
 233		out->gpuvm_enable = false;
 234		out->hostvm_enable = false;
 235		out->cursor_64bpp_support = true;	//false;
 236		out->dynamic_metadata_vm_enabled = false;
 237
 238		out->max_num_hdmi_frl_outputs = 1;
 239		out->max_num_dp2p0_outputs = 4;		//2;
 240		out->max_num_dp2p0_streams = 4;
 241		break;
 242	}
 243}
 244
 245void dml2_init_socbb_params(struct dml2_context *dml2, const struct dc *in_dc, struct soc_bounding_box_st *out)
 246{
 247	out->dprefclk_mhz = dml2->config.bbox_overrides.dprefclk_mhz;
 248	out->xtalclk_mhz = dml2->config.bbox_overrides.xtalclk_mhz;
 249	out->pcierefclk_mhz = 100;
 250	out->refclk_mhz = dml2->config.bbox_overrides.dchub_refclk_mhz;
 251
 252	out->max_outstanding_reqs = 512;
 253	out->pct_ideal_sdp_bw_after_urgent = 100;
 254	out->pct_ideal_fabric_bw_after_urgent = 67;
 255	out->pct_ideal_dram_bw_after_urgent_pixel_only = 20;
 256	out->pct_ideal_dram_bw_after_urgent_pixel_and_vm = 60;
 257	out->pct_ideal_dram_bw_after_urgent_vm_only = 30;
 258	out->pct_ideal_dram_bw_after_urgent_strobe = 67;
 259	out->max_avg_sdp_bw_use_normal_percent = 80;
 260	out->max_avg_fabric_bw_use_normal_percent = 60;
 261	out->max_avg_dram_bw_use_normal_percent = 15;
 262	out->max_avg_dram_bw_use_normal_strobe_percent = 50;
 263
 264	out->urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096;
 265	out->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096;
 266	out->urgent_out_of_order_return_per_channel_vm_only_bytes = 4096;
 267	out->return_bus_width_bytes = 64;
 268	out->dram_channel_width_bytes = 2;
 269	out->fabric_datapath_to_dcn_data_return_bytes = 64;
 270	out->hostvm_min_page_size_kbytes = 0;
 271	out->gpuvm_min_page_size_kbytes = 256;
 272	out->phy_downspread_percent = 0.38;
 273	out->dcn_downspread_percent = 0.5;
 274	out->dispclk_dppclk_vco_speed_mhz = dml2->config.bbox_overrides.disp_pll_vco_speed_mhz;
 275	out->mall_allocated_for_dcn_mbytes = dml2->config.mall_cfg.max_cab_allocation_bytes / 1048576; // 64 or 32 MB;
 276
 277	out->do_urgent_latency_adjustment = true;
 278
 279	switch (dml2->v20.dml_core_ctx.project) {
 280
 281	case dml_project_dcn32:
 282	default:
 283		out->num_chans = 24;
 284		out->round_trip_ping_latency_dcfclk_cycles = 263;
 285		out->smn_latency_us = 2;
 286		break;
 287
 288	case dml_project_dcn321:
 289		out->num_chans = 8;
 290		out->round_trip_ping_latency_dcfclk_cycles = 207;
 291		out->smn_latency_us = 0;
 292		break;
 293
 294	case dml_project_dcn35:
 295	case dml_project_dcn351:
 296	case dml_project_dcn36:
 297		out->num_chans = 4;
 298		out->round_trip_ping_latency_dcfclk_cycles = 106;
 299		out->smn_latency_us = 2;
 300		out->dispclk_dppclk_vco_speed_mhz = 3600;
 301		out->pct_ideal_dram_bw_after_urgent_pixel_only = 65.0;
 302		break;
 303
 304
 305	case dml_project_dcn401:
 306		out->pct_ideal_fabric_bw_after_urgent = 76;			//67;
 307		out->max_avg_sdp_bw_use_normal_percent = 75;		//80;
 308		out->max_avg_fabric_bw_use_normal_percent = 57;		//60;
 309
 310		out->urgent_out_of_order_return_per_channel_pixel_only_bytes = 0;	//4096;
 311		out->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 0;	//4096;
 312		out->urgent_out_of_order_return_per_channel_vm_only_bytes = 0;		//4096;
 313
 314		out->num_chans = 16;
 315		out->round_trip_ping_latency_dcfclk_cycles = 1000;	//263;
 316		out->smn_latency_us = 0;							//2 us
 317		out->mall_allocated_for_dcn_mbytes = dml2->config.mall_cfg.max_cab_allocation_bytes / 1048576; // 64;
 318		break;
 319	}
 320	/* ---Overrides if available--- */
 321	if (dml2->config.bbox_overrides.dram_num_chan)
 322		out->num_chans = dml2->config.bbox_overrides.dram_num_chan;
 323
 324	if (dml2->config.bbox_overrides.dram_chanel_width_bytes)
 325		out->dram_channel_width_bytes = dml2->config.bbox_overrides.dram_chanel_width_bytes;
 326}
 327
 328void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,
 329	const struct soc_bounding_box_st *in_bbox, struct soc_states_st *out)
 330{
 331	struct dml2_policy_build_synthetic_soc_states_scratch *s = &dml2->v20.scratch.create_scratch.build_synthetic_socbb_scratch;
 332	struct dml2_policy_build_synthetic_soc_states_params *p = &dml2->v20.scratch.build_synthetic_socbb_params;
 333	unsigned int dcfclk_stas_mhz[NUM_DCFCLK_STAS] = {0};
 334	unsigned int dcfclk_stas_mhz_new[NUM_DCFCLK_STAS_NEW] = {0};
 335	unsigned int dml_project = dml2->v20.dml_core_ctx.project;
 336
 337	unsigned int i = 0;
 338	unsigned int transactions_per_mem_clock = 16; // project specific, depends on used Memory type
 339
 340	if (dml_project == dml_project_dcn351) {
 341		p->dcfclk_stas_mhz = dcfclk_stas_mhz_new;
 342		p->num_dcfclk_stas = NUM_DCFCLK_STAS_NEW;
 343	} else {
 344		p->dcfclk_stas_mhz = dcfclk_stas_mhz;
 345		p->num_dcfclk_stas = NUM_DCFCLK_STAS;
 346	}
 347
 348	p->in_bbox = in_bbox;
 349	p->out_states = out;
 350	p->in_states = &dml2->v20.scratch.create_scratch.in_states;
 351
 352
 353	/* Initial hardcoded values */
 354	switch (dml2->v20.dml_core_ctx.project) {
 355
 356	case dml_project_dcn32:
 357	default:
 358		p->in_states->num_states = 2;
 359		transactions_per_mem_clock = 16;
 360		p->in_states->state_array[0].socclk_mhz = 620.0;
 361		p->in_states->state_array[0].dscclk_mhz = 716.667;
 362		p->in_states->state_array[0].phyclk_mhz = 810;
 363		p->in_states->state_array[0].phyclk_d18_mhz = 667;
 364		p->in_states->state_array[0].phyclk_d32_mhz = 625;
 365		p->in_states->state_array[0].dtbclk_mhz = 1564.0;
 366		p->in_states->state_array[0].fabricclk_mhz = 450.0;
 367		p->in_states->state_array[0].dcfclk_mhz = 300.0;
 368		p->in_states->state_array[0].dispclk_mhz = 2150.0;
 369		p->in_states->state_array[0].dppclk_mhz = 2150.0;
 370		p->in_states->state_array[0].dram_speed_mts = 100 * transactions_per_mem_clock;
 371
 372		p->in_states->state_array[0].urgent_latency_pixel_data_only_us = 4;
 373		p->in_states->state_array[0].urgent_latency_pixel_mixed_with_vm_data_us = 0;
 374		p->in_states->state_array[0].urgent_latency_vm_data_only_us = 0;
 375		p->in_states->state_array[0].writeback_latency_us = 12;
 376		p->in_states->state_array[0].urgent_latency_adjustment_fabric_clock_component_us = 1;
 377		p->in_states->state_array[0].urgent_latency_adjustment_fabric_clock_reference_mhz = 3000;
 378		p->in_states->state_array[0].sr_exit_z8_time_us = 0;
 379		p->in_states->state_array[0].sr_enter_plus_exit_z8_time_us = 0;
 380		p->in_states->state_array[0].dram_clock_change_latency_us = 400;
 381		p->in_states->state_array[0].use_ideal_dram_bw_strobe = true;
 382		p->in_states->state_array[0].sr_exit_time_us = 42.97;
 383		p->in_states->state_array[0].sr_enter_plus_exit_time_us = 49.94;
 384		p->in_states->state_array[0].fclk_change_latency_us = 20;
 385		p->in_states->state_array[0].usr_retraining_latency_us = 2;
 386
 387		p->in_states->state_array[1].socclk_mhz = 1200.0;
 388		p->in_states->state_array[1].fabricclk_mhz = 2500.0;
 389		p->in_states->state_array[1].dcfclk_mhz = 1564.0;
 390		p->in_states->state_array[1].dram_speed_mts = 1125 * transactions_per_mem_clock;
 391		break;
 392
 393	case dml_project_dcn321:
 394		p->in_states->num_states = 2;
 395		transactions_per_mem_clock = 16;
 396		p->in_states->state_array[0].socclk_mhz = 582.0;
 397		p->in_states->state_array[0].dscclk_mhz = 573.333;
 398		p->in_states->state_array[0].phyclk_mhz = 810;
 399		p->in_states->state_array[0].phyclk_d18_mhz = 667;
 400		p->in_states->state_array[0].phyclk_d32_mhz = 313;
 401		p->in_states->state_array[0].dtbclk_mhz = 1564.0;
 402		p->in_states->state_array[0].fabricclk_mhz = 450.0;
 403		p->in_states->state_array[0].dcfclk_mhz = 300.0;
 404		p->in_states->state_array[0].dispclk_mhz = 1720.0;
 405		p->in_states->state_array[0].dppclk_mhz = 1720.0;
 406		p->in_states->state_array[0].dram_speed_mts = 100 * transactions_per_mem_clock;
 407
 408		p->in_states->state_array[0].urgent_latency_pixel_data_only_us = 4;
 409		p->in_states->state_array[0].urgent_latency_pixel_mixed_with_vm_data_us = 0;
 410		p->in_states->state_array[0].urgent_latency_vm_data_only_us = 0;
 411		p->in_states->state_array[0].writeback_latency_us = 12;
 412		p->in_states->state_array[0].urgent_latency_adjustment_fabric_clock_component_us = 1;
 413		p->in_states->state_array[0].urgent_latency_adjustment_fabric_clock_reference_mhz = 3000;
 414		p->in_states->state_array[0].sr_exit_z8_time_us = 0;
 415		p->in_states->state_array[0].sr_enter_plus_exit_z8_time_us = 0;
 416		p->in_states->state_array[0].dram_clock_change_latency_us = 400;
 417		p->in_states->state_array[0].use_ideal_dram_bw_strobe = true;
 418		p->in_states->state_array[0].sr_exit_time_us = 19.95;
 419		p->in_states->state_array[0].sr_enter_plus_exit_time_us = 24.36;
 420		p->in_states->state_array[0].fclk_change_latency_us = 7;
 421		p->in_states->state_array[0].usr_retraining_latency_us = 0;
 422
 423		p->in_states->state_array[1].socclk_mhz = 1200.0;
 424		p->in_states->state_array[1].fabricclk_mhz = 2250.0;
 425		p->in_states->state_array[1].dcfclk_mhz = 1434.0;
 426		p->in_states->state_array[1].dram_speed_mts = 1000 * transactions_per_mem_clock;
 427		break;
 428
 429
 430	case dml_project_dcn401:
 431		p->in_states->num_states = 2;
 432		transactions_per_mem_clock = 16;
 433		p->in_states->state_array[0].socclk_mhz = 300;		//620.0;
 434		p->in_states->state_array[0].dscclk_mhz = 666.667;	//716.667;
 435		p->in_states->state_array[0].phyclk_mhz = 810;
 436		p->in_states->state_array[0].phyclk_d18_mhz = 667;
 437		p->in_states->state_array[0].phyclk_d32_mhz = 625;
 438		p->in_states->state_array[0].dtbclk_mhz = 2000;		//1564.0;
 439		p->in_states->state_array[0].fabricclk_mhz = 300;	//450.0;
 440		p->in_states->state_array[0].dcfclk_mhz = 200;		//300.0;
 441		p->in_states->state_array[0].dispclk_mhz = 2000;	//2150.0;
 442		p->in_states->state_array[0].dppclk_mhz = 2000;		//2150.0;
 443		p->in_states->state_array[0].dram_speed_mts = 97 * transactions_per_mem_clock; //100 *
 444
 445		p->in_states->state_array[0].urgent_latency_pixel_data_only_us = 4;
 446		p->in_states->state_array[0].urgent_latency_pixel_mixed_with_vm_data_us = 0;
 447		p->in_states->state_array[0].urgent_latency_vm_data_only_us = 0;
 448		p->in_states->state_array[0].writeback_latency_us = 12;
 449		p->in_states->state_array[0].urgent_latency_adjustment_fabric_clock_component_us = 1;
 450		p->in_states->state_array[0].urgent_latency_adjustment_fabric_clock_reference_mhz = 1000;	//3000;
 451		p->in_states->state_array[0].sr_exit_z8_time_us = 0;
 452		p->in_states->state_array[0].sr_enter_plus_exit_z8_time_us = 0;
 453		p->in_states->state_array[0].dram_clock_change_latency_us = 400;
 454		p->in_states->state_array[0].use_ideal_dram_bw_strobe = true;
 455		p->in_states->state_array[0].sr_exit_time_us = 15.70;	//42.97;
 456		p->in_states->state_array[0].sr_enter_plus_exit_time_us = 20.20;	//49.94;
 457		p->in_states->state_array[0].fclk_change_latency_us = 0;	//20;
 458		p->in_states->state_array[0].usr_retraining_latency_us = 0;	//2;
 459
 460		p->in_states->state_array[1].socclk_mhz = 1600;		//1200.0;
 461		p->in_states->state_array[1].fabricclk_mhz = 2500;	//2500.0;
 462		p->in_states->state_array[1].dcfclk_mhz = 1800;		//1564.0;
 463		p->in_states->state_array[1].dram_speed_mts = 1125 * transactions_per_mem_clock;
 464		break;
 465	}
 466
 467	/* Override from passed values, if available */
 468	for (i = 0; i < p->in_states->num_states; i++) {
 469		if (dml2->config.bbox_overrides.sr_exit_latency_us) {
 470			p->in_states->state_array[i].sr_exit_time_us =
 471				dml2->config.bbox_overrides.sr_exit_latency_us;
 472		}
 473
 474		if (dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us) {
 475			p->in_states->state_array[i].sr_enter_plus_exit_time_us =
 476				dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us;
 477		}
 478
 479		if (dml2->config.bbox_overrides.sr_exit_z8_time_us) {
 480			p->in_states->state_array[i].sr_exit_z8_time_us =
 481				dml2->config.bbox_overrides.sr_exit_z8_time_us;
 482		}
 483
 484		if (dml2->config.bbox_overrides.sr_enter_plus_exit_z8_time_us) {
 485			p->in_states->state_array[i].sr_enter_plus_exit_z8_time_us =
 486				dml2->config.bbox_overrides.sr_enter_plus_exit_z8_time_us;
 487		}
 488
 489		if (dml2->config.bbox_overrides.urgent_latency_us) {
 490			p->in_states->state_array[i].urgent_latency_pixel_data_only_us =
 491				dml2->config.bbox_overrides.urgent_latency_us;
 492		}
 493
 494		if (dml2->config.bbox_overrides.dram_clock_change_latency_us) {
 495			p->in_states->state_array[i].dram_clock_change_latency_us =
 496				dml2->config.bbox_overrides.dram_clock_change_latency_us;
 497		}
 498
 499		if (dml2->config.bbox_overrides.fclk_change_latency_us) {
 500			p->in_states->state_array[i].fclk_change_latency_us =
 501				dml2->config.bbox_overrides.fclk_change_latency_us;
 502		}
 503	}
 504
 505	/* DCFCLK stas values are project specific */
 506	if ((dml2->v20.dml_core_ctx.project == dml_project_dcn32) ||
 507		(dml2->v20.dml_core_ctx.project == dml_project_dcn321)) {
 508		p->dcfclk_stas_mhz[0] = p->in_states->state_array[0].dcfclk_mhz;
 509		p->dcfclk_stas_mhz[1] = 615;
 510		p->dcfclk_stas_mhz[2] = 906;
 511		p->dcfclk_stas_mhz[3] = 1324;
 512		p->dcfclk_stas_mhz[4] = p->in_states->state_array[1].dcfclk_mhz;
 513	} else if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 &&
 514			dml2->v20.dml_core_ctx.project != dml_project_dcn36 &&
 515			dml2->v20.dml_core_ctx.project != dml_project_dcn351) {
 516		p->dcfclk_stas_mhz[0] = 300;
 517		p->dcfclk_stas_mhz[1] = 615;
 518		p->dcfclk_stas_mhz[2] = 906;
 519		p->dcfclk_stas_mhz[3] = 1324;
 520		p->dcfclk_stas_mhz[4] = 1500;
 521	}
 522	/* Copy clocks tables entries, if available */
 523	if (dml2->config.bbox_overrides.clks_table.num_states) {
 524		p->in_states->num_states = dml2->config.bbox_overrides.clks_table.num_states;
 525		for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels; i++) {
 526			p->in_states->state_array[i].dcfclk_mhz = dml2->config.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz;
 527		}
 528
 529		p->dcfclk_stas_mhz[0] = dml2->config.bbox_overrides.clks_table.clk_entries[0].dcfclk_mhz;
 530		if (i > 1)
 531			p->dcfclk_stas_mhz[4] = dml2->config.bbox_overrides.clks_table.clk_entries[i-1].dcfclk_mhz;
 532
 533		for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels; i++) {
 534			p->in_states->state_array[i].fabricclk_mhz =
 535				dml2->config.bbox_overrides.clks_table.clk_entries[i].fclk_mhz;
 536		}
 537
 538		for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels; i++) {
 539			p->in_states->state_array[i].dram_speed_mts =
 540				dml2->config.bbox_overrides.clks_table.clk_entries[i].memclk_mhz * transactions_per_mem_clock;
 541		}
 542
 543		for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels; i++) {
 544			p->in_states->state_array[i].socclk_mhz =
 545				dml2->config.bbox_overrides.clks_table.clk_entries[i].socclk_mhz;
 546		}
 547
 548		for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels; i++) {
 549			if (dml2->config.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz > 0)
 550				p->in_states->state_array[i].dtbclk_mhz =
 551					dml2->config.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz;
 552		}
 553
 554		for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels; i++) {
 555			p->in_states->state_array[i].dispclk_mhz =
 556				dml2->config.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz;
 557			p->in_states->state_array[i].dppclk_mhz =
 558				dml2->config.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz;
 559		}
 560	}
 561
 562	if (dml2->v20.dml_core_ctx.project == dml_project_dcn35 ||
 563	    dml2->v20.dml_core_ctx.project == dml_project_dcn36 ||
 564	    dml2->v20.dml_core_ctx.project == dml_project_dcn351) {
 565		int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0,
 566			max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0, max_socclk_mhz = 0;
 567
 568		for (i = 0; i < p->in_states->num_states; i++) {
 569			if (p->in_states->state_array[i].dcfclk_mhz > max_dcfclk_mhz)
 570				max_dcfclk_mhz = (int)p->in_states->state_array[i].dcfclk_mhz;
 571			if (p->in_states->state_array[i].fabricclk_mhz > max_fclk_mhz)
 572				max_fclk_mhz = (int)p->in_states->state_array[i].fabricclk_mhz;
 573			if (p->in_states->state_array[i].socclk_mhz > max_socclk_mhz)
 574				max_socclk_mhz = (int)p->in_states->state_array[i].socclk_mhz;
 575			if (p->in_states->state_array[i].dram_speed_mts > max_uclk_mhz)
 576				max_uclk_mhz = (int)p->in_states->state_array[i].dram_speed_mts;
 577			if (p->in_states->state_array[i].dispclk_mhz > max_dispclk_mhz)
 578				max_dispclk_mhz = (int)p->in_states->state_array[i].dispclk_mhz;
 579			if (p->in_states->state_array[i].dppclk_mhz > max_dppclk_mhz)
 580				max_dppclk_mhz = (int)p->in_states->state_array[i].dppclk_mhz;
 581			if (p->in_states->state_array[i].phyclk_mhz > max_phyclk_mhz)
 582				max_phyclk_mhz = (int)p->in_states->state_array[i].phyclk_mhz;
 583			if (p->in_states->state_array[i].dtbclk_mhz > max_dtbclk_mhz)
 584				max_dtbclk_mhz = (int)p->in_states->state_array[i].dtbclk_mhz;
 585		}
 586
 587		for (i = 0; i < p->in_states->num_states; i++) {
 588			/* Independent states - including base (unlisted) parameters from state 0. */
 589			p->out_states->state_array[i] = p->in_states->state_array[0];
 590
 591			p->out_states->state_array[i].dispclk_mhz = max_dispclk_mhz;
 592			p->out_states->state_array[i].dppclk_mhz = max_dppclk_mhz;
 593			p->out_states->state_array[i].dtbclk_mhz = max_dtbclk_mhz;
 594			p->out_states->state_array[i].phyclk_mhz = max_phyclk_mhz;
 595
 596			p->out_states->state_array[i].dscclk_mhz = max_dispclk_mhz / 3.0;
 597			p->out_states->state_array[i].phyclk_mhz = max_phyclk_mhz;
 598			p->out_states->state_array[i].dtbclk_mhz = max_dtbclk_mhz;
 599
 600			/* Dependent states. */
 601			p->out_states->state_array[i].dram_speed_mts = p->in_states->state_array[i].dram_speed_mts;
 602			p->out_states->state_array[i].fabricclk_mhz = p->in_states->state_array[i].fabricclk_mhz;
 603			p->out_states->state_array[i].socclk_mhz = p->in_states->state_array[i].socclk_mhz;
 604			p->out_states->state_array[i].dcfclk_mhz = p->in_states->state_array[i].dcfclk_mhz;
 605		}
 606
 607		p->out_states->num_states = p->in_states->num_states;
 608	} else {
 609		dml2_policy_build_synthetic_soc_states(s, p);
 610	}
 611}
 612
 613void dml2_translate_ip_params(const struct dc *in, struct ip_params_st *out)
 614{
 615	const struct _vcs_dpi_ip_params_st *in_ip_params = &in->dml.ip;
 616	/* Copy over the IP params tp dml2_ctx */
 617	out->compressed_buffer_segment_size_in_kbytes = in_ip_params->compressed_buffer_segment_size_in_kbytes;
 618	out->config_return_buffer_size_in_kbytes = in_ip_params->config_return_buffer_size_in_kbytes;
 619	out->cursor_buffer_size = in_ip_params->cursor_buffer_size;
 620	out->cursor_chunk_size = in_ip_params->cursor_chunk_size;
 621	out->dcc_meta_buffer_size_bytes = in_ip_params->dcc_meta_buffer_size_bytes;
 622	out->dcc_supported = in_ip_params->dcc_supported;
 623	out->dispclk_delay_subtotal = in_ip_params->dispclk_delay_subtotal;
 624	out->dispclk_ramp_margin_percent = in_ip_params->dispclk_ramp_margin_percent;
 625	out->dppclk_delay_cnvc_cursor = in_ip_params->dppclk_delay_cnvc_cursor;
 626	out->dppclk_delay_cnvc_formatter = in_ip_params->dppclk_delay_cnvc_formatter;
 627	out->dppclk_delay_scl = in_ip_params->dppclk_delay_scl;
 628	out->dppclk_delay_scl_lb_only = in_ip_params->dppclk_delay_scl_lb_only;
 629	out->dppclk_delay_subtotal = in_ip_params->dppclk_delay_subtotal;
 630	out->dpte_buffer_size_in_pte_reqs_chroma = in_ip_params->dpte_buffer_size_in_pte_reqs_chroma;
 631	out->dpte_buffer_size_in_pte_reqs_luma = in_ip_params->dpte_buffer_size_in_pte_reqs_luma;
 632	out->dsc422_native_support = in_ip_params->dsc422_native_support;
 633	out->dynamic_metadata_vm_enabled = in_ip_params->dynamic_metadata_vm_enabled;
 634	out->gpuvm_enable = in_ip_params->gpuvm_enable;
 635	out->gpuvm_max_page_table_levels = in_ip_params->gpuvm_max_page_table_levels;
 636	out->hostvm_enable = in_ip_params->hostvm_enable;
 637	out->hostvm_max_page_table_levels = in_ip_params->hostvm_max_page_table_levels;
 638	out->line_buffer_size_bits = in_ip_params->line_buffer_size_bits;
 639	out->maximum_dsc_bits_per_component = in_ip_params->maximum_dsc_bits_per_component;
 640	out->maximum_pixels_per_line_per_dsc_unit = in_ip_params->maximum_pixels_per_line_per_dsc_unit;
 641	out->max_dchub_pscl_bw_pix_per_clk = in_ip_params->max_dchub_pscl_bw_pix_per_clk;
 642	out->max_hscl_ratio = in_ip_params->max_hscl_ratio;
 643	out->max_hscl_taps = in_ip_params->max_hscl_taps;
 644	out->max_inter_dcn_tile_repeaters = in_ip_params->max_inter_dcn_tile_repeaters;
 645	out->max_lb_vscl_bw_pix_per_clk = in_ip_params->max_lb_vscl_bw_pix_per_clk;
 646	out->max_line_buffer_lines = in_ip_params->max_line_buffer_lines;
 647	out->max_num_dp2p0_outputs = in_ip_params->max_num_dp2p0_outputs;
 648	out->max_num_dp2p0_streams = in_ip_params->max_num_dp2p0_streams;
 649	out->max_num_dpp = in_ip_params->max_num_dpp;
 650	out->max_num_hdmi_frl_outputs = in_ip_params->max_num_hdmi_frl_outputs;
 651	out->max_num_otg = in_ip_params->max_num_otg;
 652	out->max_num_wb = in_ip_params->max_num_wb;
 653	out->max_pscl_lb_bw_pix_per_clk = in_ip_params->max_pscl_lb_bw_pix_per_clk;
 654	out->max_vscl_hscl_bw_pix_per_clk = in_ip_params->max_vscl_hscl_bw_pix_per_clk;
 655	out->max_vscl_ratio = in_ip_params->max_vscl_ratio;
 656	out->max_vscl_taps = in_ip_params->max_vscl_taps;
 657	out->meta_chunk_size_kbytes = in_ip_params->meta_chunk_size_kbytes;
 658	out->meta_fifo_size_in_kentries = in_ip_params->meta_fifo_size_in_kentries;
 659	out->min_meta_chunk_size_bytes = in_ip_params->min_meta_chunk_size_bytes;
 660	out->min_pixel_chunk_size_bytes = in_ip_params->min_pixel_chunk_size_bytes;
 661	out->num_dsc = in_ip_params->num_dsc;
 662	out->pixel_chunk_size_kbytes = in_ip_params->pixel_chunk_size_kbytes;
 663	out->ptoi_supported = in_ip_params->ptoi_supported;
 664	out->rob_buffer_size_kbytes = in_ip_params->rob_buffer_size_kbytes;
 665	out->writeback_chunk_size_kbytes = in_ip_params->writeback_chunk_size_kbytes;
 666	out->writeback_interface_buffer_size_kbytes = in_ip_params->writeback_interface_buffer_size_kbytes;
 667	out->writeback_line_buffer_buffer_size = in_ip_params->writeback_line_buffer_buffer_size;
 668	out->writeback_max_hscl_ratio = in_ip_params->writeback_max_hscl_ratio;
 669	out->writeback_max_hscl_taps = in_ip_params->writeback_max_hscl_taps;
 670	out->writeback_max_vscl_ratio = in_ip_params->writeback_max_vscl_ratio;
 671	out->writeback_max_vscl_taps = in_ip_params->writeback_max_vscl_taps;
 672	out->writeback_min_hscl_ratio = in_ip_params->writeback_min_hscl_ratio;
 673	out->writeback_min_vscl_ratio = in_ip_params->writeback_min_vscl_ratio;
 674	out->zero_size_buffer_entries = in_ip_params->zero_size_buffer_entries;
 675
 676	/* As per hardcoded reference / discussions */
 677	out->config_return_buffer_segment_size_in_kbytes = 64;
 678	//out->vblank_nom_default_us = 600;
 679	out->vblank_nom_default_us = in_ip_params->VBlankNomDefaultUS;
 680}
 681
 682void dml2_translate_socbb_params(const struct dc *in, struct soc_bounding_box_st *out)
 683{
 684	const struct _vcs_dpi_soc_bounding_box_st *in_soc_params = &in->dml.soc;
 685	/* Copy over the SOCBB params to dml2_ctx */
 686	out->dispclk_dppclk_vco_speed_mhz = in_soc_params->dispclk_dppclk_vco_speed_mhz;
 687	out->do_urgent_latency_adjustment = in_soc_params->do_urgent_latency_adjustment;
 688	out->dram_channel_width_bytes = (dml_uint_t)in_soc_params->dram_channel_width_bytes;
 689	out->fabric_datapath_to_dcn_data_return_bytes = (dml_uint_t)in_soc_params->fabric_datapath_to_dcn_data_return_bytes;
 690	out->gpuvm_min_page_size_kbytes = in_soc_params->gpuvm_min_page_size_bytes / 1024;
 691	out->hostvm_min_page_size_kbytes = in_soc_params->hostvm_min_page_size_bytes / 1024;
 692	out->mall_allocated_for_dcn_mbytes = (dml_uint_t)in_soc_params->mall_allocated_for_dcn_mbytes;
 693	out->max_avg_dram_bw_use_normal_percent = in_soc_params->max_avg_dram_bw_use_normal_percent;
 694	out->max_avg_fabric_bw_use_normal_percent = in_soc_params->max_avg_fabric_bw_use_normal_percent;
 695	out->max_avg_dram_bw_use_normal_strobe_percent = in_soc_params->max_avg_dram_bw_use_normal_strobe_percent;
 696	out->max_avg_sdp_bw_use_normal_percent = in_soc_params->max_avg_sdp_bw_use_normal_percent;
 697	out->max_outstanding_reqs = in_soc_params->max_request_size_bytes;
 698	out->num_chans = in_soc_params->num_chans;
 699	out->pct_ideal_dram_bw_after_urgent_strobe = in_soc_params->pct_ideal_dram_bw_after_urgent_strobe;
 700	out->pct_ideal_dram_bw_after_urgent_vm_only = in_soc_params->pct_ideal_dram_sdp_bw_after_urgent_vm_only;
 701	out->pct_ideal_fabric_bw_after_urgent = in_soc_params->pct_ideal_fabric_bw_after_urgent;
 702	out->pct_ideal_sdp_bw_after_urgent = in_soc_params->pct_ideal_sdp_bw_after_urgent;
 703	out->phy_downspread_percent = in_soc_params->downspread_percent;
 704	out->refclk_mhz = 50; // As per hardcoded reference.
 705	out->return_bus_width_bytes = in_soc_params->return_bus_width_bytes;
 706	out->round_trip_ping_latency_dcfclk_cycles = in_soc_params->round_trip_ping_latency_dcfclk_cycles;
 707	out->smn_latency_us = in_soc_params->smn_latency_us;
 708	out->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = in_soc_params->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
 709	out->urgent_out_of_order_return_per_channel_pixel_only_bytes = in_soc_params->urgent_out_of_order_return_per_channel_pixel_only_bytes;
 710	out->urgent_out_of_order_return_per_channel_vm_only_bytes = in_soc_params->urgent_out_of_order_return_per_channel_vm_only_bytes;
 711	out->pct_ideal_dram_bw_after_urgent_pixel_and_vm = in_soc_params->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
 712	out->pct_ideal_dram_bw_after_urgent_pixel_only = in_soc_params->pct_ideal_dram_sdp_bw_after_urgent_pixel_only;
 713	out->dcn_downspread_percent = in_soc_params->dcn_downspread_percent;
 714}
 715
 716void dml2_translate_soc_states(const struct dc *dc, struct soc_states_st *out, int num_states)
 717{
 718	unsigned int i = 0;
 719	out->num_states = num_states;
 720
 721	for (i = 0; i < out->num_states; i++) {
 722		out->state_array[i].dcfclk_mhz = dc->dml.soc.clock_limits[i].dcfclk_mhz;
 723		out->state_array[i].dispclk_mhz = dc->dml.soc.clock_limits[i].dispclk_mhz;
 724		out->state_array[i].dppclk_mhz = dc->dml.soc.clock_limits[i].dppclk_mhz;
 725		out->state_array[i].dram_speed_mts = dc->dml.soc.clock_limits[i].dram_speed_mts;
 726		out->state_array[i].dtbclk_mhz = dc->dml.soc.clock_limits[i].dtbclk_mhz;
 727		out->state_array[i].socclk_mhz = dc->dml.soc.clock_limits[i].socclk_mhz;
 728		out->state_array[i].fabricclk_mhz = dc->dml.soc.clock_limits[i].fabricclk_mhz;
 729		out->state_array[i].dscclk_mhz = dc->dml.soc.clock_limits[i].dscclk_mhz;
 730		out->state_array[i].phyclk_d18_mhz = dc->dml.soc.clock_limits[i].phyclk_d18_mhz;
 731		out->state_array[i].phyclk_d32_mhz = dc->dml.soc.clock_limits[i].phyclk_d32_mhz;
 732		out->state_array[i].phyclk_mhz = dc->dml.soc.clock_limits[i].phyclk_mhz;
 733		out->state_array[i].sr_enter_plus_exit_time_us = dc->dml.soc.sr_enter_plus_exit_time_us;
 734		out->state_array[i].sr_exit_time_us = dc->dml.soc.sr_exit_time_us;
 735		out->state_array[i].fclk_change_latency_us = dc->dml.soc.fclk_change_latency_us;
 736		out->state_array[i].dram_clock_change_latency_us = dc->dml.soc.dram_clock_change_latency_us;
 737		out->state_array[i].usr_retraining_latency_us = dc->dml.soc.usr_retraining_latency_us;
 738		out->state_array[i].writeback_latency_us = dc->dml.soc.writeback_latency_us;
 739		/* Driver initialized values for these are different than the spreadsheet. Use the
 740		 * spreadsheet ones for now. We need to decided which ones to use.
 741		 */
 742		out->state_array[i].sr_exit_z8_time_us = dc->dml.soc.sr_exit_z8_time_us;
 743		out->state_array[i].sr_enter_plus_exit_z8_time_us = dc->dml.soc.sr_enter_plus_exit_z8_time_us;
 744		//out->state_array[i].sr_exit_z8_time_us = 5.20;
 745		//out->state_array[i].sr_enter_plus_exit_z8_time_us = 9.60;
 746		out->state_array[i].use_ideal_dram_bw_strobe = true;
 747		out->state_array[i].urgent_latency_pixel_data_only_us = dc->dml.soc.urgent_latency_pixel_data_only_us;
 748		out->state_array[i].urgent_latency_pixel_mixed_with_vm_data_us = dc->dml.soc.urgent_latency_pixel_mixed_with_vm_data_us;
 749		out->state_array[i].urgent_latency_vm_data_only_us = dc->dml.soc.urgent_latency_vm_data_only_us;
 750		out->state_array[i].urgent_latency_adjustment_fabric_clock_component_us = dc->dml.soc.urgent_latency_adjustment_fabric_clock_component_us;
 751		out->state_array[i].urgent_latency_adjustment_fabric_clock_reference_mhz = dc->dml.soc.urgent_latency_adjustment_fabric_clock_reference_mhz;
 752	}
 753}
 754
 755static void populate_dml_timing_cfg_from_stream_state(struct dml_timing_cfg_st *out, unsigned int location, const struct dc_stream_state *in)
 756{
 757	dml_uint_t hblank_start, vblank_start;
 758
 759	out->HActive[location] = in->timing.h_addressable + in->timing.h_border_left + in->timing.h_border_right;
 760	out->VActive[location] = in->timing.v_addressable + in->timing.v_border_bottom + in->timing.v_border_top;
 761	out->RefreshRate[location] = ((in->timing.pix_clk_100hz * 100) / in->timing.h_total) / in->timing.v_total;
 762	out->VFrontPorch[location] = in->timing.v_front_porch;
 763	out->PixelClock[location] = in->timing.pix_clk_100hz / 10000.00;
 764	if (in->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
 765		out->PixelClock[location] *= 2;
 766	out->HTotal[location] = in->timing.h_total;
 767	out->VTotal[location] = in->timing.v_total;
 768	out->Interlace[location] = in->timing.flags.INTERLACE;
 769	hblank_start = in->timing.h_total - in->timing.h_front_porch;
 770	out->HBlankEnd[location] = hblank_start
 771					- in->timing.h_addressable
 772					- in->timing.h_border_left
 773					- in->timing.h_border_right;
 774	vblank_start = in->timing.v_total - in->timing.v_front_porch;
 775	out->VBlankEnd[location] = vblank_start
 776					- in->timing.v_addressable
 777					- in->timing.v_border_top
 778					- in->timing.v_border_bottom;
 779	out->DRRDisplay[location] = false;
 780}
 781
 782static void populate_dml_output_cfg_from_stream_state(struct dml_output_cfg_st *out, unsigned int location,
 783				const struct dc_stream_state *in, const struct pipe_ctx *pipe, struct dml2_context *dml2)
 784{
 785	unsigned int output_bpc;
 786
 787	out->DSCEnable[location] = (enum dml_dsc_enable)in->timing.flags.DSC;
 788	out->OutputLinkDPLanes[location] = 4; // As per code in dcn20_resource.c
 789	out->DSCInputBitPerComponent[location] = 12; // As per code in dcn20_resource.c
 790	out->DSCSlices[location] = in->timing.dsc_cfg.num_slices_h;
 791
 792	switch (in->signal) {
 793	case SIGNAL_TYPE_DISPLAY_PORT_MST:
 794	case SIGNAL_TYPE_DISPLAY_PORT:
 795		out->OutputEncoder[location] = dml_dp;
 796		if (location < MAX_HPO_DP2_ENCODERS && dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location] != -1)
 797			out->OutputEncoder[dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location]] = dml_dp2p0;
 798		break;
 799	case SIGNAL_TYPE_EDP:
 800		out->OutputEncoder[location] = dml_edp;
 801		break;
 802	case SIGNAL_TYPE_HDMI_TYPE_A:
 803	case SIGNAL_TYPE_DVI_SINGLE_LINK:
 804	case SIGNAL_TYPE_DVI_DUAL_LINK:
 805		out->OutputEncoder[location] = dml_hdmi;
 806		break;
 807	default:
 808		out->OutputEncoder[location] = dml_dp;
 809	}
 810
 811	switch (in->timing.display_color_depth) {
 812	case COLOR_DEPTH_666:
 813		output_bpc = 6;
 814		break;
 815	case COLOR_DEPTH_888:
 816		output_bpc = 8;
 817		break;
 818	case COLOR_DEPTH_101010:
 819		output_bpc = 10;
 820		break;
 821	case COLOR_DEPTH_121212:
 822		output_bpc = 12;
 823		break;
 824	case COLOR_DEPTH_141414:
 825		output_bpc = 14;
 826		break;
 827	case COLOR_DEPTH_161616:
 828		output_bpc = 16;
 829		break;
 830	case COLOR_DEPTH_999:
 831		output_bpc = 9;
 832		break;
 833	case COLOR_DEPTH_111111:
 834		output_bpc = 11;
 835		break;
 836	default:
 837		output_bpc = 8;
 838		break;
 839	}
 840
 841	switch (in->timing.pixel_encoding) {
 842	case PIXEL_ENCODING_RGB:
 843	case PIXEL_ENCODING_YCBCR444:
 844		out->OutputFormat[location] = dml_444;
 845		out->OutputBpp[location] = (dml_float_t)output_bpc * 3;
 846		break;
 847	case PIXEL_ENCODING_YCBCR420:
 848		out->OutputFormat[location] = dml_420;
 849		out->OutputBpp[location] = (output_bpc * 3.0) / 2;
 850		break;
 851	case PIXEL_ENCODING_YCBCR422:
 852		if (in->timing.flags.DSC && !in->timing.dsc_cfg.ycbcr422_simple)
 853			out->OutputFormat[location] = dml_n422;
 854		else
 855			out->OutputFormat[location] = dml_s422;
 856		out->OutputBpp[location] = (dml_float_t)output_bpc * 2;
 857		break;
 858	default:
 859		out->OutputFormat[location] = dml_444;
 860		out->OutputBpp[location] = (dml_float_t)output_bpc * 3;
 861		break;
 862	}
 863
 864	if (in->timing.flags.DSC) {
 865		out->OutputBpp[location] = in->timing.dsc_cfg.bits_per_pixel / 16.0;
 866	}
 867
 868	// This has been false throughout DCN32x development. If needed we can change this later on.
 869	out->OutputMultistreamEn[location] = false;
 870
 871	switch (in->signal) {
 872	case SIGNAL_TYPE_NONE:
 873	case SIGNAL_TYPE_DVI_SINGLE_LINK:
 874	case SIGNAL_TYPE_DVI_DUAL_LINK:
 875	case SIGNAL_TYPE_HDMI_TYPE_A:
 876	case SIGNAL_TYPE_LVDS:
 877	case SIGNAL_TYPE_RGB:
 878	case SIGNAL_TYPE_DISPLAY_PORT:
 879	case SIGNAL_TYPE_DISPLAY_PORT_MST:
 880	case SIGNAL_TYPE_EDP:
 881	case SIGNAL_TYPE_VIRTUAL:
 882	default:
 883		out->OutputLinkDPRate[location] = dml_dp_rate_na;
 884		break;
 885	}
 886
 887	out->PixelClockBackEnd[location] = in->timing.pix_clk_100hz / 10000.00;
 888
 889	out->AudioSampleLayout[location] = in->audio_info.modes->sample_size;
 890	out->AudioSampleRate[location] = in->audio_info.modes->max_bit_rate;
 891
 892	out->OutputDisabled[location] = true;
 893}
 894
 895static void populate_dummy_dml_surface_cfg(struct dml_surface_cfg_st *out, unsigned int location, const struct dc_stream_state *in)
 896{
 897	out->SurfaceWidthY[location] = in->timing.h_addressable;
 898	out->SurfaceHeightY[location] = in->timing.v_addressable;
 899	out->SurfaceWidthC[location] = in->timing.h_addressable;
 900	out->SurfaceHeightC[location] = in->timing.v_addressable;
 901	out->PitchY[location] = ((out->SurfaceWidthY[location] + 127) / 128) * 128;
 902	out->PitchC[location] = 1;
 903	out->DCCEnable[location] = false;
 904	out->DCCMetaPitchY[location] = 0;
 905	out->DCCMetaPitchC[location] = 0;
 906	out->DCCRateLuma[location] = 1.0;
 907	out->DCCRateChroma[location] = 1.0;
 908	out->DCCFractionOfZeroSizeRequestsLuma[location] = 0;
 909	out->DCCFractionOfZeroSizeRequestsChroma[location] = 0;
 910	out->SurfaceTiling[location] = dml_sw_64kb_r_x;
 911	out->SourcePixelFormat[location] = dml_444_32;
 912}
 913
 914static void populate_dml_surface_cfg_from_plane_state(enum dml_project_id dml2_project, struct dml_surface_cfg_st *out, unsigned int location, const struct dc_plane_state *in)
 915{
 916	out->PitchY[location] = in->plane_size.surface_pitch;
 917	out->SurfaceHeightY[location] = in->plane_size.surface_size.height;
 918	out->SurfaceWidthY[location] = in->plane_size.surface_size.width;
 919	out->SurfaceHeightC[location] = in->plane_size.chroma_size.height;
 920	out->SurfaceWidthC[location] = in->plane_size.chroma_size.width;
 921	out->PitchC[location] = in->plane_size.chroma_pitch;
 922	out->DCCEnable[location] = in->dcc.enable;
 923	out->DCCMetaPitchY[location] = in->dcc.meta_pitch;
 924	out->DCCMetaPitchC[location] = in->dcc.meta_pitch_c;
 925	out->DCCRateLuma[location] = 1.0;
 926	out->DCCRateChroma[location] = 1.0;
 927	out->DCCFractionOfZeroSizeRequestsLuma[location] = in->dcc.independent_64b_blks;
 928	out->DCCFractionOfZeroSizeRequestsChroma[location] = in->dcc.independent_64b_blks_c;
 929
 930	switch (dml2_project) {
 931	default:
 932		out->SurfaceTiling[location] = (enum dml_swizzle_mode)in->tiling_info.gfx9.swizzle;
 933		break;
 934	case dml_project_dcn401:
 935		// Temporary use gfx11 swizzle in dml, until proper dml for DCN4x is integrated/implemented
 936		switch (in->tiling_info.gfx_addr3.swizzle) {
 937		case DC_ADDR3_SW_4KB_2D:
 938		case DC_ADDR3_SW_64KB_2D:
 939		case DC_ADDR3_SW_256KB_2D:
 940		default:
 941			out->SurfaceTiling[location] = dml_sw_64kb_r_x;
 942			break;
 943		case DC_ADDR3_SW_LINEAR:
 944			out->SurfaceTiling[location] = dml_sw_linear;
 945			break;
 946		}
 947	}
 948
 949	switch (in->format) {
 950	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 951	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
 952		out->SourcePixelFormat[location] = dml_420_8;
 953		break;
 954	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
 955	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
 956		out->SourcePixelFormat[location] = dml_420_10;
 957		break;
 958	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 959	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
 960	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 961	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 962		out->SourcePixelFormat[location] = dml_444_64;
 963		break;
 964	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
 965	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 966		out->SourcePixelFormat[location] = dml_444_16;
 967		break;
 968	case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
 969		out->SourcePixelFormat[location] = dml_444_8;
 970		break;
 971	case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
 972		out->SourcePixelFormat[location] = dml_rgbe_alpha;
 973		break;
 974	default:
 975		out->SourcePixelFormat[location] = dml_444_32;
 976		break;
 977	}
 978}
 979
 980static struct scaler_data *get_scaler_data_for_plane(
 981		const struct dc_plane_state *in,
 982		struct dc_state *context)
 983{
 984	int i;
 985	struct pipe_ctx *temp_pipe = &context->res_ctx.temp_pipe;
 986
 987	memset(temp_pipe, 0, sizeof(struct pipe_ctx));
 988
 989	for (i = 0; i < MAX_PIPES; i++)	{
 990		const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 991
 992		if (pipe->plane_state == in && !pipe->prev_odm_pipe) {
 993			temp_pipe->stream = pipe->stream;
 994			temp_pipe->plane_state = pipe->plane_state;
 995			temp_pipe->plane_res.scl_data.taps = pipe->plane_res.scl_data.taps;
 996			temp_pipe->stream_res = pipe->stream_res;
 997			resource_build_scaling_params(temp_pipe);
 998			break;
 999		}
1000	}
1001
1002	ASSERT(i < MAX_PIPES);
1003	return &temp_pipe->plane_res.scl_data;
1004}
1005
1006static void populate_dummy_dml_plane_cfg(struct dml_plane_cfg_st *out, unsigned int location,
1007					 const struct dc_stream_state *in,
1008					 const struct soc_bounding_box_st *soc)
1009{
1010	dml_uint_t width, height;
1011
1012	if (in->timing.h_addressable > 3840)
1013		width = 3840;
1014	else
1015		width = in->timing.h_addressable;	// 4K max
1016
1017	if (in->timing.v_addressable > 2160)
1018		height = 2160;
1019	else
1020		height = in->timing.v_addressable;	// 4K max
1021
1022	out->CursorBPP[location] = dml_cur_32bit;
1023	out->CursorWidth[location] = 256;
1024
1025	out->GPUVMMinPageSizeKBytes[location] = soc->gpuvm_min_page_size_kbytes;
1026
1027	out->ViewportWidth[location] = width;
1028	out->ViewportHeight[location] = height;
1029	out->ViewportStationary[location] = false;
1030	out->ViewportWidthChroma[location] = 0;
1031	out->ViewportHeightChroma[location] = 0;
1032	out->ViewportXStart[location] = 0;
1033	out->ViewportXStartC[location] = 0;
1034	out->ViewportYStart[location] = 0;
1035	out->ViewportYStartC[location] = 0;
1036
1037	out->ScalerEnabled[location] = false;
1038	out->HRatio[location] = 1.0;
1039	out->VRatio[location] = 1.0;
1040	out->HRatioChroma[location] = 0;
1041	out->VRatioChroma[location] = 0;
1042	out->HTaps[location] = 1;
1043	out->VTaps[location] = 1;
1044	out->HTapsChroma[location] = 0;
1045	out->VTapsChroma[location] = 0;
1046	out->SourceScan[location] = dml_rotation_0;
1047	out->ScalerRecoutWidth[location] = width;
1048
1049	out->LBBitPerPixel[location] = 57;
1050
1051	out->DynamicMetadataEnable[location] = false;
1052
1053	out->NumberOfCursors[location] = 1;
1054	out->UseMALLForStaticScreen[location] = dml_use_mall_static_screen_disable;
1055	out->UseMALLForPStateChange[location] = dml_use_mall_pstate_change_disable;
1056
1057	out->DETSizeOverride[location] = 256;
1058
1059	out->ScalerEnabled[location] = false;
1060}
1061
1062static void populate_dml_plane_cfg_from_plane_state(struct dml_plane_cfg_st *out, unsigned int location,
1063						    const struct dc_plane_state *in, struct dc_state *context,
1064						    const struct soc_bounding_box_st *soc)
1065{
1066	struct scaler_data *scaler_data = get_scaler_data_for_plane(in, context);
1067
1068	out->CursorBPP[location] = dml_cur_32bit;
1069	out->CursorWidth[location] = 256;
1070
1071	out->GPUVMMinPageSizeKBytes[location] = soc->gpuvm_min_page_size_kbytes;
1072
1073	out->ViewportWidth[location] = scaler_data->viewport.width;
1074	out->ViewportHeight[location] = scaler_data->viewport.height;
1075	out->ViewportWidthChroma[location] = scaler_data->viewport_c.width;
1076	out->ViewportHeightChroma[location] = scaler_data->viewport_c.height;
1077	out->ViewportXStart[location] = scaler_data->viewport.x;
1078	out->ViewportYStart[location] = scaler_data->viewport.y;
1079	out->ViewportXStartC[location] = scaler_data->viewport_c.x;
1080	out->ViewportYStartC[location] = scaler_data->viewport_c.y;
1081	out->ViewportStationary[location] = false;
1082
1083	out->ScalerEnabled[location] = scaler_data->ratios.horz.value != dc_fixpt_one.value ||
1084				scaler_data->ratios.horz_c.value != dc_fixpt_one.value ||
1085				scaler_data->ratios.vert.value != dc_fixpt_one.value ||
1086				scaler_data->ratios.vert_c.value != dc_fixpt_one.value;
1087
1088	/* Current driver code base uses LBBitPerPixel as 57. There is a discrepancy
1089	 * from the HW/DML teams about this value. Initialize LBBitPerPixel with the
1090	 * value current used in Navi3x .
1091	 */
1092
1093	out->LBBitPerPixel[location] = 57;
1094
1095	if (out->ScalerEnabled[location] == false) {
1096		out->HRatio[location] = 1;
1097		out->HRatioChroma[location] = 1;
1098		out->VRatio[location] = 1;
1099		out->VRatioChroma[location] = 1;
1100	} else {
1101		/* Follow the original dml_wrapper.c code direction to fix scaling issues */
1102		out->HRatio[location] = (dml_float_t)scaler_data->ratios.horz.value / (1ULL << 32);
1103		out->HRatioChroma[location] = (dml_float_t)scaler_data->ratios.horz_c.value / (1ULL << 32);
1104		out->VRatio[location] = (dml_float_t)scaler_data->ratios.vert.value / (1ULL << 32);
1105		out->VRatioChroma[location] = (dml_float_t)scaler_data->ratios.vert_c.value / (1ULL << 32);
1106	}
1107
1108	if (!scaler_data->taps.h_taps) {
1109		out->HTaps[location] = 1;
1110		out->HTapsChroma[location] = 1;
1111	} else {
1112		out->HTaps[location] = scaler_data->taps.h_taps;
1113		out->HTapsChroma[location] = scaler_data->taps.h_taps_c;
1114	}
1115	if (!scaler_data->taps.v_taps) {
1116		out->VTaps[location] = 1;
1117		out->VTapsChroma[location] = 1;
1118	} else {
1119		out->VTaps[location] = scaler_data->taps.v_taps;
1120		out->VTapsChroma[location] = scaler_data->taps.v_taps_c;
1121	}
1122
1123	out->SourceScan[location] = (enum dml_rotation_angle)in->rotation;
1124	out->ScalerRecoutWidth[location] = in->dst_rect.width;
1125
1126	out->DynamicMetadataEnable[location] = false;
1127	out->DynamicMetadataLinesBeforeActiveRequired[location] = 0;
1128	out->DynamicMetadataTransmittedBytes[location] = 0;
1129
1130	out->NumberOfCursors[location] = 1;
1131}
1132
1133static unsigned int map_stream_to_dml_display_cfg(const struct dml2_context *dml2,
1134		const struct dc_stream_state *stream, const struct dml_display_cfg_st *dml_dispcfg)
1135{
1136	int i = 0;
1137	int location = -1;
1138
1139	for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {
1140		if (dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[i] && dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[i] == stream->stream_id) {
1141			location = i;
1142			break;
1143		}
1144	}
1145
1146	return location;
1147}
1148
1149static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *context, const struct dc_plane_state *plane,
1150		unsigned int stream_id, unsigned int plane_index, unsigned int *plane_id)
1151{
1152	int i, j;
1153	bool is_plane_duplicate = dml2->v20.scratch.plane_duplicate_exists;
1154
1155	if (!plane_id)
1156		return false;
1157
1158	for (i = 0; i < context->stream_count; i++) {
1159		if (context->streams[i]->stream_id == stream_id) {
1160			for (j = 0; j < context->stream_status[i].plane_count; j++) {
1161				if (context->stream_status[i].plane_states[j] == plane &&
1162					(!is_plane_duplicate || (j == plane_index))) {
1163					*plane_id = (i << 16) | j;
1164					return true;
1165				}
1166			}
1167		}
1168	}
1169
1170	return false;
1171}
1172
1173static unsigned int map_plane_to_dml_display_cfg(const struct dml2_context *dml2, const struct dc_plane_state *plane,
1174		const struct dc_state *context, const struct dml_display_cfg_st *dml_dispcfg, unsigned int stream_id, int plane_index)
1175{
1176	unsigned int plane_id;
1177	int i = 0;
1178	int location = -1;
1179
1180	if (!get_plane_id(context->bw_ctx.dml2, context, plane, stream_id, plane_index, &plane_id)) {
1181		ASSERT(false);
1182		return -1;
1183	}
1184
1185	for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {
1186		if (dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[i] && dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[i] == plane_id) {
1187			location = i;
1188			break;
1189		}
1190	}
1191
1192	return location;
1193}
1194
1195static void dml2_populate_pipe_to_plane_index_mapping(struct dml2_context *dml2, struct dc_state *state)
1196{
1197	unsigned int i;
1198	unsigned int pipe_index = 0;
1199	unsigned int plane_index = 0;
1200	struct dml2_dml_to_dc_pipe_mapping *dml_to_dc_pipe_mapping = &dml2->v20.scratch.dml_to_dc_pipe_mapping;
1201
1202	for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {
1203		dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid[i] = false;
1204		dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index[i] = 0;
1205	}
1206
1207	for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {
1208		struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];
1209
1210		if (!pipe || !pipe->stream || !pipe->plane_state)
1211			continue;
1212
1213		while (pipe) {
1214			pipe_index = pipe->pipe_idx;
1215
1216			if (pipe->stream && dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid[pipe_index] == false) {
1217				dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index[pipe_index] = plane_index;
1218				plane_index++;
1219				dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid[pipe_index] = true;
1220			}
1221
1222			pipe = pipe->bottom_pipe;
1223		}
1224
1225		plane_index = 0;
1226	}
1227}
1228
1229static void populate_dml_writeback_cfg_from_stream_state(struct dml_writeback_cfg_st *out,
1230		unsigned int location, const struct dc_stream_state *in)
1231{
1232	if (in->num_wb_info > 0) {
1233		for (int i = 0; i < __DML_NUM_DMB__; i++) {
1234			const struct dc_writeback_info *wb_info = &in->writeback_info[i];
1235			/*current dml support 1 dwb per stream, limitation*/
1236			if (wb_info->wb_enabled) {
1237				out->WritebackEnable[location] = wb_info->wb_enabled;
1238				out->ActiveWritebacksPerSurface[location] = wb_info->dwb_params.cnv_params.src_width;
1239				out->WritebackDestinationWidth[location] = wb_info->dwb_params.dest_width;
1240				out->WritebackDestinationHeight[location] = wb_info->dwb_params.dest_height;
1241
1242				out->WritebackSourceWidth[location] = wb_info->dwb_params.cnv_params.crop_en ?
1243					wb_info->dwb_params.cnv_params.crop_width :
1244					wb_info->dwb_params.cnv_params.src_width;
1245
1246				out->WritebackSourceHeight[location] = wb_info->dwb_params.cnv_params.crop_en ?
1247					wb_info->dwb_params.cnv_params.crop_height :
1248					wb_info->dwb_params.cnv_params.src_height;
1249				/*current design does not have chroma scaling, need to follow up*/
1250				out->WritebackHTaps[location] = wb_info->dwb_params.scaler_taps.h_taps > 0 ?
1251					wb_info->dwb_params.scaler_taps.h_taps : 1;
1252				out->WritebackVTaps[location] = wb_info->dwb_params.scaler_taps.v_taps > 0 ?
1253					wb_info->dwb_params.scaler_taps.v_taps : 1;
1254
1255				out->WritebackHRatio[location] = wb_info->dwb_params.cnv_params.crop_en ?
1256					(double)wb_info->dwb_params.cnv_params.crop_width /
1257						(double)wb_info->dwb_params.dest_width :
1258					(double)wb_info->dwb_params.cnv_params.src_width /
1259						(double)wb_info->dwb_params.dest_width;
1260				out->WritebackVRatio[location] = wb_info->dwb_params.cnv_params.crop_en ?
1261					(double)wb_info->dwb_params.cnv_params.crop_height /
1262						(double)wb_info->dwb_params.dest_height :
1263					(double)wb_info->dwb_params.cnv_params.src_height /
1264						(double)wb_info->dwb_params.dest_height;
1265			}
1266		}
1267	}
1268}
1269
1270static void dml2_map_hpo_stream_encoder_to_hpo_link_encoder_index(struct dml2_context *dml2, struct dc_state *context)
1271{
1272	int i;
1273	struct pipe_ctx *current_pipe_context;
1274
1275	/* Scratch gets reset to zero in dml, but link encoder instance can be zero, so reset to -1 */
1276	for (i = 0; i < MAX_HPO_DP2_ENCODERS; i++) {
1277		dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[i] = -1;
1278	}
1279
1280	/* If an HPO stream encoder is allocated to a pipe, get the instance of it's allocated HPO Link encoder */
1281	for (i = 0; i < MAX_PIPES; i++) {
1282		current_pipe_context = &context->res_ctx.pipe_ctx[i];
1283		if (current_pipe_context->stream &&
1284			current_pipe_context->stream_res.hpo_dp_stream_enc &&
1285			current_pipe_context->link_res.hpo_dp_link_enc &&
1286			dc_is_dp_signal(current_pipe_context->stream->signal)) {
1287				dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[current_pipe_context->stream_res.hpo_dp_stream_enc->inst] =
1288					current_pipe_context->link_res.hpo_dp_link_enc->inst;
1289			}
1290	}
1291}
1292
1293void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_state *context, struct dml_display_cfg_st *dml_dispcfg)
1294{
1295	int i = 0, j = 0, k = 0;
1296	int disp_cfg_stream_location, disp_cfg_plane_location;
1297	enum mall_stream_type stream_mall_type;
1298	struct pipe_ctx *current_pipe_context;
1299
1300	for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {
1301		dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[i] = false;
1302		dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[i] = false;
1303		dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[i] = false;
1304		dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[i] = false;
1305	}
1306
1307	//Generally these are set by referencing our latest BB/IP params in dcn32_resource.c file
1308	dml_dispcfg->plane.GPUVMEnable = dml2->v20.dml_core_ctx.ip.gpuvm_enable;
1309	dml_dispcfg->plane.GPUVMMaxPageTableLevels = dml2->v20.dml_core_ctx.ip.gpuvm_max_page_table_levels;
1310	dml_dispcfg->plane.HostVMEnable = dml2->v20.dml_core_ctx.ip.hostvm_enable;
1311	dml_dispcfg->plane.HostVMMaxPageTableLevels = dml2->v20.dml_core_ctx.ip.hostvm_max_page_table_levels;
1312	if (dml2->v20.dml_core_ctx.ip.hostvm_enable)
1313		dml2->v20.dml_core_ctx.policy.AllowForPStateChangeOrStutterInVBlankFinal = dml_prefetch_support_uclk_fclk_and_stutter;
1314
1315	dml2_populate_pipe_to_plane_index_mapping(dml2, context);
1316	dml2_map_hpo_stream_encoder_to_hpo_link_encoder_index(dml2, context);
1317
1318	for (i = 0; i < context->stream_count; i++) {
1319		current_pipe_context = NULL;
1320		for (k = 0; k < MAX_PIPES; k++) {
1321			/* find one pipe allocated to this stream for the purpose of getting
1322			info about the link later */
1323			if (context->streams[i] == context->res_ctx.pipe_ctx[k].stream) {
1324				current_pipe_context = &context->res_ctx.pipe_ctx[k];
1325				break;
1326			}
1327		}
1328		disp_cfg_stream_location = map_stream_to_dml_display_cfg(dml2, context->streams[i], dml_dispcfg);
1329		stream_mall_type = dc_state_get_stream_subvp_type(context, context->streams[i]);
1330
1331		if (disp_cfg_stream_location < 0)
1332			disp_cfg_stream_location = dml_dispcfg->num_timings++;
1333
1334		ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__);
1335
1336		populate_dml_timing_cfg_from_stream_state(&dml_dispcfg->timing, disp_cfg_stream_location, context->streams[i]);
1337		populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output, disp_cfg_stream_location, context->streams[i], current_pipe_context, dml2);
1338		/*Call site for populate_dml_writeback_cfg_from_stream_state*/
1339		populate_dml_writeback_cfg_from_stream_state(&dml_dispcfg->writeback,
1340			disp_cfg_stream_location, context->streams[i]);
1341
1342		switch (context->streams[i]->debug.force_odm_combine_segments) {
1343		case 2:
1344			dml2->v20.dml_core_ctx.policy.ODMUse[disp_cfg_stream_location] = dml_odm_use_policy_combine_2to1;
1345			break;
1346		case 4:
1347			dml2->v20.dml_core_ctx.policy.ODMUse[disp_cfg_stream_location] = dml_odm_use_policy_combine_4to1;
1348			break;
1349		default:
1350			break;
1351		}
1352
1353		dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[disp_cfg_stream_location] = context->streams[i]->stream_id;
1354		dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[disp_cfg_stream_location] = true;
1355
1356		if (context->stream_status[i].plane_count == 0) {
1357			disp_cfg_plane_location = dml_dispcfg->num_surfaces++;
1358
1359			populate_dummy_dml_surface_cfg(&dml_dispcfg->surface, disp_cfg_plane_location, context->streams[i]);
1360			populate_dummy_dml_plane_cfg(&dml_dispcfg->plane, disp_cfg_plane_location,
1361						     context->streams[i], &dml2->v20.dml_core_ctx.soc);
1362
1363			dml_dispcfg->plane.BlendingAndTiming[disp_cfg_plane_location] = disp_cfg_stream_location;
1364
1365			dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[disp_cfg_plane_location] = true;
1366		} else {
1367			for (j = 0; j < context->stream_status[i].plane_count; j++) {
1368				disp_cfg_plane_location = map_plane_to_dml_display_cfg(dml2,
1369					context->stream_status[i].plane_states[j], context, dml_dispcfg, context->streams[i]->stream_id, j);
1370
1371				if (disp_cfg_plane_location < 0)
1372					disp_cfg_plane_location = dml_dispcfg->num_surfaces++;
1373
1374				ASSERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__);
1375
1376				populate_dml_surface_cfg_from_plane_state(dml2->v20.dml_core_ctx.project, &dml_dispcfg->surface, disp_cfg_plane_location, context->stream_status[i].plane_states[j]);
1377				populate_dml_plane_cfg_from_plane_state(
1378					&dml_dispcfg->plane, disp_cfg_plane_location,
1379					context->stream_status[i].plane_states[j], context,
1380					&dml2->v20.dml_core_ctx.soc);
1381
1382				if (stream_mall_type == SUBVP_MAIN) {
1383					dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_sub_viewport;
1384					dml_dispcfg->plane.UseMALLForStaticScreen[disp_cfg_plane_location] = dml_use_mall_static_screen_optimize;
1385				} else if (stream_mall_type == SUBVP_PHANTOM) {
1386					dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_phantom_pipe;
1387					dml_dispcfg->plane.UseMALLForStaticScreen[disp_cfg_plane_location] = dml_use_mall_static_screen_disable;
1388					dml2->v20.dml_core_ctx.policy.ImmediateFlipRequirement[disp_cfg_plane_location] = dml_immediate_flip_not_required;
1389				} else {
1390					dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_disable;
1391					dml_dispcfg->plane.UseMALLForStaticScreen[disp_cfg_plane_location] = dml_use_mall_static_screen_optimize;
1392				}
1393
1394				dml_dispcfg->plane.BlendingAndTiming[disp_cfg_plane_location] = disp_cfg_stream_location;
1395
1396				if (get_plane_id(dml2, context, context->stream_status[i].plane_states[j], context->streams[i]->stream_id, j,
1397					&dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[disp_cfg_plane_location]))
1398					dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[disp_cfg_plane_location] = true;
1399
1400				if (j >= 1) {
1401					populate_dml_timing_cfg_from_stream_state(&dml_dispcfg->timing, disp_cfg_plane_location, context->streams[i]);
1402					populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output, disp_cfg_plane_location, context->streams[i], current_pipe_context, dml2);
1403					switch (context->streams[i]->debug.force_odm_combine_segments) {
1404					case 2:
1405						dml2->v20.dml_core_ctx.policy.ODMUse[disp_cfg_plane_location] = dml_odm_use_policy_combine_2to1;
1406						break;
1407					case 4:
1408						dml2->v20.dml_core_ctx.policy.ODMUse[disp_cfg_plane_location] = dml_odm_use_policy_combine_4to1;
1409						break;
1410					default:
1411						break;
1412					}
1413
1414					if (stream_mall_type == SUBVP_MAIN)
1415						dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_sub_viewport;
1416					else if (stream_mall_type == SUBVP_PHANTOM)
1417						dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_phantom_pipe;
1418
1419					dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[disp_cfg_plane_location] = context->streams[i]->stream_id;
1420					dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[disp_cfg_plane_location] = true;
1421
1422					dml_dispcfg->num_timings++;
1423				}
1424			}
1425		}
1426	}
1427}
1428
1429void dml2_update_pipe_ctx_dchub_regs(struct _vcs_dpi_dml_display_rq_regs_st *rq_regs,
1430	struct _vcs_dpi_dml_display_dlg_regs_st *disp_dlg_regs,
1431	struct _vcs_dpi_dml_display_ttu_regs_st *disp_ttu_regs,
1432	struct pipe_ctx *out)
1433{
1434	memset(&out->rq_regs, 0, sizeof(out->rq_regs));
1435	out->rq_regs.rq_regs_l.chunk_size = rq_regs->rq_regs_l.chunk_size;
1436	out->rq_regs.rq_regs_l.min_chunk_size = rq_regs->rq_regs_l.min_chunk_size;
1437	out->rq_regs.rq_regs_l.meta_chunk_size = rq_regs->rq_regs_l.meta_chunk_size;
1438	out->rq_regs.rq_regs_l.min_meta_chunk_size = rq_regs->rq_regs_l.min_meta_chunk_size;
1439	out->rq_regs.rq_regs_l.dpte_group_size = rq_regs->rq_regs_l.dpte_group_size;
1440	out->rq_regs.rq_regs_l.mpte_group_size = rq_regs->rq_regs_l.mpte_group_size;
1441	out->rq_regs.rq_regs_l.swath_height = rq_regs->rq_regs_l.swath_height;
1442	out->rq_regs.rq_regs_l.pte_row_height_linear = rq_regs->rq_regs_l.pte_row_height_linear;
1443
1444	out->rq_regs.rq_regs_c.chunk_size = rq_regs->rq_regs_c.chunk_size;
1445	out->rq_regs.rq_regs_c.min_chunk_size = rq_regs->rq_regs_c.min_chunk_size;
1446	out->rq_regs.rq_regs_c.meta_chunk_size = rq_regs->rq_regs_c.meta_chunk_size;
1447	out->rq_regs.rq_regs_c.min_meta_chunk_size = rq_regs->rq_regs_c.min_meta_chunk_size;
1448	out->rq_regs.rq_regs_c.dpte_group_size = rq_regs->rq_regs_c.dpte_group_size;
1449	out->rq_regs.rq_regs_c.mpte_group_size = rq_regs->rq_regs_c.mpte_group_size;
1450	out->rq_regs.rq_regs_c.swath_height = rq_regs->rq_regs_c.swath_height;
1451	out->rq_regs.rq_regs_c.pte_row_height_linear = rq_regs->rq_regs_c.pte_row_height_linear;
1452
1453	out->rq_regs.drq_expansion_mode = rq_regs->drq_expansion_mode;
1454	out->rq_regs.prq_expansion_mode = rq_regs->prq_expansion_mode;
1455	out->rq_regs.mrq_expansion_mode = rq_regs->mrq_expansion_mode;
1456	out->rq_regs.crq_expansion_mode = rq_regs->crq_expansion_mode;
1457	out->rq_regs.plane1_base_address = rq_regs->plane1_base_address;
1458
1459	memset(&out->dlg_regs, 0, sizeof(out->dlg_regs));
1460	out->dlg_regs.refcyc_h_blank_end = disp_dlg_regs->refcyc_h_blank_end;
1461	out->dlg_regs.dlg_vblank_end = disp_dlg_regs->dlg_vblank_end;
1462	out->dlg_regs.min_dst_y_next_start = disp_dlg_regs->min_dst_y_next_start;
1463	out->dlg_regs.refcyc_per_htotal = disp_dlg_regs->refcyc_per_htotal;
1464	out->dlg_regs.refcyc_x_after_scaler = disp_dlg_regs->refcyc_x_after_scaler;
1465	out->dlg_regs.dst_y_after_scaler = disp_dlg_regs->dst_y_after_scaler;
1466	out->dlg_regs.dst_y_prefetch = disp_dlg_regs->dst_y_prefetch;
1467	out->dlg_regs.dst_y_per_vm_vblank = disp_dlg_regs->dst_y_per_vm_vblank;
1468	out->dlg_regs.dst_y_per_row_vblank = disp_dlg_regs->dst_y_per_row_vblank;
1469	out->dlg_regs.dst_y_per_vm_flip = disp_dlg_regs->dst_y_per_vm_flip;
1470	out->dlg_regs.dst_y_per_row_flip = disp_dlg_regs->dst_y_per_row_flip;
1471	out->dlg_regs.ref_freq_to_pix_freq = disp_dlg_regs->ref_freq_to_pix_freq;
1472	out->dlg_regs.vratio_prefetch = disp_dlg_regs->vratio_prefetch;
1473	out->dlg_regs.vratio_prefetch_c = disp_dlg_regs->vratio_prefetch_c;
1474	out->dlg_regs.refcyc_per_pte_group_vblank_l = disp_dlg_regs->refcyc_per_pte_group_vblank_l;
1475	out->dlg_regs.refcyc_per_pte_group_vblank_c = disp_dlg_regs->refcyc_per_pte_group_vblank_c;
1476	out->dlg_regs.refcyc_per_meta_chunk_vblank_l = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l;
1477	out->dlg_regs.refcyc_per_meta_chunk_vblank_c = disp_dlg_regs->refcyc_per_meta_chunk_vblank_c;
1478	out->dlg_regs.refcyc_per_pte_group_flip_l = disp_dlg_regs->refcyc_per_pte_group_flip_l;
1479	out->dlg_regs.refcyc_per_pte_group_flip_c = disp_dlg_regs->refcyc_per_pte_group_flip_c;
1480	out->dlg_regs.refcyc_per_meta_chunk_flip_l = disp_dlg_regs->refcyc_per_meta_chunk_flip_l;
1481	out->dlg_regs.refcyc_per_meta_chunk_flip_c = disp_dlg_regs->refcyc_per_meta_chunk_flip_c;
1482	out->dlg_regs.dst_y_per_pte_row_nom_l = disp_dlg_regs->dst_y_per_pte_row_nom_l;
1483	out->dlg_regs.dst_y_per_pte_row_nom_c = disp_dlg_regs->dst_y_per_pte_row_nom_c;
1484	out->dlg_regs.refcyc_per_pte_group_nom_l = disp_dlg_regs->refcyc_per_pte_group_nom_l;
1485	out->dlg_regs.refcyc_per_pte_group_nom_c = disp_dlg_regs->refcyc_per_pte_group_nom_c;
1486	out->dlg_regs.dst_y_per_meta_row_nom_l = disp_dlg_regs->dst_y_per_meta_row_nom_l;
1487	out->dlg_regs.dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_c;
1488	out->dlg_regs.refcyc_per_meta_chunk_nom_l = disp_dlg_regs->refcyc_per_meta_chunk_nom_l;
1489	out->dlg_regs.refcyc_per_meta_chunk_nom_c = disp_dlg_regs->refcyc_per_meta_chunk_nom_c;
1490	out->dlg_regs.refcyc_per_line_delivery_pre_l = disp_dlg_regs->refcyc_per_line_delivery_pre_l;
1491	out->dlg_regs.refcyc_per_line_delivery_pre_c = disp_dlg_regs->refcyc_per_line_delivery_pre_c;
1492	out->dlg_regs.refcyc_per_line_delivery_l = disp_dlg_regs->refcyc_per_line_delivery_l;
1493	out->dlg_regs.refcyc_per_line_delivery_c = disp_dlg_regs->refcyc_per_line_delivery_c;
1494	out->dlg_regs.refcyc_per_vm_group_vblank = disp_dlg_regs->refcyc_per_vm_group_vblank;
1495	out->dlg_regs.refcyc_per_vm_group_flip = disp_dlg_regs->refcyc_per_vm_group_flip;
1496	out->dlg_regs.refcyc_per_vm_req_vblank = disp_dlg_regs->refcyc_per_vm_req_vblank;
1497	out->dlg_regs.refcyc_per_vm_req_flip = disp_dlg_regs->refcyc_per_vm_req_flip;
1498	out->dlg_regs.dst_y_offset_cur0 = disp_dlg_regs->dst_y_offset_cur0;
1499	out->dlg_regs.chunk_hdl_adjust_cur0 = disp_dlg_regs->chunk_hdl_adjust_cur0;
1500	out->dlg_regs.dst_y_offset_cur1 = disp_dlg_regs->dst_y_offset_cur1;
1501	out->dlg_regs.chunk_hdl_adjust_cur1 = disp_dlg_regs->chunk_hdl_adjust_cur1;
1502	out->dlg_regs.vready_after_vcount0 = disp_dlg_regs->vready_after_vcount0;
1503	out->dlg_regs.dst_y_delta_drq_limit = disp_dlg_regs->dst_y_delta_drq_limit;
1504	out->dlg_regs.refcyc_per_vm_dmdata = disp_dlg_regs->refcyc_per_vm_dmdata;
1505	out->dlg_regs.dmdata_dl_delta = disp_dlg_regs->dmdata_dl_delta;
1506
1507	memset(&out->ttu_regs, 0, sizeof(out->ttu_regs));
1508	out->ttu_regs.qos_level_low_wm = disp_ttu_regs->qos_level_low_wm;
1509	out->ttu_regs.qos_level_high_wm = disp_ttu_regs->qos_level_high_wm;
1510	out->ttu_regs.min_ttu_vblank = disp_ttu_regs->min_ttu_vblank;
1511	out->ttu_regs.qos_level_flip = disp_ttu_regs->qos_level_flip;
1512	out->ttu_regs.refcyc_per_req_delivery_l = disp_ttu_regs->refcyc_per_req_delivery_l;
1513	out->ttu_regs.refcyc_per_req_delivery_c = disp_ttu_regs->refcyc_per_req_delivery_c;
1514	out->ttu_regs.refcyc_per_req_delivery_cur0 = disp_ttu_regs->refcyc_per_req_delivery_cur0;
1515	out->ttu_regs.refcyc_per_req_delivery_cur1 = disp_ttu_regs->refcyc_per_req_delivery_cur1;
1516	out->ttu_regs.refcyc_per_req_delivery_pre_l = disp_ttu_regs->refcyc_per_req_delivery_pre_l;
1517	out->ttu_regs.refcyc_per_req_delivery_pre_c = disp_ttu_regs->refcyc_per_req_delivery_pre_c;
1518	out->ttu_regs.refcyc_per_req_delivery_pre_cur0 = disp_ttu_regs->refcyc_per_req_delivery_pre_cur0;
1519	out->ttu_regs.refcyc_per_req_delivery_pre_cur1 = disp_ttu_regs->refcyc_per_req_delivery_pre_cur1;
1520	out->ttu_regs.qos_level_fixed_l = disp_ttu_regs->qos_level_fixed_l;
1521	out->ttu_regs.qos_level_fixed_c = disp_ttu_regs->qos_level_fixed_c;
1522	out->ttu_regs.qos_level_fixed_cur0 = disp_ttu_regs->qos_level_fixed_cur0;
1523	out->ttu_regs.qos_level_fixed_cur1 = disp_ttu_regs->qos_level_fixed_cur1;
1524	out->ttu_regs.qos_ramp_disable_l = disp_ttu_regs->qos_ramp_disable_l;
1525	out->ttu_regs.qos_ramp_disable_c = disp_ttu_regs->qos_ramp_disable_c;
1526	out->ttu_regs.qos_ramp_disable_cur0 = disp_ttu_regs->qos_ramp_disable_cur0;
1527	out->ttu_regs.qos_ramp_disable_cur1 = disp_ttu_regs->qos_ramp_disable_cur1;
1528}