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dml_top.h

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linux-6.19.14/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top.h C
 1// SPDX-License-Identifier: MIT
 2//
 3// Copyright 2024 Advanced Micro Devices, Inc.
 4
 5#ifndef __DML_TOP_H__
 6#define __DML_TOP_H__
 7
 8#include "dml_top_types.h"
 9
10/*
11 * Top Level Interface for DML2
12 */
13
14/*
15 * Returns the size of the DML instance for the caller to allocate
16 */
17unsigned int dml2_get_instance_size_bytes(void);
18
19/*
20 * Initializes the DML instance (i.e. with configuration, soc BB, IP params, etc...)
21 */
22bool dml2_initialize_instance(struct dml2_initialize_instance_in_out *in_out);
23
24/*
25 * Determines if the input mode is supported (boolean) on the SoC at all.  Does not return
26 * information on how mode should be programmed.
27 */
28bool dml2_check_mode_supported(struct dml2_check_mode_supported_in_out *in_out);
29
30/*
31 * Determines the full (optimized) programming for the input mode.  Returns minimum
32 * clocks as well as dchub register programming values for all pipes, additional meta
33 * such as ODM or MPCC combine factors.
34 */
35bool dml2_build_mode_programming(struct dml2_build_mode_programming_in_out *in_out);
36
37/*
38 * Determines the correct per pipe mcache register programming for a valid mode.
39 * The mcache allocation must have been calculated (successfully) in a previous
40 * call to dml2_build_mode_programming.
41 * The actual hubp viewport dimensions be what the actual registers will be
42 * programmed to (i.e. based on scaler setup).
43 */
44bool dml2_build_mcache_programming(struct dml2_build_mcache_programming_in_out *in_out);
45
46#endif
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