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dml1_display_rq_dlg_calc.c
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linux-6.19.14/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1/* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#include "dml1_display_rq_dlg_calc.h" 27#include "display_mode_lib.h" 28 29#include "dml_inline_defs.h" 30 31/* 32 * NOTE: 33 * This file is gcc-parseable HW gospel, coming straight from HW engineers. 34 * 35 * It doesn't adhere to Linux kernel style and sometimes will do things in odd 36 * ways. Unless there is something clearly wrong with it the code should 37 * remain as-is as it provides us with a guarantee from HW that it is correct. 38 */ 39 40static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma) 41{ 42 unsigned int ret_val = 1; 43 44 if (source_format == dm_444_16) { 45 if (!is_chroma) 46 ret_val = 2; 47 } else if (source_format == dm_444_32) { 48 if (!is_chroma) 49 ret_val = 4; 50 } else if (source_format == dm_444_64) { 51 if (!is_chroma) 52 ret_val = 8; 53 } else if (source_format == dm_420_8) { 54 if (is_chroma) 55 ret_val = 2; 56 else 57 ret_val = 1; 58 } else if (source_format == dm_420_10) { 59 if (is_chroma) 60 ret_val = 4; 61 else 62 ret_val = 2; 63 } 64 return ret_val; 65} 66 67static bool is_dual_plane(enum source_format_class source_format) 68{ 69 bool ret_val = 0; 70 71 if ((source_format == dm_420_8) || (source_format == dm_420_10)) 72 ret_val = 1; 73 74 return ret_val; 75} 76 77static void get_blk256_size( 78 unsigned int *blk256_width, 79 unsigned int *blk256_height, 80 unsigned int bytes_per_element) 81{ 82 if (bytes_per_element == 1) { 83 *blk256_width = 16; 84 *blk256_height = 16; 85 } else if (bytes_per_element == 2) { 86 *blk256_width = 16; 87 *blk256_height = 8; 88 } else if (bytes_per_element == 4) { 89 *blk256_width = 8; 90 *blk256_height = 8; 91 } else if (bytes_per_element == 8) { 92 *blk256_width = 8; 93 *blk256_height = 4; 94 } 95} 96 97static double get_refcyc_per_delivery( 98 struct display_mode_lib *mode_lib, 99 double refclk_freq_in_mhz, 100 double pclk_freq_in_mhz, 101 unsigned int recout_width, 102 double vratio, 103 double hscale_pixel_rate, 104 unsigned int delivery_width, 105 unsigned int req_per_swath_ub) 106{ 107 double refcyc_per_delivery = 0.0; 108 109 if (vratio <= 1.0) { 110 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width 111 / pclk_freq_in_mhz / (double) req_per_swath_ub; 112 } else { 113 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width 114 / (double) hscale_pixel_rate / (double) req_per_swath_ub; 115 } 116 117 DTRACE("DLG: %s: refclk_freq_in_mhz = %3.2f", __func__, refclk_freq_in_mhz); 118 DTRACE("DLG: %s: pclk_freq_in_mhz = %3.2f", __func__, pclk_freq_in_mhz); 119 DTRACE("DLG: %s: recout_width = %d", __func__, recout_width); 120 DTRACE("DLG: %s: vratio = %3.2f", __func__, vratio); 121 DTRACE("DLG: %s: req_per_swath_ub = %d", __func__, req_per_swath_ub); 122 DTRACE("DLG: %s: refcyc_per_delivery= %3.2f", __func__, refcyc_per_delivery); 123 124 return refcyc_per_delivery; 125 126} 127 128static double get_vratio_pre( 129 struct display_mode_lib *mode_lib, 130 unsigned int max_num_sw, 131 unsigned int max_partial_sw, 132 unsigned int swath_height, 133 double vinit, 134 double l_sw) 135{ 136 double prefill = dml_floor(vinit, 1); 137 double vratio_pre = 1.0; 138 139 vratio_pre = (max_num_sw * swath_height + max_partial_sw) / l_sw; 140 141 if (swath_height > 4) { 142 double tmp0 = (max_num_sw * swath_height) / (l_sw - (prefill - 3.0) / 2.0); 143 144 if (tmp0 > vratio_pre) 145 vratio_pre = tmp0; 146 } 147 148 DTRACE("DLG: %s: max_num_sw = %0d", __func__, max_num_sw); 149 DTRACE("DLG: %s: max_partial_sw = %0d", __func__, max_partial_sw); 150 DTRACE("DLG: %s: swath_height = %0d", __func__, swath_height); 151 DTRACE("DLG: %s: vinit = %3.2f", __func__, vinit); 152 DTRACE("DLG: %s: vratio_pre = %3.2f", __func__, vratio_pre); 153 154 if (vratio_pre < 1.0) { 155 DTRACE("WARNING_DLG: %s: vratio_pre=%3.2f < 1.0, set to 1.0", __func__, vratio_pre); 156 vratio_pre = 1.0; 157 } 158 159 if (vratio_pre > 4.0) { 160 DTRACE( 161 "WARNING_DLG: %s: vratio_pre=%3.2f > 4.0 (max scaling ratio). set to 4.0", 162 __func__, 163 vratio_pre); 164 vratio_pre = 4.0; 165 } 166 167 return vratio_pre; 168} 169 170static void get_swath_need( 171 struct display_mode_lib *mode_lib, 172 unsigned int *max_num_sw, 173 unsigned int *max_partial_sw, 174 unsigned int swath_height, 175 double vinit) 176{ 177 double prefill = dml_floor(vinit, 1); 178 unsigned int max_partial_sw_int; 179 180 DTRACE("DLG: %s: swath_height = %0d", __func__, swath_height); 181 DTRACE("DLG: %s: vinit = %3.2f", __func__, vinit); 182 183 ASSERT(prefill > 0.0 && prefill <= 8.0); 184 185 *max_num_sw = (unsigned int) (dml_ceil((prefill - 1.0) / (double) swath_height, 1) + 1.0); /* prefill has to be >= 1 */ 186 max_partial_sw_int = 187 (prefill == 1) ? 188 (swath_height - 1) : 189 ((unsigned int) (prefill - 2.0) % swath_height); 190 *max_partial_sw = (max_partial_sw_int < 1) ? 1 : max_partial_sw_int; /* ensure minimum of 1 is used */ 191 192 DTRACE("DLG: %s: max_num_sw = %0d", __func__, *max_num_sw); 193 DTRACE("DLG: %s: max_partial_sw = %0d", __func__, *max_partial_sw); 194} 195 196static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size) 197{ 198 if (tile_size == dm_256k_tile) 199 return (256 * 1024); 200 else if (tile_size == dm_64k_tile) 201 return (64 * 1024); 202 else 203 return (4 * 1024); 204} 205 206static void extract_rq_sizing_regs( 207 struct display_mode_lib *mode_lib, 208 struct _vcs_dpi_display_data_rq_regs_st *rq_regs, 209 const struct _vcs_dpi_display_data_rq_sizing_params_st *rq_sizing) 210{ 211 DTRACE("DLG: %s: rq_sizing param", __func__); 212 print__data_rq_sizing_params_st(mode_lib, rq_sizing); 213 214 rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10; 215 216 if (rq_sizing->min_chunk_bytes == 0) 217 rq_regs->min_chunk_size = 0; 218 else 219 rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1; 220 221 rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10; 222 if (rq_sizing->min_meta_chunk_bytes == 0) 223 rq_regs->min_meta_chunk_size = 0; 224 else 225 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1; 226 227 rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6; 228 rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6; 229} 230 231void dml1_extract_rq_regs( 232 struct display_mode_lib *mode_lib, 233 struct _vcs_dpi_display_rq_regs_st *rq_regs, 234 const struct _vcs_dpi_display_rq_params_st *rq_param) 235{ 236 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; 237 unsigned int detile_buf_plane1_addr = 0; 238 239 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); 240 if (rq_param->yuv420) 241 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); 242 243 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); 244 rq_regs->rq_regs_c.swath_height = dml_log2(rq_param->dlg.rq_c.swath_height); 245 246 /* TODO: take the max between luma, chroma chunk size? 247 * okay for now, as we are setting chunk_bytes to 8kb anyways 248 */ 249 if (rq_param->sizing.rq_l.chunk_bytes >= 32 * 1024) { /*32kb */ 250 rq_regs->drq_expansion_mode = 0; 251 } else { 252 rq_regs->drq_expansion_mode = 2; 253 } 254 rq_regs->prq_expansion_mode = 1; 255 rq_regs->mrq_expansion_mode = 1; 256 rq_regs->crq_expansion_mode = 1; 257 258 if (rq_param->yuv420) { 259 if ((double) rq_param->misc.rq_l.stored_swath_bytes 260 / (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { 261 detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); /* half to chroma */ 262 } else { 263 detile_buf_plane1_addr = dml_round_to_multiple( 264 (unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 265 256, 266 0) / 64.0; /* 2/3 to chroma */ 267 } 268 } 269 rq_regs->plane1_base_address = detile_buf_plane1_addr; 270} 271 272static void handle_det_buf_split( 273 struct display_mode_lib *mode_lib, 274 struct _vcs_dpi_display_rq_params_st *rq_param, 275 const struct _vcs_dpi_display_pipe_source_params_st *pipe_src_param) 276{ 277 unsigned int total_swath_bytes = 0; 278 unsigned int swath_bytes_l = 0; 279 unsigned int swath_bytes_c = 0; 280 unsigned int full_swath_bytes_packed_l = 0; 281 unsigned int full_swath_bytes_packed_c = 0; 282 bool req128_l = 0; 283 bool req128_c = 0; 284 bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear); 285 bool surf_vert = (pipe_src_param->source_scan == dm_vert); 286 unsigned int log2_swath_height_l = 0; 287 unsigned int log2_swath_height_c = 0; 288 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; 289 290 full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes; 291 full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes; 292 293 if (rq_param->yuv420_10bpc) { 294 full_swath_bytes_packed_l = dml_round_to_multiple( 295 rq_param->misc.rq_l.full_swath_bytes * 2 / 3, 296 256, 297 1) + 256; 298 full_swath_bytes_packed_c = dml_round_to_multiple( 299 rq_param->misc.rq_c.full_swath_bytes * 2 / 3, 300 256, 301 1) + 256; 302 } 303 304 if (rq_param->yuv420) { 305 total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c; 306 307 if (total_swath_bytes <= detile_buf_size_in_bytes) { /*full 256b request */ 308 req128_l = 0; 309 req128_c = 0; 310 swath_bytes_l = full_swath_bytes_packed_l; 311 swath_bytes_c = full_swath_bytes_packed_c; 312 } else { /*128b request (for luma only for yuv420 8bpc) */ 313 req128_l = 1; 314 req128_c = 0; 315 swath_bytes_l = full_swath_bytes_packed_l / 2; 316 swath_bytes_c = full_swath_bytes_packed_c; 317 } 318 319 /* Bug workaround, luma and chroma req size needs to be the same. (see: DEGVIDCN10-137) 320 * TODO: Remove after rtl fix 321 */ 322 if (req128_l == 1) { 323 req128_c = 1; 324 DTRACE("DLG: %s: bug workaround DEGVIDCN10-137", __func__); 325 } 326 327 /* Note: assumption, the config that pass in will fit into 328 * the detiled buffer. 329 */ 330 } else { 331 total_swath_bytes = 2 * full_swath_bytes_packed_l; 332 333 if (total_swath_bytes <= detile_buf_size_in_bytes) 334 req128_l = 0; 335 else 336 req128_l = 1; 337 338 swath_bytes_l = total_swath_bytes; 339 swath_bytes_c = 0; 340 } 341 rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l; 342 rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c; 343 344 if (surf_linear) { 345 log2_swath_height_l = 0; 346 log2_swath_height_c = 0; 347 } else { 348 unsigned int swath_height_l; 349 unsigned int swath_height_c; 350 351 if (!surf_vert) { 352 swath_height_l = rq_param->misc.rq_l.blk256_height; 353 swath_height_c = rq_param->misc.rq_c.blk256_height; 354 } else { 355 swath_height_l = rq_param->misc.rq_l.blk256_width; 356 swath_height_c = rq_param->misc.rq_c.blk256_width; 357 } 358 359 if (swath_height_l > 0) 360 log2_swath_height_l = dml_log2(swath_height_l); 361 362 if (req128_l && log2_swath_height_l > 0) 363 log2_swath_height_l -= 1; 364 365 if (swath_height_c > 0) 366 log2_swath_height_c = dml_log2(swath_height_c); 367 368 if (req128_c && log2_swath_height_c > 0) 369 log2_swath_height_c -= 1; 370 } 371 372 rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l; 373 rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c; 374 375 DTRACE("DLG: %s: req128_l = %0d", __func__, req128_l); 376 DTRACE("DLG: %s: req128_c = %0d", __func__, req128_c); 377 DTRACE("DLG: %s: full_swath_bytes_packed_l = %0d", __func__, full_swath_bytes_packed_l); 378 DTRACE("DLG: %s: full_swath_bytes_packed_c = %0d", __func__, full_swath_bytes_packed_c); 379} 380 381/* Need refactor. */ 382static void dml1_rq_dlg_get_row_heights( 383 struct display_mode_lib *mode_lib, 384 unsigned int *o_dpte_row_height, 385 unsigned int *o_meta_row_height, 386 unsigned int vp_width, 387 unsigned int data_pitch, 388 int source_format, 389 int tiling, 390 int macro_tile_size, 391 int source_scan, 392 int is_chroma) 393{ 394 bool surf_linear = (tiling == dm_sw_linear); 395 bool surf_vert = (source_scan == dm_vert); 396 397 unsigned int bytes_per_element = get_bytes_per_element( 398 (enum source_format_class) source_format, 399 is_chroma); 400 unsigned int log2_bytes_per_element = dml_log2(bytes_per_element); 401 unsigned int blk256_width = 0; 402 unsigned int blk256_height = 0; 403 404 unsigned int log2_blk256_height; 405 unsigned int blk_bytes; 406 unsigned int log2_blk_bytes; 407 unsigned int log2_blk_height; 408 unsigned int log2_blk_width; 409 unsigned int log2_meta_req_bytes; 410 unsigned int log2_meta_req_height; 411 unsigned int log2_meta_req_width; 412 unsigned int log2_meta_row_height; 413 unsigned int log2_vmpg_bytes; 414 unsigned int dpte_buf_in_pte_reqs; 415 unsigned int log2_vmpg_height; 416 unsigned int log2_vmpg_width; 417 unsigned int log2_dpte_req_height_ptes; 418 unsigned int log2_dpte_req_width_ptes; 419 unsigned int log2_dpte_req_height; 420 unsigned int log2_dpte_req_width; 421 unsigned int log2_dpte_row_height_linear; 422 unsigned int log2_dpte_row_height; 423 unsigned int dpte_req_width; 424 425 if (surf_linear) { 426 blk256_width = 256; 427 blk256_height = 1; 428 } else { 429 get_blk256_size(&blk256_width, &blk256_height, bytes_per_element); 430 } 431 432 log2_blk256_height = dml_log2((double) blk256_height); 433 blk_bytes = surf_linear ? 434 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size); 435 log2_blk_bytes = dml_log2((double) blk_bytes); 436 log2_blk_height = 0; 437 log2_blk_width = 0; 438 439 /* remember log rule 440 * "+" in log is multiply 441 * "-" in log is divide 442 * "/2" is like square root 443 * blk is vertical biased 444 */ 445 if (tiling != dm_sw_linear) 446 log2_blk_height = log2_blk256_height 447 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); 448 else 449 log2_blk_height = 0; /* blk height of 1 */ 450 451 log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height; 452 453 /* ------- */ 454 /* meta */ 455 /* ------- */ 456 log2_meta_req_bytes = 6; /* meta request is 64b and is 8x8byte meta element */ 457 458 /* each 64b meta request for dcn is 8x8 meta elements and 459 * a meta element covers one 256b block of the data surface. 460 */ 461 log2_meta_req_height = log2_blk256_height + 3; /* meta req is 8x8 */ 462 log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element 463 - log2_meta_req_height; 464 log2_meta_row_height = 0; 465 466 /* the dimensions of a meta row are meta_row_width x meta_row_height in elements. 467 * calculate upper bound of the meta_row_width 468 */ 469 if (!surf_vert) 470 log2_meta_row_height = log2_meta_req_height; 471 else 472 log2_meta_row_height = log2_meta_req_width; 473 474 *o_meta_row_height = 1 << log2_meta_row_height; 475 476 /* ------ */ 477 /* dpte */ 478 /* ------ */ 479 log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes); 480 dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma; 481 482 log2_vmpg_height = 0; 483 log2_vmpg_width = 0; 484 log2_dpte_req_height_ptes = 0; 485 log2_dpte_req_width_ptes = 0; 486 log2_dpte_req_height = 0; 487 log2_dpte_req_width = 0; 488 log2_dpte_row_height_linear = 0; 489 log2_dpte_row_height = 0; 490 dpte_req_width = 0; /* 64b dpte req width in data element */ 491 492 if (surf_linear) 493 log2_vmpg_height = 0; /* one line high */ 494 else 495 log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height; 496 log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height; 497 498 /* only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4. */ 499 if (log2_blk_bytes <= log2_vmpg_bytes) 500 log2_dpte_req_height_ptes = 0; 501 else if (log2_blk_height - log2_vmpg_height >= 2) 502 log2_dpte_req_height_ptes = 2; 503 else 504 log2_dpte_req_height_ptes = log2_blk_height - log2_vmpg_height; 505 log2_dpte_req_width_ptes = 3 - log2_dpte_req_height_ptes; 506 507 ASSERT((log2_dpte_req_width_ptes == 3 && log2_dpte_req_height_ptes == 0) || /* 8x1 */ 508 (log2_dpte_req_width_ptes == 2 && log2_dpte_req_height_ptes == 1) || /* 4x2 */ 509 (log2_dpte_req_width_ptes == 1 && log2_dpte_req_height_ptes == 2)); /* 2x4 */ 510 511 /* the dpte request dimensions in data elements is dpte_req_width x dpte_req_height 512 * log2_wmpg_width is how much 1 pte represent, now trying to calculate how much 64b pte req represent 513 */ 514 log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes; 515 log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes; 516 dpte_req_width = 1 << log2_dpte_req_width; 517 518 /* calculate pitch dpte row buffer can hold 519 * round the result down to a power of two. 520 */ 521 if (surf_linear) { 522 log2_dpte_row_height_linear = dml_floor( 523 dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 524 1); 525 526 ASSERT(log2_dpte_row_height_linear >= 3); 527 528 if (log2_dpte_row_height_linear > 7) 529 log2_dpte_row_height_linear = 7; 530 531 log2_dpte_row_height = log2_dpte_row_height_linear; 532 } else { 533 /* the upper bound of the dpte_row_width without dependency on viewport position follows. */ 534 if (!surf_vert) 535 log2_dpte_row_height = log2_dpte_req_height; 536 else 537 log2_dpte_row_height = 538 (log2_blk_width < log2_dpte_req_width) ? 539 log2_blk_width : log2_dpte_req_width; 540 } 541 542 /* From programming guide: 543 * There is a special case of saving only half of ptes returned due to buffer space limits. 544 * this case applies to 4 and 8bpe in horizontal access of a vp_width greater than 2560+16 545 * when the pte request is 2x4 ptes (which happens when vmpg_bytes =4kb and tile blk_bytes >=64kb). 546 */ 547 if (!surf_vert && vp_width > (2560 + 16) && bytes_per_element >= 4 && log2_vmpg_bytes == 12 548 && log2_blk_bytes >= 16) 549 log2_dpte_row_height = log2_dpte_row_height - 1; /*half of the full height */ 550 551 *o_dpte_row_height = 1 << log2_dpte_row_height; 552} 553 554static void get_surf_rq_param( 555 struct display_mode_lib *mode_lib, 556 struct _vcs_dpi_display_data_rq_sizing_params_st *rq_sizing_param, 557 struct _vcs_dpi_display_data_rq_dlg_params_st *rq_dlg_param, 558 struct _vcs_dpi_display_data_rq_misc_params_st *rq_misc_param, 559 const struct _vcs_dpi_display_pipe_source_params_st *pipe_src_param, 560 bool is_chroma) 561{ 562 unsigned int vp_width = 0; 563 unsigned int vp_height = 0; 564 unsigned int data_pitch = 0; 565 unsigned int meta_pitch = 0; 566 unsigned int ppe = 1; 567 bool surf_linear; 568 bool surf_vert; 569 unsigned int bytes_per_element; 570 unsigned int log2_bytes_per_element; 571 unsigned int blk256_width; 572 unsigned int blk256_height; 573 unsigned int log2_blk256_width; 574 unsigned int log2_blk256_height; 575 unsigned int blk_bytes; 576 unsigned int log2_blk_bytes; 577 unsigned int log2_blk_height; 578 unsigned int log2_blk_width; 579 unsigned int log2_meta_req_bytes; 580 unsigned int log2_meta_req_height; 581 unsigned int log2_meta_req_width; 582 unsigned int meta_req_width; 583 unsigned int meta_req_height; 584 unsigned int log2_meta_row_height; 585 unsigned int meta_row_width_ub; 586 unsigned int log2_meta_chunk_bytes; 587 unsigned int log2_meta_chunk_height; 588 unsigned int log2_meta_chunk_width; 589 unsigned int log2_min_meta_chunk_bytes; 590 unsigned int min_meta_chunk_width; 591 unsigned int meta_chunk_width; 592 unsigned int meta_chunk_per_row_int; 593 unsigned int meta_row_remainder; 594 unsigned int meta_chunk_threshold; 595 unsigned int meta_blk_bytes; 596 unsigned int meta_blk_height; 597 unsigned int meta_blk_width; 598 unsigned int meta_surface_bytes; 599 unsigned int vmpg_bytes; 600 unsigned int meta_pte_req_per_frame_ub; 601 unsigned int meta_pte_bytes_per_frame_ub; 602 unsigned int log2_vmpg_bytes; 603 unsigned int dpte_buf_in_pte_reqs; 604 unsigned int log2_vmpg_height; 605 unsigned int log2_vmpg_width; 606 unsigned int log2_dpte_req_height_ptes; 607 unsigned int log2_dpte_req_width_ptes; 608 unsigned int log2_dpte_req_height; 609 unsigned int log2_dpte_req_width; 610 unsigned int log2_dpte_row_height_linear; 611 unsigned int log2_dpte_row_height; 612 unsigned int log2_dpte_group_width; 613 unsigned int dpte_row_width_ub; 614 unsigned int dpte_row_height; 615 unsigned int dpte_req_height; 616 unsigned int dpte_req_width; 617 unsigned int dpte_group_width; 618 unsigned int log2_dpte_group_bytes; 619 unsigned int log2_dpte_group_length; 620 unsigned int func_meta_row_height, func_dpte_row_height; 621 622 /* TODO check if ppe apply for both luma and chroma in 422 case */ 623 if (is_chroma) { 624 vp_width = pipe_src_param->viewport_width_c / ppe; 625 vp_height = pipe_src_param->viewport_height_c; 626 data_pitch = pipe_src_param->data_pitch_c; 627 meta_pitch = pipe_src_param->meta_pitch_c; 628 } else { 629 vp_width = pipe_src_param->viewport_width / ppe; 630 vp_height = pipe_src_param->viewport_height; 631 data_pitch = pipe_src_param->data_pitch; 632 meta_pitch = pipe_src_param->meta_pitch; 633 } 634 635 rq_sizing_param->chunk_bytes = 8192; 636 637 if (rq_sizing_param->chunk_bytes == 64 * 1024) 638 rq_sizing_param->min_chunk_bytes = 0; 639 else 640 rq_sizing_param->min_chunk_bytes = 1024; 641 642 rq_sizing_param->meta_chunk_bytes = 2048; 643 rq_sizing_param->min_meta_chunk_bytes = 256; 644 645 rq_sizing_param->mpte_group_bytes = 2048; 646 647 surf_linear = (pipe_src_param->sw_mode == dm_sw_linear); 648 surf_vert = (pipe_src_param->source_scan == dm_vert); 649 650 bytes_per_element = get_bytes_per_element( 651 (enum source_format_class) pipe_src_param->source_format, 652 is_chroma); 653 log2_bytes_per_element = dml_log2(bytes_per_element); 654 blk256_width = 0; 655 blk256_height = 0; 656 657 if (surf_linear) { 658 blk256_width = 256 / bytes_per_element; 659 blk256_height = 1; 660 } else { 661 get_blk256_size(&blk256_width, &blk256_height, bytes_per_element); 662 } 663 664 DTRACE("DLG: %s: surf_linear = %d", __func__, surf_linear); 665 DTRACE("DLG: %s: surf_vert = %d", __func__, surf_vert); 666 DTRACE("DLG: %s: blk256_width = %d", __func__, blk256_width); 667 DTRACE("DLG: %s: blk256_height = %d", __func__, blk256_height); 668 669 log2_blk256_width = dml_log2((double) blk256_width); 670 log2_blk256_height = dml_log2((double) blk256_height); 671 blk_bytes = 672 surf_linear ? 256 : get_blk_size_bytes( 673 (enum source_macro_tile_size) pipe_src_param->macro_tile_size); 674 log2_blk_bytes = dml_log2((double) blk_bytes); 675 log2_blk_height = 0; 676 log2_blk_width = 0; 677 678 /* remember log rule 679 * "+" in log is multiply 680 * "-" in log is divide 681 * "/2" is like square root 682 * blk is vertical biased 683 */ 684 if (pipe_src_param->sw_mode != dm_sw_linear) 685 log2_blk_height = log2_blk256_height 686 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); 687 else 688 log2_blk_height = 0; /* blk height of 1 */ 689 690 log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height; 691 692 if (!surf_vert) { 693 rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1) 694 + blk256_width; 695 rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width; 696 } else { 697 rq_dlg_param->swath_width_ub = dml_round_to_multiple( 698 vp_height - 1, 699 blk256_height, 700 1) + blk256_height; 701 rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height; 702 } 703 704 if (!surf_vert) 705 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height 706 * bytes_per_element; 707 else 708 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width 709 * bytes_per_element; 710 711 rq_misc_param->blk256_height = blk256_height; 712 rq_misc_param->blk256_width = blk256_width; 713 714 /* ------- */ 715 /* meta */ 716 /* ------- */ 717 log2_meta_req_bytes = 6; /* meta request is 64b and is 8x8byte meta element */ 718 719 /* each 64b meta request for dcn is 8x8 meta elements and 720 * a meta element covers one 256b block of the data surface. 721 */ 722 log2_meta_req_height = log2_blk256_height + 3; /* meta req is 8x8 byte, each byte represent 1 blk256 */ 723 log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element 724 - log2_meta_req_height; 725 meta_req_width = 1 << log2_meta_req_width; 726 meta_req_height = 1 << log2_meta_req_height; 727 log2_meta_row_height = 0; 728 meta_row_width_ub = 0; 729 730 /* the dimensions of a meta row are meta_row_width x meta_row_height in elements. 731 * calculate upper bound of the meta_row_width 732 */ 733 if (!surf_vert) { 734 log2_meta_row_height = log2_meta_req_height; 735 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) 736 + meta_req_width; 737 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; 738 } else { 739 log2_meta_row_height = log2_meta_req_width; 740 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) 741 + meta_req_height; 742 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; 743 } 744 rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64; 745 746 log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes); 747 log2_meta_chunk_height = log2_meta_row_height; 748 749 /*full sized meta chunk width in unit of data elements */ 750 log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element 751 - log2_meta_chunk_height; 752 log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes); 753 min_meta_chunk_width = 1 754 << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element 755 - log2_meta_chunk_height); 756 meta_chunk_width = 1 << log2_meta_chunk_width; 757 meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width); 758 meta_row_remainder = meta_row_width_ub % meta_chunk_width; 759 meta_chunk_threshold = 0; 760 meta_blk_bytes = 4096; 761 meta_blk_height = blk256_height * 64; 762 meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height; 763 meta_surface_bytes = meta_pitch 764 * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) 765 + meta_blk_height) * bytes_per_element / 256; 766 vmpg_bytes = mode_lib->soc.vmm_page_size_bytes; 767 meta_pte_req_per_frame_ub = (dml_round_to_multiple( 768 meta_surface_bytes - vmpg_bytes, 769 8 * vmpg_bytes, 770 1) + 8 * vmpg_bytes) / (8 * vmpg_bytes); 771 meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; /*64B mpte request */ 772 rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub; 773 774 DTRACE("DLG: %s: meta_blk_height = %d", __func__, meta_blk_height); 775 DTRACE("DLG: %s: meta_blk_width = %d", __func__, meta_blk_width); 776 DTRACE("DLG: %s: meta_surface_bytes = %d", __func__, meta_surface_bytes); 777 DTRACE("DLG: %s: meta_pte_req_per_frame_ub = %d", __func__, meta_pte_req_per_frame_ub); 778 DTRACE("DLG: %s: meta_pte_bytes_per_frame_ub = %d", __func__, meta_pte_bytes_per_frame_ub); 779 780 if (!surf_vert) 781 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; 782 else 783 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; 784 785 if (meta_row_remainder <= meta_chunk_threshold) 786 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1; 787 else 788 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2; 789 790 rq_dlg_param->meta_row_height = 1 << log2_meta_row_height; 791 792 /* ------ */ 793 /* dpte */ 794 /* ------ */ 795 log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes); 796 dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma; 797 798 log2_vmpg_height = 0; 799 log2_vmpg_width = 0; 800 log2_dpte_req_height_ptes = 0; 801 log2_dpte_req_width_ptes = 0; 802 log2_dpte_req_height = 0; 803 log2_dpte_req_width = 0; 804 log2_dpte_row_height_linear = 0; 805 log2_dpte_row_height = 0; 806 log2_dpte_group_width = 0; 807 dpte_row_width_ub = 0; 808 dpte_row_height = 0; 809 dpte_req_height = 0; /* 64b dpte req height in data element */ 810 dpte_req_width = 0; /* 64b dpte req width in data element */ 811 dpte_group_width = 0; 812 log2_dpte_group_bytes = 0; 813 log2_dpte_group_length = 0; 814 815 if (surf_linear) 816 log2_vmpg_height = 0; /* one line high */ 817 else 818 log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height; 819 log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height; 820 821 /* only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4. */ 822 if (log2_blk_bytes <= log2_vmpg_bytes) 823 log2_dpte_req_height_ptes = 0; 824 else if (log2_blk_height - log2_vmpg_height >= 2) 825 log2_dpte_req_height_ptes = 2; 826 else 827 log2_dpte_req_height_ptes = log2_blk_height - log2_vmpg_height; 828 log2_dpte_req_width_ptes = 3 - log2_dpte_req_height_ptes; 829 830 /* Ensure we only have the 3 shapes */ 831 ASSERT((log2_dpte_req_width_ptes == 3 && log2_dpte_req_height_ptes == 0) || /* 8x1 */ 832 (log2_dpte_req_width_ptes == 2 && log2_dpte_req_height_ptes == 1) || /* 4x2 */ 833 (log2_dpte_req_width_ptes == 1 && log2_dpte_req_height_ptes == 2)); /* 2x4 */ 834 835 /* The dpte request dimensions in data elements is dpte_req_width x dpte_req_height 836 * log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent 837 * That depends on the pte shape (i.e. 8x1, 4x2, 2x4) 838 */ 839 log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes; 840 log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes; 841 dpte_req_height = 1 << log2_dpte_req_height; 842 dpte_req_width = 1 << log2_dpte_req_width; 843 844 /* calculate pitch dpte row buffer can hold 845 * round the result down to a power of two. 846 */ 847 if (surf_linear) { 848 log2_dpte_row_height_linear = dml_floor( 849 dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 850 1); 851 852 ASSERT(log2_dpte_row_height_linear >= 3); 853 854 if (log2_dpte_row_height_linear > 7) 855 log2_dpte_row_height_linear = 7; 856 857 log2_dpte_row_height = log2_dpte_row_height_linear; 858 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; 859 860 /* For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary. 861 * the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering. 862 */ 863 dpte_row_width_ub = dml_round_to_multiple( 864 data_pitch * dpte_row_height - 1, 865 dpte_req_width, 866 1) + dpte_req_width; 867 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; 868 } else { 869 /* for tiled mode, row height is the same as req height and row store up to vp size upper bound */ 870 if (!surf_vert) { 871 log2_dpte_row_height = log2_dpte_req_height; 872 dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1) 873 + dpte_req_width; 874 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; 875 } else { 876 log2_dpte_row_height = 877 (log2_blk_width < log2_dpte_req_width) ? 878 log2_blk_width : log2_dpte_req_width; 879 dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1) 880 + dpte_req_height; 881 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height; 882 } 883 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; 884 } 885 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; 886 887 /* From programming guide: 888 * There is a special case of saving only half of ptes returned due to buffer space limits. 889 * this case applies to 4 and 8bpe in horizontal access of a vp_width greater than 2560+16 890 * when the pte request is 2x4 ptes (which happens when vmpg_bytes =4kb and tile blk_bytes >=64kb). 891 */ 892 if (!surf_vert && vp_width > (2560 + 16) && bytes_per_element >= 4 && log2_vmpg_bytes == 12 893 && log2_blk_bytes >= 16) { 894 log2_dpte_row_height = log2_dpte_row_height - 1; /*half of the full height */ 895 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; 896 } 897 898 /* the dpte_group_bytes is reduced for the specific case of vertical 899 * access of a tile surface that has dpte request of 8x1 ptes. 900 */ 901 if (!surf_linear && (log2_dpte_req_height_ptes == 0) && surf_vert) /*reduced, in this case, will have page fault within a group */ 902 rq_sizing_param->dpte_group_bytes = 512; 903 else 904 /*full size */ 905 rq_sizing_param->dpte_group_bytes = 2048; 906 907 /*since pte request size is 64byte, the number of data pte requests per full sized group is as follows. */ 908 log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes); 909 log2_dpte_group_length = log2_dpte_group_bytes - 6; /*length in 64b requests */ 910 911 /* full sized data pte group width in elements */ 912 if (!surf_vert) 913 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width; 914 else 915 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height; 916 917 dpte_group_width = 1 << log2_dpte_group_width; 918 919 /* since dpte groups are only aligned to dpte_req_width and not dpte_group_width, 920 * the upper bound for the dpte groups per row is as follows. 921 */ 922 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil( 923 (double) dpte_row_width_ub / dpte_group_width, 924 1); 925 926 dml1_rq_dlg_get_row_heights( 927 mode_lib, 928 &func_dpte_row_height, 929 &func_meta_row_height, 930 vp_width, 931 data_pitch, 932 pipe_src_param->source_format, 933 pipe_src_param->sw_mode, 934 pipe_src_param->macro_tile_size, 935 pipe_src_param->source_scan, 936 is_chroma); 937 938 /* Just a check to make sure this function and the new one give the same 939 * result. The standalone get_row_heights() function is based off of the 940 * code in this function so the same changes need to be made to both. 941 */ 942 if (rq_dlg_param->meta_row_height != func_meta_row_height) { 943 DTRACE( 944 "MISMATCH: rq_dlg_param->meta_row_height = %d", 945 rq_dlg_param->meta_row_height); 946 DTRACE("MISMATCH: func_meta_row_height = %d", func_meta_row_height); 947 ASSERT(0); 948 } 949 950 if (rq_dlg_param->dpte_row_height != func_dpte_row_height) { 951 DTRACE( 952 "MISMATCH: rq_dlg_param->dpte_row_height = %d", 953 rq_dlg_param->dpte_row_height); 954 DTRACE("MISMATCH: func_dpte_row_height = %d", func_dpte_row_height); 955 ASSERT(0); 956 } 957} 958 959void dml1_rq_dlg_get_rq_params( 960 struct display_mode_lib *mode_lib, 961 struct _vcs_dpi_display_rq_params_st *rq_param, 962 const struct _vcs_dpi_display_pipe_source_params_st *pipe_src_param) 963{ 964 /* get param for luma surface */ 965 rq_param->yuv420 = pipe_src_param->source_format == dm_420_8 966 || pipe_src_param->source_format == dm_420_10; 967 rq_param->yuv420_10bpc = pipe_src_param->source_format == dm_420_10; 968 969 get_surf_rq_param( 970 mode_lib, 971 &(rq_param->sizing.rq_l), 972 &(rq_param->dlg.rq_l), 973 &(rq_param->misc.rq_l), 974 pipe_src_param, 975 0); 976 977 if (is_dual_plane((enum source_format_class) pipe_src_param->source_format)) { 978 /* get param for chroma surface */ 979 get_surf_rq_param( 980 mode_lib, 981 &(rq_param->sizing.rq_c), 982 &(rq_param->dlg.rq_c), 983 &(rq_param->misc.rq_c), 984 pipe_src_param, 985 1); 986 } 987 988 /* calculate how to split the det buffer space between luma and chroma */ 989 handle_det_buf_split(mode_lib, rq_param, pipe_src_param); 990 print__rq_params_st(mode_lib, rq_param); 991} 992 993/* Note: currently taken in as is. 994 * Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma. 995 */ 996void dml1_rq_dlg_get_dlg_params( 997 struct display_mode_lib *mode_lib, 998 struct _vcs_dpi_display_dlg_regs_st *disp_dlg_regs, 999 struct _vcs_dpi_display_ttu_regs_st *disp_ttu_regs, 1000 const struct _vcs_dpi_display_rq_dlg_params_st *rq_dlg_param, 1001 const struct _vcs_dpi_display_dlg_sys_params_st *dlg_sys_param, 1002 const struct _vcs_dpi_display_e2e_pipe_params_st *e2e_pipe_param, 1003 const bool cstate_en, 1004 const bool pstate_en, 1005 const bool vm_en, 1006 const bool iflip_en) 1007{ 1008 /* Timing */ 1009 unsigned int htotal = e2e_pipe_param->pipe.dest.htotal; 1010 unsigned int hblank_end = e2e_pipe_param->pipe.dest.hblank_end; 1011 unsigned int vblank_start = e2e_pipe_param->pipe.dest.vblank_start; 1012 unsigned int vblank_end = e2e_pipe_param->pipe.dest.vblank_end; 1013 bool interlaced = e2e_pipe_param->pipe.dest.interlaced; 1014 unsigned int min_vblank = mode_lib->ip.min_vblank_lines; 1015 1016 double pclk_freq_in_mhz = e2e_pipe_param->pipe.dest.pixel_rate_mhz; 1017 double refclk_freq_in_mhz = e2e_pipe_param->clks_cfg.refclk_mhz; 1018 double dppclk_freq_in_mhz = e2e_pipe_param->clks_cfg.dppclk_mhz; 1019 double dispclk_freq_in_mhz = e2e_pipe_param->clks_cfg.dispclk_mhz; 1020 1021 double ref_freq_to_pix_freq; 1022 double prefetch_xy_calc_in_dcfclk; 1023 double min_dcfclk_mhz; 1024 double t_calc_us; 1025 double min_ttu_vblank; 1026 double min_dst_y_ttu_vblank; 1027 unsigned int dlg_vblank_start; 1028 bool dcc_en; 1029 bool dual_plane; 1030 bool mode_422; 1031 unsigned int access_dir; 1032 unsigned int bytes_per_element_l; 1033 unsigned int bytes_per_element_c; 1034 unsigned int vp_height_l; 1035 unsigned int vp_width_l; 1036 unsigned int vp_height_c; 1037 unsigned int vp_width_c; 1038 unsigned int htaps_l; 1039 unsigned int htaps_c; 1040 double hratios_l; 1041 double hratios_c; 1042 double vratio_l; 1043 double vratio_c; 1044 double line_time_in_us; 1045 double vinit_l; 1046 double vinit_c; 1047 double vinit_bot_l; 1048 double vinit_bot_c; 1049 unsigned int swath_height_l; 1050 unsigned int swath_width_ub_l; 1051 unsigned int dpte_bytes_per_row_ub_l; 1052 unsigned int dpte_groups_per_row_ub_l; 1053 unsigned int meta_pte_bytes_per_frame_ub_l; 1054 unsigned int meta_bytes_per_row_ub_l; 1055 unsigned int swath_height_c; 1056 unsigned int swath_width_ub_c; 1057 unsigned int dpte_bytes_per_row_ub_c; 1058 unsigned int dpte_groups_per_row_ub_c; 1059 unsigned int meta_chunks_per_row_ub_l; 1060 unsigned int vupdate_offset; 1061 unsigned int vupdate_width; 1062 unsigned int vready_offset; 1063 unsigned int dppclk_delay_subtotal; 1064 unsigned int dispclk_delay_subtotal; 1065 unsigned int pixel_rate_delay_subtotal; 1066 unsigned int vstartup_start; 1067 unsigned int dst_x_after_scaler; 1068 unsigned int dst_y_after_scaler; 1069 double line_wait; 1070 double line_o; 1071 double line_setup; 1072 double line_calc; 1073 double dst_y_prefetch; 1074 double t_pre_us; 1075 unsigned int vm_bytes; 1076 unsigned int meta_row_bytes; 1077 unsigned int max_num_sw_l; 1078 unsigned int max_num_sw_c; 1079 unsigned int max_partial_sw_l; 1080 unsigned int max_partial_sw_c; 1081 double max_vinit_l; 1082 double max_vinit_c; 1083 unsigned int lsw_l; 1084 unsigned int lsw_c; 1085 unsigned int sw_bytes_ub_l; 1086 unsigned int sw_bytes_ub_c; 1087 unsigned int sw_bytes; 1088 unsigned int dpte_row_bytes; 1089 double prefetch_bw; 1090 double flip_bw; 1091 double t_vm_us; 1092 double t_r0_us; 1093 double dst_y_per_vm_vblank; 1094 double dst_y_per_row_vblank; 1095 double min_dst_y_per_vm_vblank; 1096 double min_dst_y_per_row_vblank; 1097 double lsw; 1098 double vratio_pre_l; 1099 double vratio_pre_c; 1100 unsigned int req_per_swath_ub_l; 1101 unsigned int req_per_swath_ub_c; 1102 unsigned int meta_row_height_l; 1103 unsigned int swath_width_pixels_ub_l; 1104 unsigned int swath_width_pixels_ub_c; 1105 unsigned int scaler_rec_in_width_l; 1106 unsigned int scaler_rec_in_width_c; 1107 unsigned int dpte_row_height_l; 1108 unsigned int dpte_row_height_c; 1109 double hscale_pixel_rate_l; 1110 double hscale_pixel_rate_c; 1111 double min_hratio_fact_l; 1112 double min_hratio_fact_c; 1113 double refcyc_per_line_delivery_pre_l; 1114 double refcyc_per_line_delivery_pre_c; 1115 double refcyc_per_line_delivery_l; 1116 double refcyc_per_line_delivery_c; 1117 double refcyc_per_req_delivery_pre_l; 1118 double refcyc_per_req_delivery_pre_c; 1119 double refcyc_per_req_delivery_l; 1120 double refcyc_per_req_delivery_c; 1121 double refcyc_per_req_delivery_pre_cur0; 1122 double refcyc_per_req_delivery_cur0; 1123 unsigned int full_recout_width; 1124 double hratios_cur0; 1125 unsigned int cur0_src_width; 1126 enum cursor_bpp cur0_bpp; 1127 unsigned int cur0_req_size; 1128 unsigned int cur0_req_width; 1129 double cur0_width_ub; 1130 double cur0_req_per_width; 1131 double hactive_cur0; 1132 1133 memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); 1134 memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs)); 1135 1136 DTRACE("DLG: %s: cstate_en = %d", __func__, cstate_en); 1137 DTRACE("DLG: %s: pstate_en = %d", __func__, pstate_en); 1138 DTRACE("DLG: %s: vm_en = %d", __func__, vm_en); 1139 DTRACE("DLG: %s: iflip_en = %d", __func__, iflip_en); 1140 1141 /* ------------------------- */ 1142 /* Section 1.5.2.1: OTG dependent Params */ 1143 /* ------------------------- */ 1144 DTRACE("DLG: %s: dppclk_freq_in_mhz = %3.2f", __func__, dppclk_freq_in_mhz); 1145 DTRACE("DLG: %s: dispclk_freq_in_mhz = %3.2f", __func__, dispclk_freq_in_mhz); 1146 DTRACE("DLG: %s: refclk_freq_in_mhz = %3.2f", __func__, refclk_freq_in_mhz); 1147 DTRACE("DLG: %s: pclk_freq_in_mhz = %3.2f", __func__, pclk_freq_in_mhz); 1148 DTRACE("DLG: %s: interlaced = %d", __func__, interlaced); 1149 1150 ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; 1151 ASSERT(ref_freq_to_pix_freq < 4.0); 1152 disp_dlg_regs->ref_freq_to_pix_freq = 1153 (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); 1154 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal 1155 * dml_pow(2, 8)); 1156 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end 1157 * (double) ref_freq_to_pix_freq); 1158 ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13)); 1159 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; /* 15 bits */ 1160 1161 prefetch_xy_calc_in_dcfclk = 24.0; /* TODO: ip_param */ 1162 min_dcfclk_mhz = dlg_sys_param->deepsleep_dcfclk_mhz; 1163 t_calc_us = prefetch_xy_calc_in_dcfclk / min_dcfclk_mhz; 1164 min_ttu_vblank = dlg_sys_param->t_urg_wm_us; 1165 if (cstate_en) 1166 min_ttu_vblank = dml_max(dlg_sys_param->t_sr_wm_us, min_ttu_vblank); 1167 if (pstate_en) 1168 min_ttu_vblank = dml_max(dlg_sys_param->t_mclk_wm_us, min_ttu_vblank); 1169 min_ttu_vblank = min_ttu_vblank + t_calc_us; 1170 1171 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal; 1172 dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; 1173 1174 disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start 1175 + min_dst_y_ttu_vblank) * dml_pow(2, 2)); 1176 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18)); 1177 1178 DTRACE("DLG: %s: min_dcfclk_mhz = %3.2f", __func__, min_dcfclk_mhz); 1179 DTRACE("DLG: %s: min_ttu_vblank = %3.2f", __func__, min_ttu_vblank); 1180 DTRACE( 1181 "DLG: %s: min_dst_y_ttu_vblank = %3.2f", 1182 __func__, 1183 min_dst_y_ttu_vblank); 1184 DTRACE("DLG: %s: t_calc_us = %3.2f", __func__, t_calc_us); 1185 DTRACE( 1186 "DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x", 1187 __func__, 1188 disp_dlg_regs->min_dst_y_next_start); 1189 DTRACE( 1190 "DLG: %s: ref_freq_to_pix_freq = %3.2f", 1191 __func__, 1192 ref_freq_to_pix_freq); 1193 1194 /* ------------------------- */ 1195 /* Section 1.5.2.2: Prefetch, Active and TTU */ 1196 /* ------------------------- */ 1197 /* Prefetch Calc */ 1198 /* Source */ 1199 dcc_en = e2e_pipe_param->pipe.src.dcc; 1200 dual_plane = is_dual_plane( 1201 (enum source_format_class) e2e_pipe_param->pipe.src.source_format); 1202 mode_422 = 0; /* TODO */ 1203 access_dir = (e2e_pipe_param->pipe.src.source_scan == dm_vert); /* vp access direction: horizontal or vertical accessed */ 1204 bytes_per_element_l = get_bytes_per_element( 1205 (enum source_format_class) e2e_pipe_param->pipe.src.source_format, 1206 0); 1207 bytes_per_element_c = get_bytes_per_element( 1208 (enum source_format_class) e2e_pipe_param->pipe.src.source_format, 1209 1); 1210 vp_height_l = e2e_pipe_param->pipe.src.viewport_height; 1211 vp_width_l = e2e_pipe_param->pipe.src.viewport_width; 1212 vp_height_c = e2e_pipe_param->pipe.src.viewport_height_c; 1213 vp_width_c = e2e_pipe_param->pipe.src.viewport_width_c; 1214 1215 /* Scaling */ 1216 htaps_l = e2e_pipe_param->pipe.scale_taps.htaps; 1217 htaps_c = e2e_pipe_param->pipe.scale_taps.htaps_c; 1218 hratios_l = e2e_pipe_param->pipe.scale_ratio_depth.hscl_ratio; 1219 hratios_c = e2e_pipe_param->pipe.scale_ratio_depth.hscl_ratio_c; 1220 vratio_l = e2e_pipe_param->pipe.scale_ratio_depth.vscl_ratio; 1221 vratio_c = e2e_pipe_param->pipe.scale_ratio_depth.vscl_ratio_c; 1222 1223 line_time_in_us = (htotal / pclk_freq_in_mhz); 1224 vinit_l = e2e_pipe_param->pipe.scale_ratio_depth.vinit; 1225 vinit_c = e2e_pipe_param->pipe.scale_ratio_depth.vinit_c; 1226 vinit_bot_l = e2e_pipe_param->pipe.scale_ratio_depth.vinit_bot; 1227 vinit_bot_c = e2e_pipe_param->pipe.scale_ratio_depth.vinit_bot_c; 1228 1229 swath_height_l = rq_dlg_param->rq_l.swath_height; 1230 swath_width_ub_l = rq_dlg_param->rq_l.swath_width_ub; 1231 dpte_bytes_per_row_ub_l = rq_dlg_param->rq_l.dpte_bytes_per_row_ub; 1232 dpte_groups_per_row_ub_l = rq_dlg_param->rq_l.dpte_groups_per_row_ub; 1233 meta_pte_bytes_per_frame_ub_l = rq_dlg_param->rq_l.meta_pte_bytes_per_frame_ub; 1234 meta_bytes_per_row_ub_l = rq_dlg_param->rq_l.meta_bytes_per_row_ub; 1235 1236 swath_height_c = rq_dlg_param->rq_c.swath_height; 1237 swath_width_ub_c = rq_dlg_param->rq_c.swath_width_ub; 1238 dpte_bytes_per_row_ub_c = rq_dlg_param->rq_c.dpte_bytes_per_row_ub; 1239 dpte_groups_per_row_ub_c = rq_dlg_param->rq_c.dpte_groups_per_row_ub; 1240 1241 meta_chunks_per_row_ub_l = rq_dlg_param->rq_l.meta_chunks_per_row_ub; 1242 vupdate_offset = e2e_pipe_param->pipe.dest.vupdate_offset; 1243 vupdate_width = e2e_pipe_param->pipe.dest.vupdate_width; 1244 vready_offset = e2e_pipe_param->pipe.dest.vready_offset; 1245 1246 dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal; 1247 dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal; 1248 pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz 1249 + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; 1250 1251 vstartup_start = e2e_pipe_param->pipe.dest.vstartup_start; 1252 1253 if (interlaced) 1254 vstartup_start = vstartup_start / 2; 1255 1256 if (vstartup_start >= min_vblank) { 1257 DTRACE( 1258 "WARNING_DLG: %s: vblank_start=%d vblank_end=%d", 1259 __func__, 1260 vblank_start, 1261 vblank_end); 1262 DTRACE( 1263 "WARNING_DLG: %s: vstartup_start=%d should be less than min_vblank=%d", 1264 __func__, 1265 vstartup_start, 1266 min_vblank); 1267 min_vblank = vstartup_start + 1; 1268 DTRACE( 1269 "WARNING_DLG: %s: vstartup_start=%d should be less than min_vblank=%d", 1270 __func__, 1271 vstartup_start, 1272 min_vblank); 1273 } 1274 1275 dst_x_after_scaler = 0; 1276 dst_y_after_scaler = 0; 1277 1278 if (e2e_pipe_param->pipe.src.is_hsplit) 1279 dst_x_after_scaler = pixel_rate_delay_subtotal 1280 + e2e_pipe_param->pipe.dest.recout_width; 1281 else 1282 dst_x_after_scaler = pixel_rate_delay_subtotal; 1283 1284 if (e2e_pipe_param->dout.output_format == dm_420) 1285 dst_y_after_scaler = 1; 1286 else 1287 dst_y_after_scaler = 0; 1288 1289 if (dst_x_after_scaler >= htotal) { 1290 dst_x_after_scaler = dst_x_after_scaler - htotal; 1291 dst_y_after_scaler = dst_y_after_scaler + 1; 1292 } 1293 1294 DTRACE("DLG: %s: htotal = %d", __func__, htotal); 1295 DTRACE( 1296 "DLG: %s: pixel_rate_delay_subtotal = %d", 1297 __func__, 1298 pixel_rate_delay_subtotal); 1299 DTRACE("DLG: %s: dst_x_after_scaler = %d", __func__, dst_x_after_scaler); 1300 DTRACE("DLG: %s: dst_y_after_scaler = %d", __func__, dst_y_after_scaler); 1301 1302 line_wait = mode_lib->soc.urgent_latency_us; 1303 if (cstate_en) 1304 line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait); 1305 if (pstate_en) 1306 line_wait = dml_max( 1307 mode_lib->soc.dram_clock_change_latency_us 1308 + mode_lib->soc.urgent_latency_us, 1309 line_wait); 1310 line_wait = line_wait / line_time_in_us; 1311 1312 line_o = (double) dst_y_after_scaler + dst_x_after_scaler / (double) htotal; 1313 line_setup = (double) (vupdate_offset + vupdate_width + vready_offset) / (double) htotal; 1314 line_calc = t_calc_us / line_time_in_us; 1315 1316 DTRACE( 1317 "DLG: %s: soc.sr_enter_plus_exit_time_us = %3.2f", 1318 __func__, 1319 (double) mode_lib->soc.sr_enter_plus_exit_time_us); 1320 DTRACE( 1321 "DLG: %s: soc.dram_clock_change_latency_us = %3.2f", 1322 __func__, 1323 (double) mode_lib->soc.dram_clock_change_latency_us); 1324 DTRACE( 1325 "DLG: %s: soc.urgent_latency_us = %3.2f", 1326 __func__, 1327 mode_lib->soc.urgent_latency_us); 1328 1329 DTRACE("DLG: %s: swath_height_l = %d", __func__, swath_height_l); 1330 if (dual_plane) 1331 DTRACE("DLG: %s: swath_height_c = %d", __func__, swath_height_c); 1332 1333 DTRACE("DLG: %s: line_time_in_us = %3.2f", __func__, (double) line_time_in_us); 1334 DTRACE("DLG: %s: vupdate_offset = %d", __func__, vupdate_offset); 1335 DTRACE("DLG: %s: vupdate_width = %d", __func__, vupdate_width); 1336 DTRACE("DLG: %s: vready_offset = %d", __func__, vready_offset); 1337 DTRACE("DLG: %s: line_time_in_us = %3.2f", __func__, line_time_in_us); 1338 DTRACE("DLG: %s: line_wait = %3.2f", __func__, line_wait); 1339 DTRACE("DLG: %s: line_o = %3.2f", __func__, line_o); 1340 DTRACE("DLG: %s: line_setup = %3.2f", __func__, line_setup); 1341 DTRACE("DLG: %s: line_calc = %3.2f", __func__, line_calc); 1342 1343 dst_y_prefetch = ((double) min_vblank - 1.0) 1344 - (line_setup + line_calc + line_wait + line_o); 1345 DTRACE("DLG: %s: dst_y_prefetch (before rnd) = %3.2f", __func__, dst_y_prefetch); 1346 ASSERT(dst_y_prefetch >= 2.0); 1347 1348 dst_y_prefetch = dml_floor(4.0 * (dst_y_prefetch + 0.125), 1) / 4; 1349 DTRACE("DLG: %s: dst_y_prefetch (after rnd) = %3.2f", __func__, dst_y_prefetch); 1350 1351 t_pre_us = dst_y_prefetch * line_time_in_us; 1352 vm_bytes = 0; 1353 meta_row_bytes = 0; 1354 1355 if (dcc_en && vm_en) 1356 vm_bytes = meta_pte_bytes_per_frame_ub_l; 1357 if (dcc_en) 1358 meta_row_bytes = meta_bytes_per_row_ub_l; 1359 1360 max_num_sw_l = 0; 1361 max_num_sw_c = 0; 1362 max_partial_sw_l = 0; 1363 max_partial_sw_c = 0; 1364 1365 max_vinit_l = interlaced ? dml_max(vinit_l, vinit_bot_l) : vinit_l; 1366 max_vinit_c = interlaced ? dml_max(vinit_c, vinit_bot_c) : vinit_c; 1367 1368 get_swath_need(mode_lib, &max_num_sw_l, &max_partial_sw_l, swath_height_l, max_vinit_l); 1369 if (dual_plane) 1370 get_swath_need( 1371 mode_lib, 1372 &max_num_sw_c, 1373 &max_partial_sw_c, 1374 swath_height_c, 1375 max_vinit_c); 1376 1377 lsw_l = max_num_sw_l * swath_height_l + max_partial_sw_l; 1378 lsw_c = max_num_sw_c * swath_height_c + max_partial_sw_c; 1379 sw_bytes_ub_l = lsw_l * swath_width_ub_l * bytes_per_element_l; 1380 sw_bytes_ub_c = lsw_c * swath_width_ub_c * bytes_per_element_c; 1381 sw_bytes = 0; 1382 dpte_row_bytes = 0; 1383 1384 if (vm_en) { 1385 if (dual_plane) 1386 dpte_row_bytes = dpte_bytes_per_row_ub_l + dpte_bytes_per_row_ub_c; 1387 else 1388 dpte_row_bytes = dpte_bytes_per_row_ub_l; 1389 } else { 1390 dpte_row_bytes = 0; 1391 } 1392 1393 if (dual_plane) 1394 sw_bytes = sw_bytes_ub_l + sw_bytes_ub_c; 1395 else 1396 sw_bytes = sw_bytes_ub_l; 1397 1398 DTRACE("DLG: %s: sw_bytes_ub_l = %d", __func__, sw_bytes_ub_l); 1399 DTRACE("DLG: %s: sw_bytes_ub_c = %d", __func__, sw_bytes_ub_c); 1400 DTRACE("DLG: %s: sw_bytes = %d", __func__, sw_bytes); 1401 DTRACE("DLG: %s: vm_bytes = %d", __func__, vm_bytes); 1402 DTRACE("DLG: %s: meta_row_bytes = %d", __func__, meta_row_bytes); 1403 DTRACE("DLG: %s: dpte_row_bytes = %d", __func__, dpte_row_bytes); 1404 1405 prefetch_bw = (vm_bytes + 2 * dpte_row_bytes + 2 * meta_row_bytes + sw_bytes) / t_pre_us; 1406 flip_bw = ((vm_bytes + dpte_row_bytes + meta_row_bytes) * dlg_sys_param->total_flip_bw) 1407 / (double) dlg_sys_param->total_flip_bytes; 1408 t_vm_us = line_time_in_us / 4.0; 1409 if (vm_en && dcc_en) { 1410 t_vm_us = dml_max( 1411 dlg_sys_param->t_extra_us, 1412 dml_max((double) vm_bytes / prefetch_bw, t_vm_us)); 1413 1414 if (iflip_en && !dual_plane) { 1415 t_vm_us = dml_max(mode_lib->soc.urgent_latency_us, t_vm_us); 1416 if (flip_bw > 0.) 1417 t_vm_us = dml_max(vm_bytes / flip_bw, t_vm_us); 1418 } 1419 } 1420 1421 t_r0_us = dml_max(dlg_sys_param->t_extra_us - t_vm_us, line_time_in_us - t_vm_us); 1422 1423 if (vm_en || dcc_en) { 1424 t_r0_us = dml_max( 1425 (double) (dpte_row_bytes + meta_row_bytes) / prefetch_bw, 1426 dlg_sys_param->t_extra_us); 1427 t_r0_us = dml_max((double) (line_time_in_us - t_vm_us), t_r0_us); 1428 1429 if (iflip_en && !dual_plane) { 1430 t_r0_us = dml_max(mode_lib->soc.urgent_latency_us * 2.0, t_r0_us); 1431 if (flip_bw > 0.) 1432 t_r0_us = dml_max( 1433 (dpte_row_bytes + meta_row_bytes) / flip_bw, 1434 t_r0_us); 1435 } 1436 } 1437 1438 disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; /* in terms of line */ 1439 disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; /* in terms of refclk */ 1440 ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13)); 1441 DTRACE( 1442 "DLG: %s: disp_dlg_regs->dst_y_after_scaler = 0x%0x", 1443 __func__, 1444 disp_dlg_regs->dst_y_after_scaler); 1445 DTRACE( 1446 "DLG: %s: disp_dlg_regs->refcyc_x_after_scaler = 0x%0x", 1447 __func__, 1448 disp_dlg_regs->refcyc_x_after_scaler); 1449 1450 disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); 1451 DTRACE( 1452 "DLG: %s: disp_dlg_regs->dst_y_prefetch = %d", 1453 __func__, 1454 disp_dlg_regs->dst_y_prefetch); 1455 1456 dst_y_per_vm_vblank = 0.0; 1457 dst_y_per_row_vblank = 0.0; 1458 1459 dst_y_per_vm_vblank = t_vm_us / line_time_in_us; 1460 dst_y_per_vm_vblank = dml_floor(4.0 * (dst_y_per_vm_vblank + 0.125), 1) / 4.0; 1461 disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); 1462 1463 dst_y_per_row_vblank = t_r0_us / line_time_in_us; 1464 dst_y_per_row_vblank = dml_floor(4.0 * (dst_y_per_row_vblank + 0.125), 1) / 4.0; 1465 disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); 1466 1467 DTRACE("DLG: %s: lsw_l = %d", __func__, lsw_l); 1468 DTRACE("DLG: %s: lsw_c = %d", __func__, lsw_c); 1469 DTRACE("DLG: %s: dpte_bytes_per_row_ub_l = %d", __func__, dpte_bytes_per_row_ub_l); 1470 DTRACE("DLG: %s: dpte_bytes_per_row_ub_c = %d", __func__, dpte_bytes_per_row_ub_c); 1471 1472 DTRACE("DLG: %s: prefetch_bw = %3.2f", __func__, prefetch_bw); 1473 DTRACE("DLG: %s: flip_bw = %3.2f", __func__, flip_bw); 1474 DTRACE("DLG: %s: t_pre_us = %3.2f", __func__, t_pre_us); 1475 DTRACE("DLG: %s: t_vm_us = %3.2f", __func__, t_vm_us); 1476 DTRACE("DLG: %s: t_r0_us = %3.2f", __func__, t_r0_us); 1477 DTRACE("DLG: %s: dst_y_per_vm_vblank = %3.2f", __func__, dst_y_per_vm_vblank); 1478 DTRACE("DLG: %s: dst_y_per_row_vblank = %3.2f", __func__, dst_y_per_row_vblank); 1479 DTRACE("DLG: %s: dst_y_prefetch = %3.2f", __func__, dst_y_prefetch); 1480 1481 min_dst_y_per_vm_vblank = 8.0; 1482 min_dst_y_per_row_vblank = 16.0; 1483 if (htotal <= 75) { 1484 min_vblank = 300; 1485 min_dst_y_per_vm_vblank = 100.0; 1486 min_dst_y_per_row_vblank = 100.0; 1487 } 1488 1489 ASSERT(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank); 1490 ASSERT(dst_y_per_row_vblank < min_dst_y_per_row_vblank); 1491 1492 ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank)); 1493 lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank); 1494 1495 DTRACE("DLG: %s: lsw = %3.2f", __func__, lsw); 1496 1497 vratio_pre_l = get_vratio_pre( 1498 mode_lib, 1499 max_num_sw_l, 1500 max_partial_sw_l, 1501 swath_height_l, 1502 max_vinit_l, 1503 lsw); 1504 vratio_pre_c = 1.0; 1505 if (dual_plane) 1506 vratio_pre_c = get_vratio_pre( 1507 mode_lib, 1508 max_num_sw_c, 1509 max_partial_sw_c, 1510 swath_height_c, 1511 max_vinit_c, 1512 lsw); 1513 1514 DTRACE("DLG: %s: vratio_pre_l=%3.2f", __func__, vratio_pre_l); 1515 DTRACE("DLG: %s: vratio_pre_c=%3.2f", __func__, vratio_pre_c); 1516 1517 ASSERT(vratio_pre_l <= 4.0); 1518 if (vratio_pre_l >= 4.0) 1519 disp_dlg_regs->vratio_prefetch = (unsigned int) dml_pow(2, 21) - 1; 1520 else 1521 disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); 1522 1523 ASSERT(vratio_pre_c <= 4.0); 1524 if (vratio_pre_c >= 4.0) 1525 disp_dlg_regs->vratio_prefetch_c = (unsigned int) dml_pow(2, 21) - 1; 1526 else 1527 disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); 1528 1529 disp_dlg_regs->refcyc_per_pte_group_vblank_l = 1530 (unsigned int) (dst_y_per_row_vblank * (double) htotal 1531 * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); 1532 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13)); 1533 1534 disp_dlg_regs->refcyc_per_pte_group_vblank_c = 1535 (unsigned int) (dst_y_per_row_vblank * (double) htotal 1536 * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_c); 1537 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int) dml_pow(2, 13)); 1538 1539 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = 1540 (unsigned int) (dst_y_per_row_vblank * (double) htotal 1541 * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); 1542 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); 1543 1544 disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = 1545 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l;/* dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now */ 1546 1547 /* Active */ 1548 req_per_swath_ub_l = rq_dlg_param->rq_l.req_per_swath_ub; 1549 req_per_swath_ub_c = rq_dlg_param->rq_c.req_per_swath_ub; 1550 meta_row_height_l = rq_dlg_param->rq_l.meta_row_height; 1551 swath_width_pixels_ub_l = 0; 1552 swath_width_pixels_ub_c = 0; 1553 scaler_rec_in_width_l = 0; 1554 scaler_rec_in_width_c = 0; 1555 dpte_row_height_l = rq_dlg_param->rq_l.dpte_row_height; 1556 dpte_row_height_c = rq_dlg_param->rq_c.dpte_row_height; 1557 1558 disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l 1559 / (double) vratio_l * dml_pow(2, 2)); 1560 ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17)); 1561 1562 disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c 1563 / (double) vratio_c * dml_pow(2, 2)); 1564 ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_c < (unsigned int) dml_pow(2, 17)); 1565 1566 disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l 1567 / (double) vratio_l * dml_pow(2, 2)); 1568 ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17)); 1569 1570 disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; /* dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now */ 1571 1572 disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l 1573 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq 1574 / (double) dpte_groups_per_row_ub_l); 1575 if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) 1576 disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; 1577 1578 disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int) ((double) dpte_row_height_c 1579 / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq 1580 / (double) dpte_groups_per_row_ub_c); 1581 if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) 1582 disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; 1583 1584 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l 1585 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq 1586 / (double) meta_chunks_per_row_ub_l); 1587 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) 1588 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; 1589 1590 if (mode_422) { 1591 swath_width_pixels_ub_l = swath_width_ub_l * 2; /* *2 for 2 pixel per element */ 1592 swath_width_pixels_ub_c = swath_width_ub_c * 2; 1593 } else { 1594 swath_width_pixels_ub_l = swath_width_ub_l * 1; 1595 swath_width_pixels_ub_c = swath_width_ub_c * 1; 1596 } 1597 1598 if (htaps_l <= 1) 1599 min_hratio_fact_l = 2.0; 1600 else if (htaps_l <= 6) { 1601 if ((hratios_l * 2.0) > 4.0) 1602 min_hratio_fact_l = 4.0; 1603 else 1604 min_hratio_fact_l = hratios_l * 2.0; 1605 } else { 1606 if (hratios_l > 4.0) 1607 min_hratio_fact_l = 4.0; 1608 else 1609 min_hratio_fact_l = hratios_l; 1610 } 1611 1612 hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz; 1613 1614 if (htaps_c <= 1) 1615 min_hratio_fact_c = 2.0; 1616 else if (htaps_c <= 6) { 1617 if ((hratios_c * 2.0) > 4.0) 1618 min_hratio_fact_c = 4.0; 1619 else 1620 min_hratio_fact_c = hratios_c * 2.0; 1621 } else { 1622 if (hratios_c > 4.0) 1623 min_hratio_fact_c = 4.0; 1624 else 1625 min_hratio_fact_c = hratios_c; 1626 } 1627 1628 hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz; 1629 1630 refcyc_per_line_delivery_pre_l = 0.; 1631 refcyc_per_line_delivery_pre_c = 0.; 1632 refcyc_per_line_delivery_l = 0.; 1633 refcyc_per_line_delivery_c = 0.; 1634 1635 refcyc_per_req_delivery_pre_l = 0.; 1636 refcyc_per_req_delivery_pre_c = 0.; 1637 refcyc_per_req_delivery_l = 0.; 1638 refcyc_per_req_delivery_c = 0.; 1639 refcyc_per_req_delivery_pre_cur0 = 0.; 1640 refcyc_per_req_delivery_cur0 = 0.; 1641 1642 full_recout_width = 0; 1643 if (e2e_pipe_param->pipe.src.is_hsplit) { 1644 if (e2e_pipe_param->pipe.dest.full_recout_width == 0) { 1645 DTRACE("DLG: %s: Warningfull_recout_width not set in hsplit mode", __func__); 1646 full_recout_width = e2e_pipe_param->pipe.dest.recout_width * 2; /* assume half split for dcn1 */ 1647 } else 1648 full_recout_width = e2e_pipe_param->pipe.dest.full_recout_width; 1649 } else 1650 full_recout_width = e2e_pipe_param->pipe.dest.recout_width; 1651 1652 refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery( 1653 mode_lib, 1654 refclk_freq_in_mhz, 1655 pclk_freq_in_mhz, 1656 full_recout_width, 1657 vratio_pre_l, 1658 hscale_pixel_rate_l, 1659 swath_width_pixels_ub_l, 1660 1); /* per line */ 1661 1662 refcyc_per_line_delivery_l = get_refcyc_per_delivery( 1663 mode_lib, 1664 refclk_freq_in_mhz, 1665 pclk_freq_in_mhz, 1666 full_recout_width, 1667 vratio_l, 1668 hscale_pixel_rate_l, 1669 swath_width_pixels_ub_l, 1670 1); /* per line */ 1671 1672 DTRACE("DLG: %s: full_recout_width = %d", __func__, full_recout_width); 1673 DTRACE("DLG: %s: hscale_pixel_rate_l = %3.2f", __func__, hscale_pixel_rate_l); 1674 DTRACE( 1675 "DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f", 1676 __func__, 1677 refcyc_per_line_delivery_pre_l); 1678 DTRACE( 1679 "DLG: %s: refcyc_per_line_delivery_l = %3.2f", 1680 __func__, 1681 refcyc_per_line_delivery_l); 1682 1683 disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor( 1684 refcyc_per_line_delivery_pre_l, 1685 1); 1686 disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor( 1687 refcyc_per_line_delivery_l, 1688 1); 1689 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13)); 1690 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13)); 1691 1692 if (dual_plane) { 1693 refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery( 1694 mode_lib, 1695 refclk_freq_in_mhz, 1696 pclk_freq_in_mhz, 1697 full_recout_width, 1698 vratio_pre_c, 1699 hscale_pixel_rate_c, 1700 swath_width_pixels_ub_c, 1701 1); /* per line */ 1702 1703 refcyc_per_line_delivery_c = get_refcyc_per_delivery( 1704 mode_lib, 1705 refclk_freq_in_mhz, 1706 pclk_freq_in_mhz, 1707 full_recout_width, 1708 vratio_c, 1709 hscale_pixel_rate_c, 1710 swath_width_pixels_ub_c, 1711 1); /* per line */ 1712 1713 DTRACE( 1714 "DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f", 1715 __func__, 1716 refcyc_per_line_delivery_pre_c); 1717 DTRACE( 1718 "DLG: %s: refcyc_per_line_delivery_c = %3.2f", 1719 __func__, 1720 refcyc_per_line_delivery_c); 1721 1722 disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor( 1723 refcyc_per_line_delivery_pre_c, 1724 1); 1725 disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor( 1726 refcyc_per_line_delivery_c, 1727 1); 1728 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13)); 1729 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13)); 1730 } 1731 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; 1732 1733 /* TTU - Luma / Chroma */ 1734 if (access_dir) { /* vertical access */ 1735 scaler_rec_in_width_l = vp_height_l; 1736 scaler_rec_in_width_c = vp_height_c; 1737 } else { 1738 scaler_rec_in_width_l = vp_width_l; 1739 scaler_rec_in_width_c = vp_width_c; 1740 } 1741 1742 refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery( 1743 mode_lib, 1744 refclk_freq_in_mhz, 1745 pclk_freq_in_mhz, 1746 full_recout_width, 1747 vratio_pre_l, 1748 hscale_pixel_rate_l, 1749 scaler_rec_in_width_l, 1750 req_per_swath_ub_l); /* per req */ 1751 refcyc_per_req_delivery_l = get_refcyc_per_delivery( 1752 mode_lib, 1753 refclk_freq_in_mhz, 1754 pclk_freq_in_mhz, 1755 full_recout_width, 1756 vratio_l, 1757 hscale_pixel_rate_l, 1758 scaler_rec_in_width_l, 1759 req_per_swath_ub_l); /* per req */ 1760 1761 DTRACE( 1762 "DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f", 1763 __func__, 1764 refcyc_per_req_delivery_pre_l); 1765 DTRACE( 1766 "DLG: %s: refcyc_per_req_delivery_l = %3.2f", 1767 __func__, 1768 refcyc_per_req_delivery_l); 1769 1770 disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l 1771 * dml_pow(2, 10)); 1772 disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l 1773 * dml_pow(2, 10)); 1774 1775 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); 1776 ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); 1777 1778 if (dual_plane) { 1779 refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery( 1780 mode_lib, 1781 refclk_freq_in_mhz, 1782 pclk_freq_in_mhz, 1783 full_recout_width, 1784 vratio_pre_c, 1785 hscale_pixel_rate_c, 1786 scaler_rec_in_width_c, 1787 req_per_swath_ub_c); /* per req */ 1788 refcyc_per_req_delivery_c = get_refcyc_per_delivery( 1789 mode_lib, 1790 refclk_freq_in_mhz, 1791 pclk_freq_in_mhz, 1792 full_recout_width, 1793 vratio_c, 1794 hscale_pixel_rate_c, 1795 scaler_rec_in_width_c, 1796 req_per_swath_ub_c); /* per req */ 1797 1798 DTRACE( 1799 "DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f", 1800 __func__, 1801 refcyc_per_req_delivery_pre_c); 1802 DTRACE( 1803 "DLG: %s: refcyc_per_req_delivery_c = %3.2f", 1804 __func__, 1805 refcyc_per_req_delivery_c); 1806 1807 disp_ttu_regs->refcyc_per_req_delivery_pre_c = 1808 (unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10)); 1809 disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c 1810 * dml_pow(2, 10)); 1811 1812 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); 1813 ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); 1814 } 1815 1816 /* TTU - Cursor */ 1817 hratios_cur0 = e2e_pipe_param->pipe.scale_ratio_depth.hscl_ratio; 1818 cur0_src_width = e2e_pipe_param->pipe.src.cur0_src_width; /* cursor source width */ 1819 cur0_bpp = (enum cursor_bpp) e2e_pipe_param->pipe.src.cur0_bpp; 1820 cur0_req_size = 0; 1821 cur0_req_width = 0; 1822 cur0_width_ub = 0.0; 1823 cur0_req_per_width = 0.0; 1824 hactive_cur0 = 0.0; 1825 1826 ASSERT(cur0_src_width <= 256); 1827 1828 if (cur0_src_width > 0) { 1829 unsigned int cur0_bit_per_pixel = 0; 1830 1831 if (cur0_bpp == dm_cur_2bit) { 1832 cur0_req_size = 64; /* byte */ 1833 cur0_bit_per_pixel = 2; 1834 } else { /* 32bit */ 1835 cur0_bit_per_pixel = 32; 1836 if (cur0_src_width >= 1 && cur0_src_width <= 16) 1837 cur0_req_size = 64; 1838 else if (cur0_src_width >= 17 && cur0_src_width <= 31) 1839 cur0_req_size = 128; 1840 else 1841 cur0_req_size = 256; 1842 } 1843 1844 cur0_req_width = (double) cur0_req_size / ((double) cur0_bit_per_pixel / 8.0); 1845 cur0_width_ub = dml_ceil((double) cur0_src_width / (double) cur0_req_width, 1) 1846 * (double) cur0_req_width; 1847 cur0_req_per_width = cur0_width_ub / (double) cur0_req_width; 1848 hactive_cur0 = (double) cur0_src_width / hratios_cur0; /* TODO: oswin to think about what to do for cursor */ 1849 1850 if (vratio_pre_l <= 1.0) { 1851 refcyc_per_req_delivery_pre_cur0 = hactive_cur0 * ref_freq_to_pix_freq 1852 / (double) cur0_req_per_width; 1853 } else { 1854 refcyc_per_req_delivery_pre_cur0 = (double) refclk_freq_in_mhz 1855 * (double) cur0_src_width / hscale_pixel_rate_l 1856 / (double) cur0_req_per_width; 1857 } 1858 1859 disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = 1860 (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); 1861 ASSERT(refcyc_per_req_delivery_pre_cur0 < dml_pow(2, 13)); 1862 1863 if (vratio_l <= 1.0) { 1864 refcyc_per_req_delivery_cur0 = hactive_cur0 * ref_freq_to_pix_freq 1865 / (double) cur0_req_per_width; 1866 } else { 1867 refcyc_per_req_delivery_cur0 = (double) refclk_freq_in_mhz 1868 * (double) cur0_src_width / hscale_pixel_rate_l 1869 / (double) cur0_req_per_width; 1870 } 1871 1872 DTRACE("DLG: %s: cur0_req_width = %d", __func__, cur0_req_width); 1873 DTRACE( 1874 "DLG: %s: cur0_width_ub = %3.2f", 1875 __func__, 1876 cur0_width_ub); 1877 DTRACE( 1878 "DLG: %s: cur0_req_per_width = %3.2f", 1879 __func__, 1880 cur0_req_per_width); 1881 DTRACE( 1882 "DLG: %s: hactive_cur0 = %3.2f", 1883 __func__, 1884 hactive_cur0); 1885 DTRACE( 1886 "DLG: %s: refcyc_per_req_delivery_pre_cur0 = %3.2f", 1887 __func__, 1888 refcyc_per_req_delivery_pre_cur0); 1889 DTRACE( 1890 "DLG: %s: refcyc_per_req_delivery_cur0 = %3.2f", 1891 __func__, 1892 refcyc_per_req_delivery_cur0); 1893 1894 disp_ttu_regs->refcyc_per_req_delivery_cur0 = 1895 (unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10)); 1896 ASSERT(refcyc_per_req_delivery_cur0 < dml_pow(2, 13)); 1897 } else { 1898 disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = 0; 1899 disp_ttu_regs->refcyc_per_req_delivery_cur0 = 0; 1900 } 1901 1902 /* TTU - Misc */ 1903 disp_ttu_regs->qos_level_low_wm = 0; 1904 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); 1905 disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal 1906 * ref_freq_to_pix_freq); 1907 ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14)); 1908 1909 disp_ttu_regs->qos_level_flip = 14; 1910 disp_ttu_regs->qos_level_fixed_l = 8; 1911 disp_ttu_regs->qos_level_fixed_c = 8; 1912 disp_ttu_regs->qos_level_fixed_cur0 = 8; 1913 disp_ttu_regs->qos_ramp_disable_l = 0; 1914 disp_ttu_regs->qos_ramp_disable_c = 0; 1915 disp_ttu_regs->qos_ramp_disable_cur0 = 0; 1916 1917 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; 1918 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); 1919 1920 print__ttu_regs_st(mode_lib, disp_ttu_regs); 1921 print__dlg_regs_st(mode_lib, disp_dlg_regs); 1922}
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