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display_rq_dlg_helpers.c
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linux-6.19.14/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c
1/* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#include "display_rq_dlg_helpers.h" 27#include "dml_logger.h" 28 29void print__rq_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_rq_params_st *rq_param) 30{ 31 dml_print("DML_RQ_DLG_CALC: ***************************\n"); 32 dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST\n"); 33 dml_print("DML_RQ_DLG_CALC: <LUMA>\n"); 34 print__data_rq_sizing_params_st(mode_lib, &rq_param->sizing.rq_l); 35 dml_print("DML_RQ_DLG_CALC: <CHROMA> ===\n"); 36 print__data_rq_sizing_params_st(mode_lib, &rq_param->sizing.rq_c); 37 38 dml_print("DML_RQ_DLG_CALC: <LUMA>\n"); 39 print__data_rq_dlg_params_st(mode_lib, &rq_param->dlg.rq_l); 40 dml_print("DML_RQ_DLG_CALC: <CHROMA>\n"); 41 print__data_rq_dlg_params_st(mode_lib, &rq_param->dlg.rq_c); 42 43 dml_print("DML_RQ_DLG_CALC: <LUMA>\n"); 44 print__data_rq_misc_params_st(mode_lib, &rq_param->misc.rq_l); 45 dml_print("DML_RQ_DLG_CALC: <CHROMA>\n"); 46 print__data_rq_misc_params_st(mode_lib, &rq_param->misc.rq_c); 47 dml_print("DML_RQ_DLG_CALC: ***************************\n"); 48} 49 50void print__data_rq_sizing_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_sizing_params_st *rq_sizing) 51{ 52 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 53 dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST\n"); 54 dml_print("DML_RQ_DLG_CALC: chunk_bytes = %0d\n", rq_sizing->chunk_bytes); 55 dml_print("DML_RQ_DLG_CALC: min_chunk_bytes = %0d\n", rq_sizing->min_chunk_bytes); 56 dml_print("DML_RQ_DLG_CALC: meta_chunk_bytes = %0d\n", rq_sizing->meta_chunk_bytes); 57 dml_print( 58 "DML_RQ_DLG_CALC: min_meta_chunk_bytes = %0d\n", 59 rq_sizing->min_meta_chunk_bytes); 60 dml_print("DML_RQ_DLG_CALC: mpte_group_bytes = %0d\n", rq_sizing->mpte_group_bytes); 61 dml_print("DML_RQ_DLG_CALC: dpte_group_bytes = %0d\n", rq_sizing->dpte_group_bytes); 62 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 63} 64 65void print__data_rq_dlg_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_dlg_params_st *rq_dlg_param) 66{ 67 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 68 dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST\n"); 69 dml_print( 70 "DML_RQ_DLG_CALC: swath_width_ub = %0d\n", 71 rq_dlg_param->swath_width_ub); 72 dml_print( 73 "DML_RQ_DLG_CALC: swath_height = %0d\n", 74 rq_dlg_param->swath_height); 75 dml_print( 76 "DML_RQ_DLG_CALC: req_per_swath_ub = %0d\n", 77 rq_dlg_param->req_per_swath_ub); 78 dml_print( 79 "DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = %0d\n", 80 rq_dlg_param->meta_pte_bytes_per_frame_ub); 81 dml_print( 82 "DML_RQ_DLG_CALC: dpte_req_per_row_ub = %0d\n", 83 rq_dlg_param->dpte_req_per_row_ub); 84 dml_print( 85 "DML_RQ_DLG_CALC: dpte_groups_per_row_ub = %0d\n", 86 rq_dlg_param->dpte_groups_per_row_ub); 87 dml_print( 88 "DML_RQ_DLG_CALC: dpte_row_height = %0d\n", 89 rq_dlg_param->dpte_row_height); 90 dml_print( 91 "DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = %0d\n", 92 rq_dlg_param->dpte_bytes_per_row_ub); 93 dml_print( 94 "DML_RQ_DLG_CALC: meta_chunks_per_row_ub = %0d\n", 95 rq_dlg_param->meta_chunks_per_row_ub); 96 dml_print( 97 "DML_RQ_DLG_CALC: meta_req_per_row_ub = %0d\n", 98 rq_dlg_param->meta_req_per_row_ub); 99 dml_print( 100 "DML_RQ_DLG_CALC: meta_row_height = %0d\n", 101 rq_dlg_param->meta_row_height); 102 dml_print( 103 "DML_RQ_DLG_CALC: meta_bytes_per_row_ub = %0d\n", 104 rq_dlg_param->meta_bytes_per_row_ub); 105 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 106} 107 108void print__data_rq_misc_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_misc_params_st *rq_misc_param) 109{ 110 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 111 dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST\n"); 112 dml_print( 113 "DML_RQ_DLG_CALC: full_swath_bytes = %0d\n", 114 rq_misc_param->full_swath_bytes); 115 dml_print( 116 "DML_RQ_DLG_CALC: stored_swath_bytes = %0d\n", 117 rq_misc_param->stored_swath_bytes); 118 dml_print("DML_RQ_DLG_CALC: blk256_width = %0d\n", rq_misc_param->blk256_width); 119 dml_print("DML_RQ_DLG_CALC: blk256_height = %0d\n", rq_misc_param->blk256_height); 120 dml_print("DML_RQ_DLG_CALC: req_width = %0d\n", rq_misc_param->req_width); 121 dml_print("DML_RQ_DLG_CALC: req_height = %0d\n", rq_misc_param->req_height); 122 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 123} 124 125void print__dlg_sys_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_dlg_sys_params_st *dlg_sys_param) 126{ 127 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 128 dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST\n"); 129 dml_print("DML_RQ_DLG_CALC: t_mclk_wm_us = %3.2f\n", dlg_sys_param->t_mclk_wm_us); 130 dml_print("DML_RQ_DLG_CALC: t_urg_wm_us = %3.2f\n", dlg_sys_param->t_urg_wm_us); 131 dml_print("DML_RQ_DLG_CALC: t_sr_wm_us = %3.2f\n", dlg_sys_param->t_sr_wm_us); 132 dml_print("DML_RQ_DLG_CALC: t_extra_us = %3.2f\n", dlg_sys_param->t_extra_us); 133 dml_print( 134 "DML_RQ_DLG_CALC: deepsleep_dcfclk_mhz = %3.2f\n", 135 dlg_sys_param->deepsleep_dcfclk_mhz); 136 dml_print( 137 "DML_RQ_DLG_CALC: total_flip_bw = %3.2f\n", 138 dlg_sys_param->total_flip_bw); 139 dml_print( 140 "DML_RQ_DLG_CALC: total_flip_bytes = %i\n", 141 dlg_sys_param->total_flip_bytes); 142 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 143} 144 145void print__data_rq_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_regs_st *rq_regs) 146{ 147 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 148 dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST\n"); 149 dml_print("DML_RQ_DLG_CALC: chunk_size = 0x%0x\n", rq_regs->chunk_size); 150 dml_print("DML_RQ_DLG_CALC: min_chunk_size = 0x%0x\n", rq_regs->min_chunk_size); 151 dml_print("DML_RQ_DLG_CALC: meta_chunk_size = 0x%0x\n", rq_regs->meta_chunk_size); 152 dml_print( 153 "DML_RQ_DLG_CALC: min_meta_chunk_size = 0x%0x\n", 154 rq_regs->min_meta_chunk_size); 155 dml_print("DML_RQ_DLG_CALC: dpte_group_size = 0x%0x\n", rq_regs->dpte_group_size); 156 dml_print("DML_RQ_DLG_CALC: mpte_group_size = 0x%0x\n", rq_regs->mpte_group_size); 157 dml_print("DML_RQ_DLG_CALC: swath_height = 0x%0x\n", rq_regs->swath_height); 158 dml_print( 159 "DML_RQ_DLG_CALC: pte_row_height_linear = 0x%0x\n", 160 rq_regs->pte_row_height_linear); 161 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 162} 163 164void print__rq_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_rq_regs_st *rq_regs) 165{ 166 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 167 dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_REGS_ST\n"); 168 dml_print("DML_RQ_DLG_CALC: <LUMA>\n"); 169 print__data_rq_regs_st(mode_lib, &rq_regs->rq_regs_l); 170 dml_print("DML_RQ_DLG_CALC: <CHROMA>\n"); 171 print__data_rq_regs_st(mode_lib, &rq_regs->rq_regs_c); 172 dml_print("DML_RQ_DLG_CALC: drq_expansion_mode = 0x%0x\n", rq_regs->drq_expansion_mode); 173 dml_print("DML_RQ_DLG_CALC: prq_expansion_mode = 0x%0x\n", rq_regs->prq_expansion_mode); 174 dml_print("DML_RQ_DLG_CALC: mrq_expansion_mode = 0x%0x\n", rq_regs->mrq_expansion_mode); 175 dml_print("DML_RQ_DLG_CALC: crq_expansion_mode = 0x%0x\n", rq_regs->crq_expansion_mode); 176 dml_print("DML_RQ_DLG_CALC: plane1_base_address = 0x%0x\n", rq_regs->plane1_base_address); 177 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 178} 179 180void print__dlg_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_dlg_regs_st *dlg_regs) 181{ 182 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 183 dml_print("DML_RQ_DLG_CALC: DISPLAY_DLG_REGS_ST\n"); 184 dml_print( 185 "DML_RQ_DLG_CALC: refcyc_h_blank_end = 0x%0x\n", 186 dlg_regs->refcyc_h_blank_end); 187 dml_print( 188 "DML_RQ_DLG_CALC: dlg_vblank_end = 0x%0x\n", 189 dlg_regs->dlg_vblank_end); 190 dml_print( 191 "DML_RQ_DLG_CALC: min_dst_y_next_start = 0x%0x\n", 192 dlg_regs->min_dst_y_next_start); 193 dml_print( 194 "DML_RQ_DLG_CALC: refcyc_per_htotal = 0x%0x\n", 195 dlg_regs->refcyc_per_htotal); 196 dml_print( 197 "DML_RQ_DLG_CALC: refcyc_x_after_scaler = 0x%0x\n", 198 dlg_regs->refcyc_x_after_scaler); 199 dml_print( 200 "DML_RQ_DLG_CALC: dst_y_after_scaler = 0x%0x\n", 201 dlg_regs->dst_y_after_scaler); 202 dml_print( 203 "DML_RQ_DLG_CALC: dst_y_prefetch = 0x%0x\n", 204 dlg_regs->dst_y_prefetch); 205 dml_print( 206 "DML_RQ_DLG_CALC: dst_y_per_vm_vblank = 0x%0x\n", 207 dlg_regs->dst_y_per_vm_vblank); 208 dml_print( 209 "DML_RQ_DLG_CALC: dst_y_per_row_vblank = 0x%0x\n", 210 dlg_regs->dst_y_per_row_vblank); 211 dml_print( 212 "DML_RQ_DLG_CALC: dst_y_per_vm_flip = 0x%0x\n", 213 dlg_regs->dst_y_per_vm_flip); 214 dml_print( 215 "DML_RQ_DLG_CALC: dst_y_per_row_flip = 0x%0x\n", 216 dlg_regs->dst_y_per_row_flip); 217 dml_print( 218 "DML_RQ_DLG_CALC: ref_freq_to_pix_freq = 0x%0x\n", 219 dlg_regs->ref_freq_to_pix_freq); 220 dml_print( 221 "DML_RQ_DLG_CALC: vratio_prefetch = 0x%0x\n", 222 dlg_regs->vratio_prefetch); 223 dml_print( 224 "DML_RQ_DLG_CALC: vratio_prefetch_c = 0x%0x\n", 225 dlg_regs->vratio_prefetch_c); 226 dml_print( 227 "DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_l = 0x%0x\n", 228 dlg_regs->refcyc_per_pte_group_vblank_l); 229 dml_print( 230 "DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_c = 0x%0x\n", 231 dlg_regs->refcyc_per_pte_group_vblank_c); 232 dml_print( 233 "DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_l = 0x%0x\n", 234 dlg_regs->refcyc_per_meta_chunk_vblank_l); 235 dml_print( 236 "DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_c = 0x%0x\n", 237 dlg_regs->refcyc_per_meta_chunk_vblank_c); 238 dml_print( 239 "DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_l = 0x%0x\n", 240 dlg_regs->refcyc_per_pte_group_flip_l); 241 dml_print( 242 "DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_c = 0x%0x\n", 243 dlg_regs->refcyc_per_pte_group_flip_c); 244 dml_print( 245 "DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_l = 0x%0x\n", 246 dlg_regs->refcyc_per_meta_chunk_flip_l); 247 dml_print( 248 "DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_c = 0x%0x\n", 249 dlg_regs->refcyc_per_meta_chunk_flip_c); 250 dml_print( 251 "DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_l = 0x%0x\n", 252 dlg_regs->dst_y_per_pte_row_nom_l); 253 dml_print( 254 "DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_c = 0x%0x\n", 255 dlg_regs->dst_y_per_pte_row_nom_c); 256 dml_print( 257 "DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_l = 0x%0x\n", 258 dlg_regs->refcyc_per_pte_group_nom_l); 259 dml_print( 260 "DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_c = 0x%0x\n", 261 dlg_regs->refcyc_per_pte_group_nom_c); 262 dml_print( 263 "DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_l = 0x%0x\n", 264 dlg_regs->dst_y_per_meta_row_nom_l); 265 dml_print( 266 "DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_c = 0x%0x\n", 267 dlg_regs->dst_y_per_meta_row_nom_c); 268 dml_print( 269 "DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_l = 0x%0x\n", 270 dlg_regs->refcyc_per_meta_chunk_nom_l); 271 dml_print( 272 "DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_c = 0x%0x\n", 273 dlg_regs->refcyc_per_meta_chunk_nom_c); 274 dml_print( 275 "DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_l = 0x%0x\n", 276 dlg_regs->refcyc_per_line_delivery_pre_l); 277 dml_print( 278 "DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_c = 0x%0x\n", 279 dlg_regs->refcyc_per_line_delivery_pre_c); 280 dml_print( 281 "DML_RQ_DLG_CALC: refcyc_per_line_delivery_l = 0x%0x\n", 282 dlg_regs->refcyc_per_line_delivery_l); 283 dml_print( 284 "DML_RQ_DLG_CALC: refcyc_per_line_delivery_c = 0x%0x\n", 285 dlg_regs->refcyc_per_line_delivery_c); 286 dml_print( 287 "DML_RQ_DLG_CALC: chunk_hdl_adjust_cur0 = 0x%0x\n", 288 dlg_regs->chunk_hdl_adjust_cur0); 289 dml_print( 290 "DML_RQ_DLG_CALC: dst_y_offset_cur1 = 0x%0x\n", 291 dlg_regs->dst_y_offset_cur1); 292 dml_print( 293 "DML_RQ_DLG_CALC: chunk_hdl_adjust_cur1 = 0x%0x\n", 294 dlg_regs->chunk_hdl_adjust_cur1); 295 dml_print( 296 "DML_RQ_DLG_CALC: vready_after_vcount0 = 0x%0x\n", 297 dlg_regs->vready_after_vcount0); 298 dml_print( 299 "DML_RQ_DLG_CALC: dst_y_delta_drq_limit = 0x%0x\n", 300 dlg_regs->dst_y_delta_drq_limit); 301 dml_print( 302 "DML_RQ_DLG_CALC: xfc_reg_transfer_delay = 0x%0x\n", 303 dlg_regs->xfc_reg_transfer_delay); 304 dml_print( 305 "DML_RQ_DLG_CALC: xfc_reg_precharge_delay = 0x%0x\n", 306 dlg_regs->xfc_reg_precharge_delay); 307 dml_print( 308 "DML_RQ_DLG_CALC: xfc_reg_remote_surface_flip_latency = 0x%0x\n", 309 dlg_regs->xfc_reg_remote_surface_flip_latency); 310 dml_print( 311 "DML_RQ_DLG_CALC: refcyc_per_vm_dmdata = 0x%0x\n", 312 dlg_regs->refcyc_per_vm_dmdata); 313 314 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 315} 316 317void print__ttu_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_ttu_regs_st *ttu_regs) 318{ 319 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 320 dml_print("DML_RQ_DLG_CALC: DISPLAY_TTU_REGS_ST\n"); 321 dml_print( 322 "DML_RQ_DLG_CALC: qos_level_low_wm = 0x%0x\n", 323 ttu_regs->qos_level_low_wm); 324 dml_print( 325 "DML_RQ_DLG_CALC: qos_level_high_wm = 0x%0x\n", 326 ttu_regs->qos_level_high_wm); 327 dml_print( 328 "DML_RQ_DLG_CALC: min_ttu_vblank = 0x%0x\n", 329 ttu_regs->min_ttu_vblank); 330 dml_print( 331 "DML_RQ_DLG_CALC: qos_level_flip = 0x%0x\n", 332 ttu_regs->qos_level_flip); 333 dml_print( 334 "DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_l = 0x%0x\n", 335 ttu_regs->refcyc_per_req_delivery_pre_l); 336 dml_print( 337 "DML_RQ_DLG_CALC: refcyc_per_req_delivery_l = 0x%0x\n", 338 ttu_regs->refcyc_per_req_delivery_l); 339 dml_print( 340 "DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_c = 0x%0x\n", 341 ttu_regs->refcyc_per_req_delivery_pre_c); 342 dml_print( 343 "DML_RQ_DLG_CALC: refcyc_per_req_delivery_c = 0x%0x\n", 344 ttu_regs->refcyc_per_req_delivery_c); 345 dml_print( 346 "DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur0 = 0x%0x\n", 347 ttu_regs->refcyc_per_req_delivery_cur0); 348 dml_print( 349 "DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur0 = 0x%0x\n", 350 ttu_regs->refcyc_per_req_delivery_pre_cur0); 351 dml_print( 352 "DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur1 = 0x%0x\n", 353 ttu_regs->refcyc_per_req_delivery_cur1); 354 dml_print( 355 "DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur1 = 0x%0x\n", 356 ttu_regs->refcyc_per_req_delivery_pre_cur1); 357 dml_print( 358 "DML_RQ_DLG_CALC: qos_level_fixed_l = 0x%0x\n", 359 ttu_regs->qos_level_fixed_l); 360 dml_print( 361 "DML_RQ_DLG_CALC: qos_ramp_disable_l = 0x%0x\n", 362 ttu_regs->qos_ramp_disable_l); 363 dml_print( 364 "DML_RQ_DLG_CALC: qos_level_fixed_c = 0x%0x\n", 365 ttu_regs->qos_level_fixed_c); 366 dml_print( 367 "DML_RQ_DLG_CALC: qos_ramp_disable_c = 0x%0x\n", 368 ttu_regs->qos_ramp_disable_c); 369 dml_print( 370 "DML_RQ_DLG_CALC: qos_level_fixed_cur0 = 0x%0x\n", 371 ttu_regs->qos_level_fixed_cur0); 372 dml_print( 373 "DML_RQ_DLG_CALC: qos_ramp_disable_cur0 = 0x%0x\n", 374 ttu_regs->qos_ramp_disable_cur0); 375 dml_print( 376 "DML_RQ_DLG_CALC: qos_level_fixed_cur1 = 0x%0x\n", 377 ttu_regs->qos_level_fixed_cur1); 378 dml_print( 379 "DML_RQ_DLG_CALC: qos_ramp_disable_cur1 = 0x%0x\n", 380 ttu_regs->qos_ramp_disable_cur1); 381 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 382}
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