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dcn35_fpu.c

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linux-6.19.14/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c C 
  1// SPDX-License-Identifier: MIT
  2/*
  3 * Copyright 2023 Advanced Micro Devices, Inc.
  4 *
  5 * Permission is hereby granted, free of charge, to any person obtaining a
  6 * copy of this software and associated documentation files (the "Software"),
  7 * to deal in the Software without restriction, including without limitation
  8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9 * and/or sell copies of the Software, and to permit persons to whom the
 10 * Software is furnished to do so, subject to the following conditions:
 11 *
 12 * The above copyright notice and this permission notice shall be included in
 13 * all copies or substantial portions of the Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 21 * OTHER DEALINGS IN THE SOFTWARE.
 22 *
 23 * Authors: AMD
 24 *
 25 */
 26#include "resource.h"
 27#include "dcn35_fpu.h"
 28#include "dcn31/dcn31_resource.h"
 29#include "dcn32/dcn32_resource.h"
 30#include "dcn35/dcn35_resource.h"
 31#include "dml/dcn31/dcn31_fpu.h"
 32#include "dml/dml_inline_defs.h"
 33
 34#include "link_service.h"
 35
 36#define DC_LOGGER_INIT(logger)
 37
 38struct _vcs_dpi_ip_params_st dcn3_5_ip = {
 39	.VBlankNomDefaultUS = 668,
 40	.gpuvm_enable = 1,
 41	.gpuvm_max_page_table_levels = 1,
 42	.hostvm_enable = 1,
 43	.hostvm_max_page_table_levels = 2,
 44	.rob_buffer_size_kbytes = 64,
 45	.det_buffer_size_kbytes = 1536,
 46	.config_return_buffer_size_in_kbytes = 1792,
 47	.compressed_buffer_segment_size_in_kbytes = 64,
 48	.meta_fifo_size_in_kentries = 32,
 49	.zero_size_buffer_entries = 512,
 50	.compbuf_reserved_space_64b = 256,
 51	.compbuf_reserved_space_zs = 64,
 52	.dpp_output_buffer_pixels = 2560,/*not used*/
 53	.opp_output_buffer_lines = 1,/*not used*/
 54	.pixel_chunk_size_kbytes = 8,
 55	//.alpha_pixel_chunk_size_kbytes = 4;/*new*/
 56	//.min_pixel_chunk_size_bytes = 1024;/*new*/
 57	.meta_chunk_size_kbytes = 2,
 58	.min_meta_chunk_size_bytes = 256,
 59	.writeback_chunk_size_kbytes = 8,
 60	.ptoi_supported = false,
 61	.num_dsc = 4,
 62	.maximum_dsc_bits_per_component = 12,/*delta from 10*/
 63	.dsc422_native_support = true,/*delta from false*/
 64	.is_line_buffer_bpp_fixed = true,/*new*/
 65	.line_buffer_fixed_bpp = 32,/*delta from 48*/
 66	.line_buffer_size_bits = 986880,/*delta from 789504*/
 67	.max_line_buffer_lines = 32,/*delta from 12*/
 68	.writeback_interface_buffer_size_kbytes = 90,
 69	.max_num_dpp = 4,
 70	.max_num_otg = 4,
 71	.max_num_hdmi_frl_outputs = 1,
 72	.max_num_wb = 1,
 73	/*.max_num_hdmi_frl_outputs = 1; new in dml2*/
 74	/*.max_num_dp2p0_outputs = 2; new in dml2*/
 75	/*.max_num_dp2p0_streams = 4; new in dml2*/
 76	.max_dchub_pscl_bw_pix_per_clk = 4,
 77	.max_pscl_lb_bw_pix_per_clk = 2,
 78	.max_lb_vscl_bw_pix_per_clk = 4,
 79	.max_vscl_hscl_bw_pix_per_clk = 4,
 80	.max_hscl_ratio = 6,
 81	.max_vscl_ratio = 6,
 82	.max_hscl_taps = 8,
 83	.max_vscl_taps = 8,
 84	.dpte_buffer_size_in_pte_reqs_luma = 68,/*changed from 64,*/
 85	.dpte_buffer_size_in_pte_reqs_chroma = 36,/*changed from 34*/
 86	/*.dcc_meta_buffer_size_bytes = 6272; new to dml2*/
 87	.dispclk_ramp_margin_percent = 1.11,/*delta from 1*/
 88	/*.dppclk_delay_subtotal = 47;
 89	.dppclk_delay_scl = 50;
 90	.dppclk_delay_scl_lb_only = 16;
 91	.dppclk_delay_cnvc_formatter = 28;
 92	.dppclk_delay_cnvc_cursor = 6;
 93	.dispclk_delay_subtotal = 125;*/ /*new to dml2*/
 94	.max_inter_dcn_tile_repeaters = 8,
 95	.cursor_buffer_size = 16,
 96	.cursor_chunk_size = 2,
 97	.writeback_line_buffer_buffer_size = 0,
 98	.writeback_min_hscl_ratio = 1,
 99	.writeback_min_vscl_ratio = 1,
100	.writeback_max_hscl_ratio = 1,
101	.writeback_max_vscl_ratio = 1,
102	.writeback_max_hscl_taps = 1,
103	.writeback_max_vscl_taps = 1,
104	.dppclk_delay_subtotal = 47, /* changed from 46,*/
105	.dppclk_delay_scl = 50,
106	.dppclk_delay_scl_lb_only = 16,
107	.dppclk_delay_cnvc_formatter = 28,/*changed from 27,*/
108	.dppclk_delay_cnvc_cursor = 6,
109	.dispclk_delay_subtotal = 125, /*changed from 119,*/
110	.dynamic_metadata_vm_enabled = false,
111	.odm_combine_4to1_supported = false,
112	.dcc_supported = true,
113//	.config_return_buffer_segment_size_in_kbytes = 64;/*required, hard coded in dml2_translate_ip_params*/
114
115};
116
117struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = {
118		/*TODO: correct dispclk/dppclk voltage level determination*/
119	.clock_limits = {
120		{
121			.state = 0,
122			.dispclk_mhz = 1200.0,
123			.dppclk_mhz = 1200.0,
124			.phyclk_mhz = 600.0,
125			.phyclk_d18_mhz = 667.0,
126			.dscclk_mhz = 186.0,
127			.dtbclk_mhz = 600.0,
128		},
129		{
130			.state = 1,
131			.dispclk_mhz = 1200.0,
132			.dppclk_mhz = 1200.0,
133			.phyclk_mhz = 810.0,
134			.phyclk_d18_mhz = 667.0,
135			.dscclk_mhz = 209.0,
136			.dtbclk_mhz = 600.0,
137		},
138		{
139			.state = 2,
140			.dispclk_mhz = 1200.0,
141			.dppclk_mhz = 1200.0,
142			.phyclk_mhz = 810.0,
143			.phyclk_d18_mhz = 667.0,
144			.dscclk_mhz = 209.0,
145			.dtbclk_mhz = 600.0,
146		},
147		{
148			.state = 3,
149			.dispclk_mhz = 1200.0,
150			.dppclk_mhz = 1200.0,
151			.phyclk_mhz = 810.0,
152			.phyclk_d18_mhz = 667.0,
153			.dscclk_mhz = 371.0,
154			.dtbclk_mhz = 600.0,
155		},
156		{
157			.state = 4,
158			.dispclk_mhz = 1200.0,
159			.dppclk_mhz = 1200.0,
160			.phyclk_mhz = 810.0,
161			.phyclk_d18_mhz = 667.0,
162			.dscclk_mhz = 400.0,
163			.dtbclk_mhz = 600.0,
164		},
165	},
166	.num_states = 5,
167	.sr_exit_time_us = 31.0,
168	.sr_enter_plus_exit_time_us = 33.0,
169	.sr_exit_z8_time_us = 250.0,
170	.sr_enter_plus_exit_z8_time_us = 350.0,
171	.fclk_change_latency_us = 24.0,
172	.usr_retraining_latency_us = 2,
173	.writeback_latency_us = 12.0,
174
175	.dram_channel_width_bytes = 4,/*not exist in dml2*/
176	.round_trip_ping_latency_dcfclk_cycles = 106,/*not exist in dml2*/
177	.urgent_latency_pixel_data_only_us = 4.0,
178	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
179	.urgent_latency_vm_data_only_us = 4.0,
180	.dram_clock_change_latency_us = 34.0,
181	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
182	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
183	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
184
185	.pct_ideal_sdp_bw_after_urgent = 80.0,
186	.pct_ideal_fabric_bw_after_urgent = 80.0, /*new to dml2*/
187	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0,
188	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
189	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,
190	.max_avg_sdp_bw_use_normal_percent = 60.0,
191	.max_avg_dram_bw_use_normal_percent = 60.0,
192	.fabric_datapath_to_dcn_data_return_bytes = 32,
193	.return_bus_width_bytes = 64,
194	.downspread_percent = 0.38,
195	.dcn_downspread_percent = 0.5,
196	.gpuvm_min_page_size_bytes = 4096,
197	.hostvm_min_page_size_bytes = 4096,
198	.do_urgent_latency_adjustment = 0,
199	.urgent_latency_adjustment_fabric_clock_component_us = 0,
200	.urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
201};
202
203void dcn35_build_wm_range_table_fpu(struct clk_mgr *clk_mgr)
204{
205	//TODO
206}
207
208
209/*
210 * dcn35_update_bw_bounding_box
211 *
212 * This would override some dcn3_5 ip_or_soc initial parameters hardcoded from
213 * spreadsheet with actual values as per dGPU SKU:
214 * - with passed few options from dc->config
215 * - with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might
216 *   need to get it from PM FW)
217 * - with passed latency values (passed in ns units) in dc-> bb override for
218 *   debugging purposes
219 * - with passed latencies from VBIOS (in 100_ns units) if available for
220 *   certain dGPU SKU
221 * - with number of DRAM channels from VBIOS (which differ for certain dGPU SKU
222 *   of the same ASIC)
223 * - clocks levels with passed clk_table entries from Clk Mgr as reported by PM
224 *   FW for different clocks (which might differ for certain dGPU SKU of the
225 *   same ASIC)
226 */
227void dcn35_update_bw_bounding_box_fpu(struct dc *dc,
228				      struct clk_bw_params *bw_params)
229{
230	unsigned int i, closest_clk_lvl;
231	int j;
232	struct clk_limit_table *clk_table = &bw_params->clk_table;
233	struct _vcs_dpi_voltage_scaling_st *clock_limits =
234		dc->scratch.update_bw_bounding_box.clock_limits;
235	int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
236
237	dc_assert_fp_enabled();
238
239	dcn3_5_ip.max_num_otg =
240		dc->res_pool->res_cap->num_timing_generator;
241	dcn3_5_ip.max_num_dpp = dc->res_pool->pipe_count;
242	dcn3_5_soc.num_chans = bw_params->num_channels;
243
244	ASSERT(clk_table->num_entries);
245
246	/* Prepass to find max clocks independent of voltage level. */
247	for (i = 0; i < clk_table->num_entries; ++i) {
248		if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
249			max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
250		if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
251			max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
252	}
253
254	for (i = 0; i < clk_table->num_entries; i++) {
255		/* loop backwards*/
256		for (closest_clk_lvl = 0, j = dcn3_5_soc.num_states - 1;
257			j >= 0; j--) {
258			if (dcn3_5_soc.clock_limits[j].dcfclk_mhz <=
259				clk_table->entries[i].dcfclk_mhz) {
260				closest_clk_lvl = j;
261				break;
262			}
263		}
264		if (clk_table->num_entries == 1) {
265			/*smu gives one DPM level, let's take the highest one*/
266			closest_clk_lvl = dcn3_5_soc.num_states - 1;
267		}
268
269		clock_limits[i].state = i;
270
271		/* Clocks dependent on voltage level. */
272		clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
273		if (clk_table->num_entries == 1 &&
274			clock_limits[i].dcfclk_mhz <
275			dcn3_5_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
276			/*SMU fix not released yet*/
277			clock_limits[i].dcfclk_mhz =
278				dcn3_5_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
279		}
280
281		clock_limits[i].fabricclk_mhz =
282			clk_table->entries[i].fclk_mhz;
283		clock_limits[i].socclk_mhz =
284			clk_table->entries[i].socclk_mhz;
285
286		if (clk_table->entries[i].memclk_mhz &&
287			clk_table->entries[i].wck_ratio)
288			clock_limits[i].dram_speed_mts =
289				clk_table->entries[i].memclk_mhz * 2 *
290				clk_table->entries[i].wck_ratio;
291
292		/* Clocks independent of voltage level. */
293		clock_limits[i].dispclk_mhz = max_dispclk_mhz ?
294			max_dispclk_mhz :
295			dcn3_5_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
296
297		clock_limits[i].dppclk_mhz = max_dppclk_mhz ?
298			max_dppclk_mhz :
299			dcn3_5_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
300
301		clock_limits[i].dram_bw_per_chan_gbps =
302			dcn3_5_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
303		clock_limits[i].dscclk_mhz =
304			dcn3_5_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
305		clock_limits[i].dtbclk_mhz =
306			dcn3_5_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
307		clock_limits[i].phyclk_d18_mhz =
308			dcn3_5_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
309		clock_limits[i].phyclk_mhz =
310			dcn3_5_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
311	}
312
313	memcpy(dcn3_5_soc.clock_limits, clock_limits,
314		sizeof(dcn3_5_soc.clock_limits));
315
316	if (clk_table->num_entries)
317		dcn3_5_soc.num_states = clk_table->num_entries;
318
319	if (max_dispclk_mhz) {
320		dcn3_5_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
321		dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
322	}
323	if ((int)(dcn3_5_soc.dram_clock_change_latency_us * 1000)
324				!= dc->debug.dram_clock_change_latency_ns
325			&& dc->debug.dram_clock_change_latency_ns) {
326		dcn3_5_soc.dram_clock_change_latency_us =
327			dc->debug.dram_clock_change_latency_ns / 1000.0;
328	}
329
330	if (dc->bb_overrides.dram_clock_change_latency_ns > 0)
331		dcn3_5_soc.dram_clock_change_latency_us =
332			dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
333
334	if (dc->bb_overrides.sr_exit_time_ns > 0)
335		dcn3_5_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
336
337	if (dc->bb_overrides.sr_enter_plus_exit_time_ns > 0)
338		dcn3_5_soc.sr_enter_plus_exit_time_us =
339			dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
340
341	if (dc->bb_overrides.sr_exit_z8_time_ns > 0)
342		dcn3_5_soc.sr_exit_z8_time_us = dc->bb_overrides.sr_exit_z8_time_ns / 1000.0;
343
344	if (dc->bb_overrides.sr_enter_plus_exit_z8_time_ns > 0)
345		dcn3_5_soc.sr_enter_plus_exit_z8_time_us =
346			dc->bb_overrides.sr_enter_plus_exit_z8_time_ns / 1000.0;
347
348	/*temp till dml2 fully work without dml1*/
349	dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip,
350				DML_PROJECT_DCN31);
351
352	/*copy to dml2, before dml2_create*/
353	if (clk_table->num_entries > 2) {
354
355		for (i = 0; i < clk_table->num_entries; i++) {
356			dc->dml2_options.bbox_overrides.clks_table.num_states =
357				clk_table->num_entries;
358			dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz =
359				clock_limits[i].dcfclk_mhz;
360			dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz =
361				clock_limits[i].fabricclk_mhz;
362			dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz =
363				clock_limits[i].dispclk_mhz;
364			dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz =
365				clock_limits[i].dppclk_mhz;
366			dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz =
367				clock_limits[i].socclk_mhz;
368			dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =
369				clk_table->entries[i].memclk_mhz * clk_table->entries[i].wck_ratio;
370
371			dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dram_speed_mts = clock_limits[i].dram_speed_mts;
372			dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =
373				clock_limits[i].dtbclk_mhz;
374			dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =
375				clk_table->num_entries;
376			dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =
377				clk_table->num_entries;
378			dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels =
379				clk_table->num_entries;
380			dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels =
381				clk_table->num_entries;
382			dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels =
383				clk_table->num_entries;
384			dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =
385				clk_table->num_entries;
386			dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels =
387				clk_table->num_entries;
388		}
389	}
390
391	/* Update latency values */
392	dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = dcn3_5_soc.dram_clock_change_latency_us;
393
394	dc->dml2_options.bbox_overrides.sr_exit_latency_us = dcn3_5_soc.sr_exit_time_us;
395	dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us = dcn3_5_soc.sr_enter_plus_exit_time_us;
396
397	dc->dml2_options.bbox_overrides.sr_exit_z8_time_us = dcn3_5_soc.sr_exit_z8_time_us;
398	dc->dml2_options.bbox_overrides.sr_enter_plus_exit_z8_time_us = dcn3_5_soc.sr_enter_plus_exit_z8_time_us;
399}
400
401static bool is_dual_plane(enum surface_pixel_format format)
402{
403	return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN ||
404		format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
405}
406
407/*
408 * micro_sec_to_vert_lines () - converts time to number of vertical lines for a given timing
409 *
410 * @param: num_us: number of microseconds
411 * @return: number of vertical lines. If exact number of vertical lines is not found then
412 *          it will round up to next number of lines to guarantee num_us
413 */
414static unsigned int micro_sec_to_vert_lines(unsigned int num_us, struct dc_crtc_timing *timing)
415{
416	unsigned int num_lines = 0;
417	unsigned int lines_time_in_ns = 1000.0 *
418			(((float)timing->h_total * 1000.0) /
419			 ((float)timing->pix_clk_100hz / 10.0));
420
421	num_lines = dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0);
422
423	return num_lines;
424}
425
426static unsigned int get_vertical_back_porch(struct dc_crtc_timing *timing)
427{
428	unsigned int v_active = 0, v_blank = 0, v_back_porch = 0;
429
430	v_active = timing->v_border_top + timing->v_addressable + timing->v_border_bottom;
431	v_blank = timing->v_total - v_active;
432	v_back_porch = v_blank - timing->v_front_porch - timing->v_sync_width;
433
434	return v_back_porch;
435}
436
437int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc,
438					      struct dc_state *context,
439					      display_e2e_pipe_params_st *pipes,
440					      enum dc_validate_mode validate_mode)
441{
442	int i, pipe_cnt;
443	struct resource_context *res_ctx = &context->res_ctx;
444	struct pipe_ctx *pipe = 0;
445	bool upscaled = false;
446	const unsigned int max_allowed_vblank_nom = 1023;
447
448	dc_assert_fp_enabled();
449
450	dcn31_populate_dml_pipes_from_context(dc, context, pipes,
451					      validate_mode);
452
453	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
454		struct dc_crtc_timing *timing;
455		unsigned int num_lines = 0;
456		unsigned int v_back_porch = 0;
457
458		if (!res_ctx->pipe_ctx[i].stream)
459			continue;
460
461		pipe = &res_ctx->pipe_ctx[i];
462		timing = &pipe->stream->timing;
463
464		num_lines = micro_sec_to_vert_lines(dcn3_5_ip.VBlankNomDefaultUS, timing);
465		v_back_porch  = get_vertical_back_porch(timing);
466
467		if (pipe->stream->adjust.v_total_max ==
468		    pipe->stream->adjust.v_total_min &&
469		    pipe->stream->adjust.v_total_min > timing->v_total) {
470			pipes[pipe_cnt].pipe.dest.vtotal =
471				pipe->stream->adjust.v_total_min;
472			pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total -
473				pipes[pipe_cnt].pipe.dest.vactive;
474		}
475
476		pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive;
477		pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines);
478		// vblank_nom should not smaller than (VSync (timing->v_sync_width + v_back_porch) + 2)
479		// + 2 is because
480		// 1 -> VStartup_start should be 1 line before VSync
481		// 1 -> always reserve 1 line between start of vblank to vstartup signal
482		pipes[pipe_cnt].pipe.dest.vblank_nom =
483			max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width + v_back_porch + 2);
484		pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblank_nom);
485
486		if (pipe->plane_state &&
487		    (pipe->plane_state->src_rect.height <
488		     pipe->plane_state->dst_rect.height ||
489		     pipe->plane_state->src_rect.width <
490		     pipe->plane_state->dst_rect.width))
491			upscaled = true;
492
493		/*
494		 * Immediate flip can be set dynamically after enabling the
495		 * plane. We need to require support for immediate flip or
496		 * underflow can be intermittently experienced depending on peak
497		 * b/w requirements.
498		 */
499		pipes[pipe_cnt].pipe.src.immediate_flip = true;
500
501		pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
502
503		dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);
504
505		pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
506		pipes[pipe_cnt].pipe.src.dcc_rate = 3;
507		pipes[pipe_cnt].dout.dsc_input_bpc = 0;
508		pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256;
509
510		if (pipes[pipe_cnt].dout.dsc_enable) {
511			switch (timing->display_color_depth) {
512			case COLOR_DEPTH_888:
513				pipes[pipe_cnt].dout.dsc_input_bpc = 8;
514				break;
515			case COLOR_DEPTH_101010:
516				pipes[pipe_cnt].dout.dsc_input_bpc = 10;
517				break;
518			case COLOR_DEPTH_121212:
519				pipes[pipe_cnt].dout.dsc_input_bpc = 12;
520				break;
521			default:
522				ASSERT(0);
523				break;
524			}
525		}
526
527		pipe_cnt++;
528	}
529
530	context->bw_ctx.dml.ip.det_buffer_size_kbytes = 384;/*per guide*/
531	dc->config.enable_4to1MPC = false;
532
533	if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
534		if (is_dual_plane(pipe->plane_state->format)
535				&& pipe->plane_state->src_rect.width <= 1920 &&
536				pipe->plane_state->src_rect.height <= 1080) {
537			dc->config.enable_4to1MPC = true;
538		} else if (!is_dual_plane(pipe->plane_state->format) &&
539			   pipe->plane_state->src_rect.width <= 5120) {
540			/*
541			 * Limit to 5k max to avoid forced pipe split when there
542			 * is not enough detile for swath
543			 */
544			context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
545			pipes[0].pipe.src.unbounded_req_mode = true;
546		}
547	} else if (context->stream_count >=
548		   dc->debug.crb_alloc_policy_min_disp_count &&
549		   dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) {
550		context->bw_ctx.dml.ip.det_buffer_size_kbytes =
551			dc->debug.crb_alloc_policy * 64;
552	} else if (context->stream_count >= 3 && upscaled) {
553		context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
554	}
555
556	for (i = 0; i < dc->res_pool->pipe_count; i++) {
557		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
558
559		if (!pipe->stream)
560			continue;
561
562		if (pipe->stream->signal == SIGNAL_TYPE_EDP &&
563		    dc->debug.seamless_boot_odm_combine &&
564		    pipe->stream->apply_seamless_boot_optimization) {
565
566			if (pipe->stream->apply_boot_odm_mode ==
567			    dm_odm_combine_policy_2to1) {
568				context->bw_ctx.dml.vba.ODMCombinePolicy =
569					dm_odm_combine_policy_2to1;
570				break;
571			}
572		}
573	}
574
575	return pipe_cnt;
576}
577
578void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context)
579{
580	enum dcn_zstate_support_state support = DCN_ZSTATE_SUPPORT_DISALLOW;
581	unsigned int i, plane_count = 0;
582	DC_LOGGER_INIT(dc->ctx->logger);
583
584	dc_assert_fp_enabled();
585
586	for (i = 0; i < dc->res_pool->pipe_count; i++) {
587		if (context->res_ctx.pipe_ctx[i].plane_state)
588			plane_count++;
589	}
590
591	if (context->stream_count == 0 || plane_count == 0) {
592		support = DCN_ZSTATE_SUPPORT_ALLOW;
593	} else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) {
594		struct dc_link *link = context->streams[0]->sink->link;
595		bool is_pwrseq0 = link && link->link_index == 0;
596		bool is_psr = (link && (link->psr_settings.psr_version == DC_PSR_VERSION_1 ||
597								link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) && !link->panel_config.psr.disable_psr);
598		bool is_replay = link && link->replay_settings.replay_feature_enabled;
599		int minmum_z8_residency =
600			dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000;
601		bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency;
602		int minmum_z10_residency =
603			dc->debug.minimum_z10_residency_time > 0 ? dc->debug.minimum_z10_residency_time : 5000;
604		bool allow_z10 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z10_residency;
605
606		/*for psr1/psr-su, we allow z8 and z10 based on latency, for replay with IPS enabled, it will enter ips2*/
607		if (is_pwrseq0 && allow_z10)
608			support = DCN_ZSTATE_SUPPORT_ALLOW;
609		else if (is_pwrseq0 && (is_psr || is_replay))
610			support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY;
611		else if (allow_z8)
612			support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY;
613
614	}
615
616	DC_LOG_SMU("zstate_support: %d, StutterPeriod: %d\n", support,
617		   (int)context->bw_ctx.dml.vba.StutterPeriod);
618
619	context->bw_ctx.bw.dcn.clk.zstate_support = support;
620}
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