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display_rq_dlg_calc_32.c
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linux-6.19.14/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
1/* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27#include "../display_mode_lib.h" 28#include "../display_mode_vba.h" 29#include "../dml_inline_defs.h" 30#include "display_rq_dlg_calc_32.h" 31 32static bool is_dual_plane(enum source_format_class source_format) 33{ 34 bool ret_val = 0; 35 36 if ((source_format == dm_420_12) || (source_format == dm_420_8) || (source_format == dm_420_10) 37 || (source_format == dm_rgbe_alpha)) 38 ret_val = 1; 39 40 return ret_val; 41} 42 43void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs, 44 struct display_mode_lib *mode_lib, 45 const display_e2e_pipe_params_st *e2e_pipe_param, 46 const unsigned int num_pipes, 47 const unsigned int pipe_idx) 48{ 49 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; 50 bool dual_plane = is_dual_plane((enum source_format_class) (src->source_format)); 51 double stored_swath_l_bytes; 52 double stored_swath_c_bytes; 53 bool is_phantom_pipe; 54 uint32_t pixel_chunk_bytes = 0; 55 uint32_t min_pixel_chunk_bytes = 0; 56 uint32_t meta_chunk_bytes = 0; 57 uint32_t min_meta_chunk_bytes = 0; 58 uint32_t dpte_group_bytes = 0; 59 uint32_t mpte_group_bytes = 0; 60 61 uint32_t p1_pixel_chunk_bytes = 0; 62 uint32_t p1_min_pixel_chunk_bytes = 0; 63 uint32_t p1_meta_chunk_bytes = 0; 64 uint32_t p1_min_meta_chunk_bytes = 0; 65 uint32_t p1_dpte_group_bytes = 0; 66 uint32_t p1_mpte_group_bytes = 0; 67 68 unsigned int detile_buf_size_in_bytes; 69 unsigned int detile_buf_plane1_addr; 70 unsigned int pte_row_height_linear; 71 72 memset(rq_regs, 0, sizeof(*rq_regs)); 73 74 dml_print("DML_DLG::%s: Calculation for pipe[%d] start, num_pipes=%d\n", __func__, pipe_idx, num_pipes); 75 76 pixel_chunk_bytes = get_pixel_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024; // From VBA 77 min_pixel_chunk_bytes = get_min_pixel_chunk_size_in_byte(mode_lib, e2e_pipe_param, num_pipes); // From VBA 78 79 if (pixel_chunk_bytes == 64 * 1024) 80 min_pixel_chunk_bytes = 0; 81 82 meta_chunk_bytes = get_meta_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024; // From VBA 83 min_meta_chunk_bytes = get_min_meta_chunk_size_in_byte(mode_lib, e2e_pipe_param, num_pipes); // From VBA 84 85 dpte_group_bytes = get_dpte_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 86 mpte_group_bytes = get_vm_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 87 88 p1_pixel_chunk_bytes = pixel_chunk_bytes; 89 p1_min_pixel_chunk_bytes = min_pixel_chunk_bytes; 90 p1_meta_chunk_bytes = meta_chunk_bytes; 91 p1_min_meta_chunk_bytes = min_meta_chunk_bytes; 92 p1_dpte_group_bytes = dpte_group_bytes; 93 p1_mpte_group_bytes = mpte_group_bytes; 94 95 if ((enum source_format_class) src->source_format == dm_rgbe_alpha) 96 p1_pixel_chunk_bytes = get_alpha_pixel_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024; 97 98 rq_regs->rq_regs_l.chunk_size = dml_log2(pixel_chunk_bytes) - 10; 99 rq_regs->rq_regs_c.chunk_size = dml_log2(p1_pixel_chunk_bytes) - 10; 100 101 if (min_pixel_chunk_bytes == 0) 102 rq_regs->rq_regs_l.min_chunk_size = 0; 103 else 104 rq_regs->rq_regs_l.min_chunk_size = dml_log2(min_pixel_chunk_bytes) - 8 + 1; 105 106 if (p1_min_pixel_chunk_bytes == 0) 107 rq_regs->rq_regs_c.min_chunk_size = 0; 108 else 109 rq_regs->rq_regs_c.min_chunk_size = dml_log2(p1_min_pixel_chunk_bytes) - 8 + 1; 110 111 rq_regs->rq_regs_l.meta_chunk_size = dml_log2(meta_chunk_bytes) - 10; 112 rq_regs->rq_regs_c.meta_chunk_size = dml_log2(p1_meta_chunk_bytes) - 10; 113 114 if (min_meta_chunk_bytes == 0) 115 rq_regs->rq_regs_l.min_meta_chunk_size = 0; 116 else 117 rq_regs->rq_regs_l.min_meta_chunk_size = dml_log2(min_meta_chunk_bytes) - 6 + 1; 118 119 if (p1_min_meta_chunk_bytes == 0) 120 rq_regs->rq_regs_c.min_meta_chunk_size = 0; 121 else 122 rq_regs->rq_regs_c.min_meta_chunk_size = dml_log2(p1_min_meta_chunk_bytes) - 6 + 1; 123 124 rq_regs->rq_regs_l.dpte_group_size = dml_log2(dpte_group_bytes) - 6; 125 rq_regs->rq_regs_l.mpte_group_size = dml_log2(mpte_group_bytes) - 6; 126 rq_regs->rq_regs_c.dpte_group_size = dml_log2(p1_dpte_group_bytes) - 6; 127 rq_regs->rq_regs_c.mpte_group_size = dml_log2(p1_mpte_group_bytes) - 6; 128 129 detile_buf_size_in_bytes = get_det_buffer_size_kbytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * 1024; 130 detile_buf_plane1_addr = 0; 131 pte_row_height_linear = get_dpte_row_height_linear_l(mode_lib, e2e_pipe_param, num_pipes, 132 pipe_idx); 133 134 if (src->sw_mode == dm_sw_linear) 135 ASSERT(pte_row_height_linear >= 8); 136 137 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(pte_row_height_linear), 1) - 3; 138 139 if (dual_plane) { 140 unsigned int p1_pte_row_height_linear = get_dpte_row_height_linear_c(mode_lib, e2e_pipe_param, 141 num_pipes, pipe_idx); 142 if (src->sw_mode == dm_sw_linear) 143 ASSERT(p1_pte_row_height_linear >= 8); 144 145 rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(p1_pte_row_height_linear), 1) - 3; 146 } 147 148 rq_regs->rq_regs_l.swath_height = dml_log2(get_swath_height_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx)); 149 rq_regs->rq_regs_c.swath_height = dml_log2(get_swath_height_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx)); 150 151 // FIXME: take the max between luma, chroma chunk size? 152 // okay for now, as we are setting pixel_chunk_bytes to 8kb anyways 153 if (pixel_chunk_bytes >= 32 * 1024 || (dual_plane && p1_pixel_chunk_bytes >= 32 * 1024)) { //32kb 154 rq_regs->drq_expansion_mode = 0; 155 } else { 156 rq_regs->drq_expansion_mode = 2; 157 } 158 rq_regs->prq_expansion_mode = 1; 159 rq_regs->mrq_expansion_mode = 1; 160 rq_regs->crq_expansion_mode = 1; 161 162 stored_swath_l_bytes = get_det_stored_buffer_size_l_bytes(mode_lib, e2e_pipe_param, num_pipes, 163 pipe_idx); 164 stored_swath_c_bytes = get_det_stored_buffer_size_c_bytes(mode_lib, e2e_pipe_param, num_pipes, 165 pipe_idx); 166 is_phantom_pipe = get_is_phantom_pipe(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 167 168 // Note: detile_buf_plane1_addr is in unit of 1KB 169 if (dual_plane) { 170 if (is_phantom_pipe) { 171 detile_buf_plane1_addr = ((1024.0 * 1024.0) / 2.0 / 1024.0); // half to chroma 172 } else { 173 if (stored_swath_l_bytes / stored_swath_c_bytes <= 1.5) { 174 detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma 175#ifdef __DML_RQ_DLG_CALC_DEBUG__ 176 dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d (1/2 to chroma)\n", 177 __func__, detile_buf_plane1_addr); 178#endif 179 } else { 180 detile_buf_plane1_addr = 181 dml_round_to_multiple( 182 (unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 183 1024, 0) / 1024.0; // 2/3 to luma 184#ifdef __DML_RQ_DLG_CALC_DEBUG__ 185 dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d (1/3 chroma)\n", 186 __func__, detile_buf_plane1_addr); 187#endif 188 } 189 } 190 } 191 rq_regs->plane1_base_address = detile_buf_plane1_addr; 192 193#ifdef __DML_RQ_DLG_CALC_DEBUG__ 194 dml_print("DML_DLG: %s: is_phantom_pipe = %d\n", __func__, is_phantom_pipe); 195 dml_print("DML_DLG: %s: stored_swath_l_bytes = %f\n", __func__, stored_swath_l_bytes); 196 dml_print("DML_DLG: %s: stored_swath_c_bytes = %f\n", __func__, stored_swath_c_bytes); 197 dml_print("DML_DLG: %s: detile_buf_size_in_bytes = %d\n", __func__, detile_buf_size_in_bytes); 198 dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d\n", __func__, detile_buf_plane1_addr); 199 dml_print("DML_DLG: %s: plane1_base_address = %d\n", __func__, rq_regs->plane1_base_address); 200#endif 201 print__rq_regs_st(mode_lib, rq_regs); 202 dml_print("DML_DLG::%s: Calculation for pipe[%d] done, num_pipes=%d\n", __func__, pipe_idx, num_pipes); 203} 204 205void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, 206 display_dlg_regs_st *dlg_regs, 207 display_ttu_regs_st *ttu_regs, 208 display_e2e_pipe_params_st *e2e_pipe_param, 209 const unsigned int num_pipes, 210 const unsigned int pipe_idx) 211{ 212 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; 213 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; 214 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; 215 double refcyc_per_req_delivery_pre_cur0 = 0.; 216 double refcyc_per_req_delivery_cur0 = 0.; 217 double refcyc_per_req_delivery_pre_c = 0.; 218 double refcyc_per_req_delivery_c = 0.; 219 double refcyc_per_req_delivery_pre_l; 220 double refcyc_per_req_delivery_l; 221 double refcyc_per_line_delivery_pre_c = 0.; 222 double refcyc_per_line_delivery_c = 0.; 223 double refcyc_per_line_delivery_pre_l; 224 double refcyc_per_line_delivery_l; 225 double min_ttu_vblank; 226 double vratio_pre_l; 227 double vratio_pre_c; 228 unsigned int min_dst_y_next_start; 229 unsigned int htotal = dst->htotal; 230 unsigned int hblank_end = dst->hblank_end; 231 unsigned int vblank_end = dst->vblank_end; 232 bool interlaced = dst->interlaced; 233 double pclk_freq_in_mhz = dst->pixel_rate_mhz; 234 unsigned int vready_after_vcount0; 235 double refclk_freq_in_mhz = clks->refclk_mhz; 236 double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; 237 bool dual_plane = 0; 238 unsigned int pipe_index_in_combine[DC__NUM_PIPES__MAX]; 239 unsigned int dst_x_after_scaler; 240 unsigned int dst_y_after_scaler; 241 double dst_y_prefetch; 242 double dst_y_per_vm_vblank; 243 double dst_y_per_row_vblank; 244 double dst_y_per_vm_flip; 245 double dst_y_per_row_flip; 246 double max_dst_y_per_vm_vblank = 32.0; 247 double max_dst_y_per_row_vblank = 16.0; 248 double dst_y_per_pte_row_nom_l; 249 double dst_y_per_pte_row_nom_c; 250 double dst_y_per_meta_row_nom_l; 251 double dst_y_per_meta_row_nom_c; 252 double refcyc_per_pte_group_nom_l; 253 double refcyc_per_pte_group_nom_c; 254 double refcyc_per_pte_group_vblank_l; 255 double refcyc_per_pte_group_vblank_c; 256 double refcyc_per_pte_group_flip_l; 257 double refcyc_per_pte_group_flip_c; 258 double refcyc_per_meta_chunk_nom_l; 259 double refcyc_per_meta_chunk_nom_c; 260 double refcyc_per_meta_chunk_vblank_l; 261 double refcyc_per_meta_chunk_vblank_c; 262 double refcyc_per_meta_chunk_flip_l; 263 double refcyc_per_meta_chunk_flip_c; 264 265 memset(dlg_regs, 0, sizeof(*dlg_regs)); 266 memset(ttu_regs, 0, sizeof(*ttu_regs)); 267 dml_print("DML_DLG::%s: Calculation for pipe[%d] starts, num_pipes=%d\n", __func__, pipe_idx, num_pipes); 268 dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz); 269 dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz); 270 dml_print("DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n", __func__, ref_freq_to_pix_freq); 271 dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced); 272 ASSERT(ref_freq_to_pix_freq < 4.0); 273 274 dlg_regs->ref_freq_to_pix_freq = (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); 275 dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8)); 276 dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits 277 278 min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 279 min_dst_y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 280 281 dml_print("DML_DLG: %s: min_ttu_vblank (us) = %3.2f\n", __func__, min_ttu_vblank); 282 dml_print("DML_DLG: %s: min_dst_y_next_start = %d\n", __func__, min_dst_y_next_start); 283 dml_print("DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n", __func__, ref_freq_to_pix_freq); 284 285 dual_plane = is_dual_plane((enum source_format_class) (src->source_format)); 286 287 vready_after_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes, 288 pipe_idx); // From VBA 289 dlg_regs->vready_after_vcount0 = vready_after_vcount0; 290 291 dml_print("DML_DLG: %s: vready_after_vcount0 = %d\n", __func__, dlg_regs->vready_after_vcount0); 292 293 dst_x_after_scaler = dml_ceil(get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx), 1); 294 dst_y_after_scaler = dml_ceil(get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx), 1); 295 296 // do some adjustment on the dst_after scaler to account for odm combine mode 297 dml_print("DML_DLG: %s: input dst_x_after_scaler = %d\n", __func__, dst_x_after_scaler); 298 dml_print("DML_DLG: %s: input dst_y_after_scaler = %d\n", __func__, dst_y_after_scaler); 299 300 // need to figure out which side of odm combine we're in 301 if (dst->odm_combine == dm_odm_combine_mode_2to1 || dst->odm_combine == dm_odm_combine_mode_4to1) { 302 // figure out which pipes go together 303 bool visited[DC__NUM_PIPES__MAX]; 304 unsigned int i, j, k; 305 306 for (k = 0; k < num_pipes; ++k) { 307 visited[k] = false; 308 pipe_index_in_combine[k] = 0; 309 } 310 311 for (i = 0; i < num_pipes; i++) { 312 if (e2e_pipe_param[i].pipe.src.is_hsplit && !visited[i]) { 313 314 unsigned int grp = e2e_pipe_param[i].pipe.src.hsplit_grp; 315 unsigned int grp_idx = 0; 316 317 for (j = i; j < num_pipes; j++) { 318 if (e2e_pipe_param[j].pipe.src.hsplit_grp == grp 319 && e2e_pipe_param[j].pipe.src.is_hsplit && !visited[j]) { 320 pipe_index_in_combine[j] = grp_idx; 321 dml_print("DML_DLG: %s: pipe[%d] is in grp %d idx %d\n", 322 __func__, j, grp, grp_idx); 323 grp_idx++; 324 visited[j] = true; 325 } 326 } 327 } 328 } 329 } 330 331 if (dst->odm_combine == dm_odm_combine_mode_disabled) { 332 // FIXME how about ODM split?? 333 dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end * ref_freq_to_pix_freq); 334 } else { 335 if (dst->odm_combine == dm_odm_combine_mode_2to1 || dst->odm_combine == dm_odm_combine_mode_4to1) { 336 // TODO: We should really check that 4to1 is supported before setting it to 4 337 unsigned int odm_combine_factor = (dst->odm_combine == dm_odm_combine_mode_2to1 ? 2 : 4); 338 unsigned int odm_pipe_index = pipe_index_in_combine[pipe_idx]; 339 340 dlg_regs->refcyc_h_blank_end = (unsigned int) (((double) hblank_end 341 + odm_pipe_index * (double) dst->hactive / odm_combine_factor) * ref_freq_to_pix_freq); 342 } 343 } 344 ASSERT(dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13)); 345 346 dml_print("DML_DLG: %s: htotal= %d\n", __func__, htotal); 347 dml_print("DML_DLG: %s: dst_x_after_scaler[%d]= %d\n", __func__, pipe_idx, dst_x_after_scaler); 348 dml_print("DML_DLG: %s: dst_y_after_scaler[%d] = %d\n", __func__, pipe_idx, dst_y_after_scaler); 349 350 dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 351 // From VBA 352 dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 353 // From VBA 354 dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 355 dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 356 dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 357 358 // magic! 359 if (htotal <= 75) { 360 max_dst_y_per_vm_vblank = 100.0; 361 max_dst_y_per_row_vblank = 100.0; 362 } 363 364 dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch); 365 dml_print("DML_DLG: %s: dst_y_per_vm_flip = %3.2f\n", __func__, dst_y_per_vm_flip); 366 dml_print("DML_DLG: %s: dst_y_per_row_flip = %3.2f\n", __func__, dst_y_per_row_flip); 367 dml_print("DML_DLG: %s: dst_y_per_vm_vblank = %3.2f\n", __func__, dst_y_per_vm_vblank); 368 dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank); 369 370 ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank); 371 ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank); 372 ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank)); 373 374 vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 375 vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 376 377 dml_print("DML_DLG: %s: vratio_pre_l = %3.2f\n", __func__, vratio_pre_l); 378 dml_print("DML_DLG: %s: vratio_pre_c = %3.2f\n", __func__, vratio_pre_c); 379 380 // Active 381 refcyc_per_line_delivery_pre_l = get_refcyc_per_line_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 382 refcyc_per_line_delivery_l = get_refcyc_per_line_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, 383 pipe_idx) * refclk_freq_in_mhz; // From VBA 384 385 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n", __func__, refcyc_per_line_delivery_pre_l); 386 dml_print("DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f\n", __func__, refcyc_per_line_delivery_l); 387 388 if (dual_plane) { 389 refcyc_per_line_delivery_pre_c = get_refcyc_per_line_delivery_pre_c_in_us(mode_lib, e2e_pipe_param, 390 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 391 refcyc_per_line_delivery_c = get_refcyc_per_line_delivery_c_in_us(mode_lib, e2e_pipe_param, num_pipes, 392 pipe_idx) * refclk_freq_in_mhz; // From VBA 393 394 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n", 395 __func__, refcyc_per_line_delivery_pre_c); 396 dml_print("DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f\n", 397 __func__, refcyc_per_line_delivery_c); 398 } 399 400 if (src->dynamic_metadata_enable && src->gpuvm) 401 dlg_regs->refcyc_per_vm_dmdata = get_refcyc_per_vm_dmdata_in_us(mode_lib, e2e_pipe_param, num_pipes, 402 pipe_idx) * refclk_freq_in_mhz; // From VBA 403 404 dlg_regs->dmdata_dl_delta = get_dmdata_dl_delta_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) 405 * refclk_freq_in_mhz; // From VBA 406 407 refcyc_per_req_delivery_pre_l = get_refcyc_per_req_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 408 refcyc_per_req_delivery_l = get_refcyc_per_req_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, 409 pipe_idx) * refclk_freq_in_mhz; // From VBA 410 411 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n", __func__, refcyc_per_req_delivery_pre_l); 412 dml_print("DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f\n", __func__, refcyc_per_req_delivery_l); 413 414 if (dual_plane) { 415 refcyc_per_req_delivery_pre_c = get_refcyc_per_req_delivery_pre_c_in_us(mode_lib, e2e_pipe_param, 416 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 417 refcyc_per_req_delivery_c = get_refcyc_per_req_delivery_c_in_us(mode_lib, e2e_pipe_param, num_pipes, 418 pipe_idx) * refclk_freq_in_mhz; // From VBA 419 420 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n", 421 __func__, refcyc_per_req_delivery_pre_c); 422 dml_print("DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f\n", __func__, refcyc_per_req_delivery_c); 423 } 424 425 // TTU - Cursor 426 ASSERT(src->num_cursors <= 1); 427 if (src->num_cursors > 0) { 428 refcyc_per_req_delivery_pre_cur0 = get_refcyc_per_cursor_req_delivery_pre_in_us(mode_lib, 429 e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 430 refcyc_per_req_delivery_cur0 = get_refcyc_per_cursor_req_delivery_in_us(mode_lib, e2e_pipe_param, 431 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 432 433 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur0 = %3.2f\n", 434 __func__, refcyc_per_req_delivery_pre_cur0); 435 dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur0 = %3.2f\n", 436 __func__, refcyc_per_req_delivery_cur0); 437 } 438 439 // Assign to register structures 440 dlg_regs->min_dst_y_next_start = min_dst_y_next_start * dml_pow(2, 2); 441 ASSERT(dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18)); 442 443 dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line 444 dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk 445 dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); 446 dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); 447 dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); 448 dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); 449 dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2)); 450 451 dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); 452 dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); 453 454 dml_print("DML_DLG: %s: dlg_regs->dst_y_per_vm_vblank = 0x%x\n", __func__, dlg_regs->dst_y_per_vm_vblank); 455 dml_print("DML_DLG: %s: dlg_regs->dst_y_per_row_vblank = 0x%x\n", __func__, dlg_regs->dst_y_per_row_vblank); 456 dml_print("DML_DLG: %s: dlg_regs->dst_y_per_vm_flip = 0x%x\n", __func__, dlg_regs->dst_y_per_vm_flip); 457 dml_print("DML_DLG: %s: dlg_regs->dst_y_per_row_flip = 0x%x\n", __func__, dlg_regs->dst_y_per_row_flip); 458 459 dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank_in_us(mode_lib, e2e_pipe_param, 460 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 461 dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, 462 pipe_idx) * refclk_freq_in_mhz; // From VBA 463 dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, 464 pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA 465 dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, 466 pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA 467 468 // From VBA 469 dst_y_per_pte_row_nom_l = get_dst_y_per_pte_row_nom_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 470 // From VBA 471 dst_y_per_pte_row_nom_c = get_dst_y_per_pte_row_nom_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 472 // From VBA 473 dst_y_per_meta_row_nom_l = get_dst_y_per_meta_row_nom_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 474 // From VBA 475 dst_y_per_meta_row_nom_c = get_dst_y_per_meta_row_nom_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 476 477 refcyc_per_pte_group_nom_l = get_refcyc_per_pte_group_nom_l_in_us(mode_lib, e2e_pipe_param, num_pipes, 478 pipe_idx) * refclk_freq_in_mhz; // From VBA 479 refcyc_per_pte_group_nom_c = get_refcyc_per_pte_group_nom_c_in_us(mode_lib, e2e_pipe_param, num_pipes, 480 pipe_idx) * refclk_freq_in_mhz; // From VBA 481 refcyc_per_pte_group_vblank_l = get_refcyc_per_pte_group_vblank_l_in_us(mode_lib, e2e_pipe_param, 482 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 483 refcyc_per_pte_group_vblank_c = get_refcyc_per_pte_group_vblank_c_in_us(mode_lib, e2e_pipe_param, 484 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 485 refcyc_per_pte_group_flip_l = get_refcyc_per_pte_group_flip_l_in_us(mode_lib, e2e_pipe_param, num_pipes, 486 pipe_idx) * refclk_freq_in_mhz; // From VBA 487 refcyc_per_pte_group_flip_c = get_refcyc_per_pte_group_flip_c_in_us(mode_lib, e2e_pipe_param, num_pipes, 488 pipe_idx) * refclk_freq_in_mhz; // From VBA 489 490 refcyc_per_meta_chunk_nom_l = get_refcyc_per_meta_chunk_nom_l_in_us(mode_lib, e2e_pipe_param, num_pipes, 491 pipe_idx) * refclk_freq_in_mhz; // From VBA 492 refcyc_per_meta_chunk_nom_c = get_refcyc_per_meta_chunk_nom_c_in_us(mode_lib, e2e_pipe_param, num_pipes, 493 pipe_idx) * refclk_freq_in_mhz; // From VBA 494 refcyc_per_meta_chunk_vblank_l = get_refcyc_per_meta_chunk_vblank_l_in_us(mode_lib, e2e_pipe_param, 495 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 496 refcyc_per_meta_chunk_vblank_c = get_refcyc_per_meta_chunk_vblank_c_in_us(mode_lib, e2e_pipe_param, 497 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 498 refcyc_per_meta_chunk_flip_l = get_refcyc_per_meta_chunk_flip_l_in_us(mode_lib, e2e_pipe_param, 499 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 500 refcyc_per_meta_chunk_flip_c = get_refcyc_per_meta_chunk_flip_c_in_us(mode_lib, e2e_pipe_param, 501 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 502 503 dlg_regs->dst_y_per_pte_row_nom_l = dst_y_per_pte_row_nom_l * dml_pow(2, 2); 504 dlg_regs->dst_y_per_pte_row_nom_c = dst_y_per_pte_row_nom_c * dml_pow(2, 2); 505 dlg_regs->dst_y_per_meta_row_nom_l = dst_y_per_meta_row_nom_l * dml_pow(2, 2); 506 dlg_regs->dst_y_per_meta_row_nom_c = dst_y_per_meta_row_nom_c * dml_pow(2, 2); 507 dlg_regs->refcyc_per_pte_group_nom_l = refcyc_per_pte_group_nom_l; 508 dlg_regs->refcyc_per_pte_group_nom_c = refcyc_per_pte_group_nom_c; 509 dlg_regs->refcyc_per_pte_group_vblank_l = refcyc_per_pte_group_vblank_l; 510 dlg_regs->refcyc_per_pte_group_vblank_c = refcyc_per_pte_group_vblank_c; 511 dlg_regs->refcyc_per_pte_group_flip_l = refcyc_per_pte_group_flip_l; 512 dlg_regs->refcyc_per_pte_group_flip_c = refcyc_per_pte_group_flip_c; 513 dlg_regs->refcyc_per_meta_chunk_nom_l = refcyc_per_meta_chunk_nom_l; 514 dlg_regs->refcyc_per_meta_chunk_nom_c = refcyc_per_meta_chunk_nom_c; 515 dlg_regs->refcyc_per_meta_chunk_vblank_l = refcyc_per_meta_chunk_vblank_l; 516 dlg_regs->refcyc_per_meta_chunk_vblank_c = refcyc_per_meta_chunk_vblank_c; 517 dlg_regs->refcyc_per_meta_chunk_flip_l = refcyc_per_meta_chunk_flip_l; 518 dlg_regs->refcyc_per_meta_chunk_flip_c = refcyc_per_meta_chunk_flip_c; 519 dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, 1); 520 dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l, 1); 521 dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c, 1); 522 dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c, 1); 523 524 dlg_regs->chunk_hdl_adjust_cur0 = 3; 525 dlg_regs->dst_y_offset_cur0 = 0; 526 dlg_regs->chunk_hdl_adjust_cur1 = 3; 527 dlg_regs->dst_y_offset_cur1 = 0; 528 529 dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off 530 531 ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l * dml_pow(2, 10)); 532 ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l * dml_pow(2, 10)); 533 ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10)); 534 ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c * dml_pow(2, 10)); 535 ttu_regs->refcyc_per_req_delivery_pre_cur0 = 536 (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); 537 ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10)); 538 ttu_regs->refcyc_per_req_delivery_pre_cur1 = 0; 539 ttu_regs->refcyc_per_req_delivery_cur1 = 0; 540 ttu_regs->qos_level_low_wm = 0; 541 542 ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal * ref_freq_to_pix_freq); 543 544 ttu_regs->qos_level_flip = 14; 545 ttu_regs->qos_level_fixed_l = 8; 546 ttu_regs->qos_level_fixed_c = 8; 547 ttu_regs->qos_level_fixed_cur0 = 8; 548 ttu_regs->qos_ramp_disable_l = 0; 549 ttu_regs->qos_ramp_disable_c = 0; 550 ttu_regs->qos_ramp_disable_cur0 = 0; 551 ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; 552 553 // CHECK for HW registers' range, assert or clamp 554 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); 555 ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); 556 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); 557 ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); 558 if (dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int) dml_pow(2, 23)) 559 dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1; 560 561 if (dlg_regs->refcyc_per_vm_group_flip >= (unsigned int) dml_pow(2, 23)) 562 dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1; 563 564 if (dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int) dml_pow(2, 23)) 565 dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1; 566 567 if (dlg_regs->refcyc_per_vm_req_flip >= (unsigned int) dml_pow(2, 23)) 568 dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; 569 570 ASSERT(dlg_regs->dst_y_after_scaler < (unsigned int) 8); 571 ASSERT(dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13)); 572 ASSERT(dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17)); 573 if (dual_plane) { 574 if (dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) { 575 // FIXME what so special about chroma, can we just assert? 576 dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u > register max U15.2 %u\n", 577 __func__, dlg_regs->dst_y_per_pte_row_nom_c, (unsigned int)dml_pow(2, 17) - 1); 578 } 579 } 580 ASSERT(dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17)); 581 ASSERT(dlg_regs->dst_y_per_meta_row_nom_c < (unsigned int)dml_pow(2, 17)); 582 583 if (dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) 584 dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; 585 if (dual_plane) { 586 if (dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) 587 dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; 588 } 589 ASSERT(dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13)); 590 if (dual_plane) { 591 ASSERT(dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13)); 592 } 593 594 if (dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) 595 dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; 596 if (dual_plane) { 597 if (dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) 598 dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; 599 } 600 ASSERT(dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); 601 ASSERT(dlg_regs->refcyc_per_meta_chunk_vblank_c < (unsigned int)dml_pow(2, 13)); 602 ASSERT(dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13)); 603 ASSERT(dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13)); 604 ASSERT(dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13)); 605 ASSERT(dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13)); 606 ASSERT(ttu_regs->qos_level_low_wm < dml_pow(2, 14)); 607 ASSERT(ttu_regs->qos_level_high_wm < dml_pow(2, 14)); 608 ASSERT(ttu_regs->min_ttu_vblank < dml_pow(2, 24)); 609 610 print__ttu_regs_st(mode_lib, ttu_regs); 611 print__dlg_regs_st(mode_lib, dlg_regs); 612 dml_print("DML_DLG::%s: Calculation for pipe[%d] done, num_pipes=%d\n", __func__, pipe_idx, num_pipes); 613} 614
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