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display_rq_dlg_calc_314.c
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linux-6.19.14/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1// SPDX-License-Identifier: MIT 2/* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27#include "../display_mode_lib.h" 28#include "../display_mode_vba.h" 29#include "../dml_inline_defs.h" 30#include "display_rq_dlg_calc_314.h" 31 32static bool CalculateBytePerPixelAnd256BBlockSizes( 33 enum source_format_class SourcePixelFormat, 34 enum dm_swizzle_mode SurfaceTiling, 35 unsigned int *BytePerPixelY, 36 unsigned int *BytePerPixelC, 37 double *BytePerPixelDETY, 38 double *BytePerPixelDETC, 39 unsigned int *BlockHeight256BytesY, 40 unsigned int *BlockHeight256BytesC, 41 unsigned int *BlockWidth256BytesY, 42 unsigned int *BlockWidth256BytesC) 43{ 44 if (SourcePixelFormat == dm_444_64) { 45 *BytePerPixelDETY = 8; 46 *BytePerPixelDETC = 0; 47 *BytePerPixelY = 8; 48 *BytePerPixelC = 0; 49 } else if (SourcePixelFormat == dm_444_32 || SourcePixelFormat == dm_rgbe) { 50 *BytePerPixelDETY = 4; 51 *BytePerPixelDETC = 0; 52 *BytePerPixelY = 4; 53 *BytePerPixelC = 0; 54 } else if (SourcePixelFormat == dm_444_16) { 55 *BytePerPixelDETY = 2; 56 *BytePerPixelDETC = 0; 57 *BytePerPixelY = 2; 58 *BytePerPixelC = 0; 59 } else if (SourcePixelFormat == dm_444_8) { 60 *BytePerPixelDETY = 1; 61 *BytePerPixelDETC = 0; 62 *BytePerPixelY = 1; 63 *BytePerPixelC = 0; 64 } else if (SourcePixelFormat == dm_rgbe_alpha) { 65 *BytePerPixelDETY = 4; 66 *BytePerPixelDETC = 1; 67 *BytePerPixelY = 4; 68 *BytePerPixelC = 1; 69 } else if (SourcePixelFormat == dm_420_8) { 70 *BytePerPixelDETY = 1; 71 *BytePerPixelDETC = 2; 72 *BytePerPixelY = 1; 73 *BytePerPixelC = 2; 74 } else if (SourcePixelFormat == dm_420_12) { 75 *BytePerPixelDETY = 2; 76 *BytePerPixelDETC = 4; 77 *BytePerPixelY = 2; 78 *BytePerPixelC = 4; 79 } else { 80 *BytePerPixelDETY = 4.0 / 3; 81 *BytePerPixelDETC = 8.0 / 3; 82 *BytePerPixelY = 2; 83 *BytePerPixelC = 4; 84 } 85 86 if ((SourcePixelFormat == dm_444_64 || SourcePixelFormat == dm_444_32 || SourcePixelFormat == dm_444_16 || SourcePixelFormat == dm_444_8 || SourcePixelFormat == dm_mono_16 87 || SourcePixelFormat == dm_mono_8 || SourcePixelFormat == dm_rgbe)) { 88 if (SurfaceTiling == dm_sw_linear) 89 *BlockHeight256BytesY = 1; 90 else if (SourcePixelFormat == dm_444_64) 91 *BlockHeight256BytesY = 4; 92 else if (SourcePixelFormat == dm_444_8) 93 *BlockHeight256BytesY = 16; 94 else 95 *BlockHeight256BytesY = 8; 96 97 *BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY; 98 *BlockHeight256BytesC = 0; 99 *BlockWidth256BytesC = 0; 100 } else { 101 if (SurfaceTiling == dm_sw_linear) { 102 *BlockHeight256BytesY = 1; 103 *BlockHeight256BytesC = 1; 104 } else if (SourcePixelFormat == dm_rgbe_alpha) { 105 *BlockHeight256BytesY = 8; 106 *BlockHeight256BytesC = 16; 107 } else if (SourcePixelFormat == dm_420_8) { 108 *BlockHeight256BytesY = 16; 109 *BlockHeight256BytesC = 8; 110 } else { 111 *BlockHeight256BytesY = 8; 112 *BlockHeight256BytesC = 8; 113 } 114 *BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY; 115 *BlockWidth256BytesC = 256U / *BytePerPixelC / *BlockHeight256BytesC; 116 } 117 return true; 118} 119 120static bool is_dual_plane(enum source_format_class source_format) 121{ 122 bool ret_val = 0; 123 124 if ((source_format == dm_420_12) || (source_format == dm_420_8) || (source_format == dm_420_10) || (source_format == dm_rgbe_alpha)) 125 ret_val = 1; 126 127 return ret_val; 128} 129 130static double get_refcyc_per_delivery( 131 struct display_mode_lib *mode_lib, 132 double refclk_freq_in_mhz, 133 double pclk_freq_in_mhz, 134 unsigned int odm_combine, 135 unsigned int recout_width, 136 unsigned int hactive, 137 double vratio, 138 double hscale_pixel_rate, 139 unsigned int delivery_width, 140 unsigned int req_per_swath_ub) 141{ 142 double refcyc_per_delivery = 0.0; 143 144 if (vratio <= 1.0) { 145 if (odm_combine) 146 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) ((unsigned int) odm_combine * 2) 147 * dml_min((double) recout_width, (double) hactive / ((unsigned int) odm_combine * 2)) / pclk_freq_in_mhz / (double) req_per_swath_ub; 148 else 149 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width / pclk_freq_in_mhz / (double) req_per_swath_ub; 150 } else { 151 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width / (double) hscale_pixel_rate / (double) req_per_swath_ub; 152 } 153 154#ifdef __DML_RQ_DLG_CALC_DEBUG__ 155 dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz); 156 dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz); 157 dml_print("DML_DLG: %s: recout_width = %d\n", __func__, recout_width); 158 dml_print("DML_DLG: %s: vratio = %3.2f\n", __func__, vratio); 159 dml_print("DML_DLG: %s: req_per_swath_ub = %d\n", __func__, req_per_swath_ub); 160 dml_print("DML_DLG: %s: hscale_pixel_rate = %3.2f\n", __func__, hscale_pixel_rate); 161 dml_print("DML_DLG: %s: delivery_width = %d\n", __func__, delivery_width); 162 dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery); 163#endif 164 165 return refcyc_per_delivery; 166 167} 168 169static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size) 170{ 171 if (tile_size == dm_256k_tile) 172 return (256 * 1024); 173 else if (tile_size == dm_64k_tile) 174 return (64 * 1024); 175 else 176 return (4 * 1024); 177} 178 179static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib, display_data_rq_regs_st *rq_regs, const display_data_rq_sizing_params_st *rq_sizing) 180{ 181 print__data_rq_sizing_params_st(mode_lib, rq_sizing); 182 183 rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10; 184 185 if (rq_sizing->min_chunk_bytes == 0) 186 rq_regs->min_chunk_size = 0; 187 else 188 rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1; 189 190 rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10; 191 if (rq_sizing->min_meta_chunk_bytes == 0) 192 rq_regs->min_meta_chunk_size = 0; 193 else 194 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1; 195 196 rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6; 197 rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6; 198} 199 200static void extract_rq_regs(struct display_mode_lib *mode_lib, display_rq_regs_st *rq_regs, const display_rq_params_st *rq_param) 201{ 202 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; 203 unsigned int detile_buf_plane1_addr = 0; 204 205 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); 206 207 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), 1) - 3; 208 209 if (rq_param->yuv420) { 210 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); 211 rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), 1) - 3; 212 } 213 214 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); 215 rq_regs->rq_regs_c.swath_height = dml_log2(rq_param->dlg.rq_c.swath_height); 216 217 // FIXME: take the max between luma, chroma chunk size? 218 // okay for now, as we are setting chunk_bytes to 8kb anyways 219 if (rq_param->sizing.rq_l.chunk_bytes >= 32 * 1024 || (rq_param->yuv420 && rq_param->sizing.rq_c.chunk_bytes >= 32 * 1024)) { //32kb 220 rq_regs->drq_expansion_mode = 0; 221 } else { 222 rq_regs->drq_expansion_mode = 2; 223 } 224 rq_regs->prq_expansion_mode = 1; 225 rq_regs->mrq_expansion_mode = 1; 226 rq_regs->crq_expansion_mode = 1; 227 228 // Note: detile_buf_plane1_addr is in unit of 1KB 229 if (rq_param->yuv420) { 230 if ((double) rq_param->misc.rq_l.stored_swath_bytes / (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { 231 detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma 232#ifdef __DML_RQ_DLG_CALC_DEBUG__ 233 dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d (1/2 to chroma)\n", __func__, detile_buf_plane1_addr); 234#endif 235 } else { 236 detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 1024, 0) / 1024.0; // 2/3 to luma 237#ifdef __DML_RQ_DLG_CALC_DEBUG__ 238 dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d (1/3 chroma)\n", __func__, detile_buf_plane1_addr); 239#endif 240 } 241 } 242 rq_regs->plane1_base_address = detile_buf_plane1_addr; 243 244#ifdef __DML_RQ_DLG_CALC_DEBUG__ 245 dml_print("DML_DLG: %s: detile_buf_size_in_bytes = %0d\n", __func__, detile_buf_size_in_bytes); 246 dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d\n", __func__, detile_buf_plane1_addr); 247 dml_print("DML_DLG: %s: plane1_base_address = %0d\n", __func__, rq_regs->plane1_base_address); 248 dml_print("DML_DLG: %s: rq_l.stored_swath_bytes = %0d\n", __func__, rq_param->misc.rq_l.stored_swath_bytes); 249 dml_print("DML_DLG: %s: rq_c.stored_swath_bytes = %0d\n", __func__, rq_param->misc.rq_c.stored_swath_bytes); 250 dml_print("DML_DLG: %s: rq_l.swath_height = %0d\n", __func__, rq_param->dlg.rq_l.swath_height); 251 dml_print("DML_DLG: %s: rq_c.swath_height = %0d\n", __func__, rq_param->dlg.rq_c.swath_height); 252#endif 253} 254 255static void handle_det_buf_split(struct display_mode_lib *mode_lib, display_rq_params_st *rq_param, const display_pipe_source_params_st *pipe_src_param) 256{ 257 unsigned int total_swath_bytes = 0; 258 unsigned int swath_bytes_l = 0; 259 unsigned int swath_bytes_c = 0; 260 unsigned int full_swath_bytes_packed_l = 0; 261 unsigned int full_swath_bytes_packed_c = 0; 262 bool req128_l = 0; 263 bool req128_c = 0; 264 bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear); 265 bool surf_vert = (pipe_src_param->source_scan == dm_vert); 266 unsigned int log2_swath_height_l = 0; 267 unsigned int log2_swath_height_c = 0; 268 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; 269 270 full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes; 271 full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes; 272 273#ifdef __DML_RQ_DLG_CALC_DEBUG__ 274 dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n", __func__, full_swath_bytes_packed_l); 275 dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n", __func__, full_swath_bytes_packed_c); 276#endif 277 278 if (rq_param->yuv420_10bpc) { 279 full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2.0 / 3.0, 256, 1) + 256; 280 full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2.0 / 3.0, 256, 1) + 256; 281#ifdef __DML_RQ_DLG_CALC_DEBUG__ 282 dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d (3-2 packing)\n", __func__, full_swath_bytes_packed_l); 283 dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d (3-2 packing)\n", __func__, full_swath_bytes_packed_c); 284#endif 285 } 286 287 if (rq_param->yuv420) 288 total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c; 289 else 290 total_swath_bytes = 2 * full_swath_bytes_packed_l; 291 292#ifdef __DML_RQ_DLG_CALC_DEBUG__ 293 dml_print("DML_DLG: %s: total_swath_bytes = %0d\n", __func__, total_swath_bytes); 294 dml_print("DML_DLG: %s: detile_buf_size_in_bytes = %0d\n", __func__, detile_buf_size_in_bytes); 295#endif 296 297 if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request 298 req128_l = 0; 299 req128_c = 0; 300 swath_bytes_l = full_swath_bytes_packed_l; 301 swath_bytes_c = full_swath_bytes_packed_c; 302 } else if (!rq_param->yuv420) { 303 req128_l = 1; 304 req128_c = 0; 305 swath_bytes_c = full_swath_bytes_packed_c; 306 swath_bytes_l = full_swath_bytes_packed_l / 2; 307 } else if ((double) full_swath_bytes_packed_l / (double) full_swath_bytes_packed_c < 1.5) { 308 req128_l = 0; 309 req128_c = 1; 310 swath_bytes_l = full_swath_bytes_packed_l; 311 swath_bytes_c = full_swath_bytes_packed_c / 2; 312 313 total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c; 314 315 if (total_swath_bytes > detile_buf_size_in_bytes) { 316 req128_l = 1; 317 swath_bytes_l = full_swath_bytes_packed_l / 2; 318 } 319 } else { 320 req128_l = 1; 321 req128_c = 0; 322 swath_bytes_l = full_swath_bytes_packed_l / 2; 323 swath_bytes_c = full_swath_bytes_packed_c; 324 325 total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c; 326 327 if (total_swath_bytes > detile_buf_size_in_bytes) { 328 req128_c = 1; 329 swath_bytes_c = full_swath_bytes_packed_c / 2; 330 } 331 } 332 333 if (rq_param->yuv420) 334 total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c; 335 else 336 total_swath_bytes = 2 * swath_bytes_l; 337 338 rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l; 339 rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c; 340 341#ifdef __DML_RQ_DLG_CALC_DEBUG__ 342 dml_print("DML_DLG: %s: total_swath_bytes = %0d\n", __func__, total_swath_bytes); 343 dml_print("DML_DLG: %s: rq_l.stored_swath_bytes = %0d\n", __func__, rq_param->misc.rq_l.stored_swath_bytes); 344 dml_print("DML_DLG: %s: rq_c.stored_swath_bytes = %0d\n", __func__, rq_param->misc.rq_c.stored_swath_bytes); 345#endif 346 if (surf_linear) { 347 log2_swath_height_l = 0; 348 log2_swath_height_c = 0; 349 } else { 350 unsigned int swath_height_l; 351 unsigned int swath_height_c; 352 353 if (!surf_vert) { 354 swath_height_l = rq_param->misc.rq_l.blk256_height; 355 swath_height_c = rq_param->misc.rq_c.blk256_height; 356 } else { 357 swath_height_l = rq_param->misc.rq_l.blk256_width; 358 swath_height_c = rq_param->misc.rq_c.blk256_width; 359 } 360 361 if (swath_height_l > 0) 362 log2_swath_height_l = dml_log2(swath_height_l); 363 364 if (req128_l && log2_swath_height_l > 0) 365 log2_swath_height_l -= 1; 366 367 if (swath_height_c > 0) 368 log2_swath_height_c = dml_log2(swath_height_c); 369 370 if (req128_c && log2_swath_height_c > 0) 371 log2_swath_height_c -= 1; 372 } 373 374 rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l; 375 rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c; 376 377#ifdef __DML_RQ_DLG_CALC_DEBUG__ 378 dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l); 379 dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c); 380 dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n", __func__, full_swath_bytes_packed_l); 381 dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n", __func__, full_swath_bytes_packed_c); 382 dml_print("DML_DLG: %s: swath_height luma = %0d\n", __func__, rq_param->dlg.rq_l.swath_height); 383 dml_print("DML_DLG: %s: swath_height chroma = %0d\n", __func__, rq_param->dlg.rq_c.swath_height); 384#endif 385} 386 387static void get_meta_and_pte_attr( 388 struct display_mode_lib *mode_lib, 389 display_data_rq_dlg_params_st *rq_dlg_param, 390 display_data_rq_misc_params_st *rq_misc_param, 391 display_data_rq_sizing_params_st *rq_sizing_param, 392 unsigned int vp_width, 393 unsigned int vp_height, 394 unsigned int data_pitch, 395 unsigned int meta_pitch, 396 unsigned int source_format, 397 unsigned int tiling, 398 unsigned int macro_tile_size, 399 unsigned int source_scan, 400 unsigned int hostvm_enable, 401 unsigned int is_chroma, 402 unsigned int surface_height) 403{ 404 bool surf_linear = (tiling == dm_sw_linear); 405 bool surf_vert = (source_scan == dm_vert); 406 407 unsigned int bytes_per_element; 408 unsigned int bytes_per_element_y; 409 unsigned int bytes_per_element_c; 410 411 unsigned int blk256_width = 0; 412 unsigned int blk256_height = 0; 413 414 unsigned int blk256_width_y = 0; 415 unsigned int blk256_height_y = 0; 416 unsigned int blk256_width_c = 0; 417 unsigned int blk256_height_c = 0; 418 unsigned int log2_bytes_per_element; 419 unsigned int log2_blk256_width; 420 unsigned int log2_blk256_height; 421 unsigned int blk_bytes; 422 unsigned int log2_blk_bytes; 423 unsigned int log2_blk_height; 424 unsigned int log2_blk_width; 425 unsigned int log2_meta_req_bytes; 426 unsigned int log2_meta_req_height; 427 unsigned int log2_meta_req_width; 428 unsigned int meta_req_width; 429 unsigned int meta_req_height; 430 unsigned int log2_meta_row_height; 431 unsigned int meta_row_width_ub; 432 unsigned int log2_meta_chunk_bytes; 433 unsigned int log2_meta_chunk_height; 434 435 //full sized meta chunk width in unit of data elements 436 unsigned int log2_meta_chunk_width; 437 unsigned int log2_min_meta_chunk_bytes; 438 unsigned int min_meta_chunk_width; 439 unsigned int meta_chunk_width; 440 unsigned int meta_chunk_per_row_int; 441 unsigned int meta_row_remainder; 442 unsigned int meta_chunk_threshold; 443 unsigned int meta_blk_height; 444 unsigned int meta_surface_bytes; 445 unsigned int vmpg_bytes; 446 unsigned int meta_pte_req_per_frame_ub; 447 unsigned int meta_pte_bytes_per_frame_ub; 448 const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.gpuvm_min_page_size_bytes); 449 const bool dual_plane_en = is_dual_plane((enum source_format_class) (source_format)); 450 const unsigned int dpte_buf_in_pte_reqs = 451 dual_plane_en ? (is_chroma ? mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma : mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma) : (mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma 452 + mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma); 453 454 unsigned int log2_vmpg_height = 0; 455 unsigned int log2_vmpg_width = 0; 456 unsigned int log2_dpte_req_height_ptes = 0; 457 unsigned int log2_dpte_req_height = 0; 458 unsigned int log2_dpte_req_width = 0; 459 unsigned int log2_dpte_row_height_linear = 0; 460 unsigned int log2_dpte_row_height = 0; 461 unsigned int log2_dpte_group_width = 0; 462 unsigned int dpte_row_width_ub = 0; 463 unsigned int dpte_req_height = 0; 464 unsigned int dpte_req_width = 0; 465 unsigned int dpte_group_width = 0; 466 unsigned int log2_dpte_group_bytes = 0; 467 unsigned int log2_dpte_group_length = 0; 468 double byte_per_pixel_det_y; 469 double byte_per_pixel_det_c; 470 471 CalculateBytePerPixelAnd256BBlockSizes( 472 (enum source_format_class) (source_format), 473 (enum dm_swizzle_mode) (tiling), 474 &bytes_per_element_y, 475 &bytes_per_element_c, 476 &byte_per_pixel_det_y, 477 &byte_per_pixel_det_c, 478 &blk256_height_y, 479 &blk256_height_c, 480 &blk256_width_y, 481 &blk256_width_c); 482 483 if (!is_chroma) { 484 blk256_width = blk256_width_y; 485 blk256_height = blk256_height_y; 486 bytes_per_element = bytes_per_element_y; 487 } else { 488 blk256_width = blk256_width_c; 489 blk256_height = blk256_height_c; 490 bytes_per_element = bytes_per_element_c; 491 } 492 493 log2_bytes_per_element = dml_log2(bytes_per_element); 494 495 dml_print("DML_DLG: %s: surf_linear = %d\n", __func__, surf_linear); 496 dml_print("DML_DLG: %s: surf_vert = %d\n", __func__, surf_vert); 497 dml_print("DML_DLG: %s: blk256_width = %d\n", __func__, blk256_width); 498 dml_print("DML_DLG: %s: blk256_height = %d\n", __func__, blk256_height); 499 500 log2_blk256_width = dml_log2((double) blk256_width); 501 log2_blk256_height = dml_log2((double) blk256_height); 502 blk_bytes = surf_linear ? 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size); 503 log2_blk_bytes = dml_log2((double) blk_bytes); 504 505 // remember log rule 506 // "+" in log is multiply 507 // "-" in log is divide 508 // "/2" is like square root 509 // blk is vertical biased 510 if (tiling != dm_sw_linear) 511 log2_blk_height = log2_blk256_height + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); 512 else 513 log2_blk_height = 0; // blk height of 1 514 515 log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height; 516 517 if (!surf_vert) { 518 unsigned int temp; 519 520 temp = dml_round_to_multiple(vp_width - 1, blk256_width, 1) + blk256_width; 521 if (data_pitch < blk256_width) { 522 dml_print("WARNING: DML_DLG: %s: swath_size calculation ignoring data_pitch=%u < blk256_width=%u\n", __func__, data_pitch, blk256_width); 523 } else { 524 if (temp > data_pitch) { 525 if (data_pitch >= vp_width) 526 temp = data_pitch; 527 else 528 dml_print("WARNING: DML_DLG: %s: swath_size calculation ignoring data_pitch=%u < vp_width=%u\n", __func__, data_pitch, vp_width); 529 } 530 } 531 rq_dlg_param->swath_width_ub = temp; 532 rq_dlg_param->req_per_swath_ub = temp >> log2_blk256_width; 533 } else { 534 unsigned int temp; 535 536 temp = dml_round_to_multiple(vp_height - 1, blk256_height, 1) + blk256_height; 537 if (surface_height < blk256_height) { 538 dml_print("WARNING: DML_DLG: %s swath_size calculation ignored surface_height=%u < blk256_height=%u\n", __func__, surface_height, blk256_height); 539 } else { 540 if (temp > surface_height) { 541 if (surface_height >= vp_height) 542 temp = surface_height; 543 else 544 dml_print("WARNING: DML_DLG: %s swath_size calculation ignored surface_height=%u < vp_height=%u\n", __func__, surface_height, vp_height); 545 } 546 } 547 rq_dlg_param->swath_width_ub = temp; 548 rq_dlg_param->req_per_swath_ub = temp >> log2_blk256_height; 549 } 550 551 if (!surf_vert) 552 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height * bytes_per_element; 553 else 554 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width * bytes_per_element; 555 556 rq_misc_param->blk256_height = blk256_height; 557 rq_misc_param->blk256_width = blk256_width; 558 559 // ------- 560 // meta 561 // ------- 562 log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element 563 564 // each 64b meta request for dcn is 8x8 meta elements and 565 // a meta element covers one 256b block of the data surface. 566 log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256 567 log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element - log2_meta_req_height; 568 meta_req_width = 1 << log2_meta_req_width; 569 meta_req_height = 1 << log2_meta_req_height; 570 571 // the dimensions of a meta row are meta_row_width x meta_row_height in elements. 572 // calculate upper bound of the meta_row_width 573 if (!surf_vert) { 574 log2_meta_row_height = log2_meta_req_height; 575 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) + meta_req_width; 576 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; 577 } else { 578 log2_meta_row_height = log2_meta_req_width; 579 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) + meta_req_height; 580 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; 581 } 582 rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64; 583 584 rq_dlg_param->meta_row_height = 1 << log2_meta_row_height; 585 586 log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes); 587 log2_meta_chunk_height = log2_meta_row_height; 588 589 //full sized meta chunk width in unit of data elements 590 log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element - log2_meta_chunk_height; 591 log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes); 592 min_meta_chunk_width = 1 << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element - log2_meta_chunk_height); 593 meta_chunk_width = 1 << log2_meta_chunk_width; 594 meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width); 595 meta_row_remainder = meta_row_width_ub % meta_chunk_width; 596 meta_chunk_threshold = 0; 597 meta_blk_height = blk256_height * 64; 598 meta_surface_bytes = meta_pitch * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) + meta_blk_height) * bytes_per_element / 256; 599 vmpg_bytes = mode_lib->soc.gpuvm_min_page_size_bytes; 600 meta_pte_req_per_frame_ub = (dml_round_to_multiple(meta_surface_bytes - vmpg_bytes, 8 * vmpg_bytes, 1) + 8 * vmpg_bytes) / (8 * vmpg_bytes); 601 meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request 602 rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub; 603 604 dml_print("DML_DLG: %s: meta_blk_height = %d\n", __func__, meta_blk_height); 605 dml_print("DML_DLG: %s: meta_surface_bytes = %d\n", __func__, meta_surface_bytes); 606 dml_print("DML_DLG: %s: meta_pte_req_per_frame_ub = %d\n", __func__, meta_pte_req_per_frame_ub); 607 dml_print("DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n", __func__, meta_pte_bytes_per_frame_ub); 608 609 if (!surf_vert) 610 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; 611 else 612 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; 613 614 if (meta_row_remainder <= meta_chunk_threshold) 615 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1; 616 else 617 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2; 618 619 // ------ 620 // dpte 621 // ------ 622 if (surf_linear) 623 log2_vmpg_height = 0; // one line high 624 else 625 log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height; 626 627 log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height; 628 629 // only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4. 630 if (surf_linear) { //one 64B PTE request returns 8 PTEs 631 log2_dpte_req_height_ptes = 0; 632 log2_dpte_req_width = log2_vmpg_width + 3; 633 log2_dpte_req_height = 0; 634 } else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size 635 //one 64B req gives 8x1 PTEs for 4KB tile 636 log2_dpte_req_height_ptes = 0; 637 log2_dpte_req_width = log2_blk_width + 3; 638 log2_dpte_req_height = log2_blk_height + 0; 639 } else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB 640 //two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB 641 log2_dpte_req_height_ptes = 4; 642 log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width 643 log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height 644 } else { //64KB page size and must 64KB tile block 645 //one 64B req gives 8x1 PTEs for 64KB tile 646 log2_dpte_req_height_ptes = 0; 647 log2_dpte_req_width = log2_blk_width + 3; 648 log2_dpte_req_height = log2_blk_height + 0; 649 } 650 651 // The dpte request dimensions in data elements is dpte_req_width x dpte_req_height 652 // log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent 653 // That depends on the pte shape (i.e. 8x1, 4x2, 2x4) 654 //log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes; 655 //log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes; 656 dpte_req_height = 1 << log2_dpte_req_height; 657 dpte_req_width = 1 << log2_dpte_req_width; 658 659 // calculate pitch dpte row buffer can hold 660 // round the result down to a power of two. 661 if (surf_linear) { 662 unsigned int dpte_row_height; 663 664 log2_dpte_row_height_linear = dml_floor(dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1); 665 666 dml_print("DML_DLG: %s: is_chroma = %d\n", __func__, is_chroma); 667 dml_print("DML_DLG: %s: dpte_buf_in_pte_reqs = %d\n", __func__, dpte_buf_in_pte_reqs); 668 dml_print("DML_DLG: %s: log2_dpte_row_height_linear = %d\n", __func__, log2_dpte_row_height_linear); 669 670 ASSERT(log2_dpte_row_height_linear >= 3); 671 672 if (log2_dpte_row_height_linear > 7) 673 log2_dpte_row_height_linear = 7; 674 675 log2_dpte_row_height = log2_dpte_row_height_linear; 676 // For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary. 677 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering. 678 dpte_row_height = 1 << log2_dpte_row_height; 679 dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1, dpte_req_width, 1) + dpte_req_width; 680 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; 681 } else { 682 // the upper bound of the dpte_row_width without dependency on viewport position follows. 683 // for tiled mode, row height is the same as req height and row store up to vp size upper bound 684 if (!surf_vert) { 685 log2_dpte_row_height = log2_dpte_req_height; 686 dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1) + dpte_req_width; 687 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; 688 } else { 689 log2_dpte_row_height = (log2_blk_width < log2_dpte_req_width) ? log2_blk_width : log2_dpte_req_width; 690 dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1) + dpte_req_height; 691 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height; 692 } 693 } 694 if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB 695 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request 696 else 697 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request 698 699 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; 700 701 // the dpte_group_bytes is reduced for the specific case of vertical 702 // access of a tile surface that has dpte request of 8x1 ptes. 703 if (hostvm_enable) 704 rq_sizing_param->dpte_group_bytes = 512; 705 else { 706 if (!surf_linear && (log2_dpte_req_height_ptes == 0) && surf_vert) //reduced, in this case, will have page fault within a group 707 rq_sizing_param->dpte_group_bytes = 512; 708 else 709 rq_sizing_param->dpte_group_bytes = 2048; 710 } 711 712 //since pte request size is 64byte, the number of data pte requests per full sized group is as follows. 713 log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes); 714 log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests 715 716 // full sized data pte group width in elements 717 if (!surf_vert) 718 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width; 719 else 720 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height; 721 722 //But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B 723 if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB 724 log2_dpte_group_width = log2_dpte_group_width - 1; 725 726 dpte_group_width = 1 << log2_dpte_group_width; 727 728 // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, 729 // the upper bound for the dpte groups per row is as follows. 730 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, 1); 731} 732 733static void get_surf_rq_param( 734 struct display_mode_lib *mode_lib, 735 display_data_rq_sizing_params_st *rq_sizing_param, 736 display_data_rq_dlg_params_st *rq_dlg_param, 737 display_data_rq_misc_params_st *rq_misc_param, 738 const display_pipe_params_st *pipe_param, 739 bool is_chroma, 740 bool is_alpha) 741{ 742 unsigned int vp_width = 0; 743 unsigned int vp_height = 0; 744 unsigned int data_pitch = 0; 745 unsigned int meta_pitch = 0; 746 unsigned int surface_height = 0; 747 unsigned int ppe = 1; 748 749 // FIXME check if ppe apply for both luma and chroma in 422 case 750 if (is_chroma | is_alpha) { 751 vp_width = pipe_param->src.viewport_width_c / ppe; 752 vp_height = pipe_param->src.viewport_height_c; 753 data_pitch = pipe_param->src.data_pitch_c; 754 meta_pitch = pipe_param->src.meta_pitch_c; 755 surface_height = pipe_param->src.surface_height_y / 2.0; 756 } else { 757 vp_width = pipe_param->src.viewport_width / ppe; 758 vp_height = pipe_param->src.viewport_height; 759 data_pitch = pipe_param->src.data_pitch; 760 meta_pitch = pipe_param->src.meta_pitch; 761 surface_height = pipe_param->src.surface_height_y; 762 } 763 764 if (pipe_param->dest.odm_combine) { 765 unsigned int access_dir; 766 unsigned int full_src_vp_width; 767 unsigned int hactive_odm; 768 unsigned int src_hactive_odm; 769 770 access_dir = (pipe_param->src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed 771 hactive_odm = pipe_param->dest.hactive / ((unsigned int) pipe_param->dest.odm_combine * 2); 772 if (is_chroma) { 773 full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width; 774 src_hactive_odm = pipe_param->scale_ratio_depth.hscl_ratio_c * hactive_odm; 775 } else { 776 full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width; 777 src_hactive_odm = pipe_param->scale_ratio_depth.hscl_ratio * hactive_odm; 778 } 779 780 if (access_dir == 0) { 781 vp_width = dml_min(full_src_vp_width, src_hactive_odm); 782 dml_print("DML_DLG: %s: vp_width = %d\n", __func__, vp_width); 783 } else { 784 vp_height = dml_min(full_src_vp_width, src_hactive_odm); 785 dml_print("DML_DLG: %s: vp_height = %d\n", __func__, vp_height); 786 787 } 788 dml_print("DML_DLG: %s: full_src_vp_width = %d\n", __func__, full_src_vp_width); 789 dml_print("DML_DLG: %s: hactive_odm = %d\n", __func__, hactive_odm); 790 dml_print("DML_DLG: %s: src_hactive_odm = %d\n", __func__, src_hactive_odm); 791 } 792 793 rq_sizing_param->chunk_bytes = 8192; 794 795 if (is_alpha) 796 rq_sizing_param->chunk_bytes = 4096; 797 798 if (rq_sizing_param->chunk_bytes == 64 * 1024) 799 rq_sizing_param->min_chunk_bytes = 0; 800 else 801 rq_sizing_param->min_chunk_bytes = 1024; 802 803 rq_sizing_param->meta_chunk_bytes = 2048; 804 rq_sizing_param->min_meta_chunk_bytes = 256; 805 806 if (pipe_param->src.hostvm) 807 rq_sizing_param->mpte_group_bytes = 512; 808 else 809 rq_sizing_param->mpte_group_bytes = 2048; 810 811 get_meta_and_pte_attr( 812 mode_lib, 813 rq_dlg_param, 814 rq_misc_param, 815 rq_sizing_param, 816 vp_width, 817 vp_height, 818 data_pitch, 819 meta_pitch, 820 pipe_param->src.source_format, 821 pipe_param->src.sw_mode, 822 pipe_param->src.macro_tile_size, 823 pipe_param->src.source_scan, 824 pipe_param->src.hostvm, 825 is_chroma, 826 surface_height); 827} 828 829static void dml_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, display_rq_params_st *rq_param, const display_pipe_params_st *pipe_param) 830{ 831 // get param for luma surface 832 rq_param->yuv420 = pipe_param->src.source_format == dm_420_8 || pipe_param->src.source_format == dm_420_10 || pipe_param->src.source_format == dm_rgbe_alpha 833 || pipe_param->src.source_format == dm_420_12; 834 835 rq_param->yuv420_10bpc = pipe_param->src.source_format == dm_420_10; 836 837 rq_param->rgbe_alpha = (pipe_param->src.source_format == dm_rgbe_alpha) ? 1 : 0; 838 839 get_surf_rq_param(mode_lib, &(rq_param->sizing.rq_l), &(rq_param->dlg.rq_l), &(rq_param->misc.rq_l), pipe_param, 0, 0); 840 841 if (is_dual_plane((enum source_format_class) (pipe_param->src.source_format))) { 842 // get param for chroma surface 843 get_surf_rq_param(mode_lib, &(rq_param->sizing.rq_c), &(rq_param->dlg.rq_c), &(rq_param->misc.rq_c), pipe_param, 1, rq_param->rgbe_alpha); 844 } 845 846 // calculate how to split the det buffer space between luma and chroma 847 handle_det_buf_split(mode_lib, rq_param, &pipe_param->src); 848 print__rq_params_st(mode_lib, rq_param); 849} 850 851void dml314_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, display_rq_regs_st *rq_regs, const display_pipe_params_st *pipe_param) 852{ 853 display_rq_params_st rq_param = {0}; 854 855 memset(rq_regs, 0, sizeof(*rq_regs)); 856 dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param); 857 extract_rq_regs(mode_lib, rq_regs, &rq_param); 858 859 print__rq_regs_st(mode_lib, rq_regs); 860} 861 862static void calculate_ttu_cursor( 863 struct display_mode_lib *mode_lib, 864 double *refcyc_per_req_delivery_pre_cur, 865 double *refcyc_per_req_delivery_cur, 866 double refclk_freq_in_mhz, 867 double ref_freq_to_pix_freq, 868 double hscale_pixel_rate_l, 869 double hscl_ratio, 870 double vratio_pre_l, 871 double vratio_l, 872 unsigned int cur_width, 873 enum cursor_bpp cur_bpp) 874{ 875 unsigned int cur_src_width = cur_width; 876 unsigned int cur_req_size = 0; 877 unsigned int cur_req_width = 0; 878 double cur_width_ub = 0.0; 879 double cur_req_per_width = 0.0; 880 double hactive_cur = 0.0; 881 882 ASSERT(cur_src_width <= 256); 883 884 *refcyc_per_req_delivery_pre_cur = 0.0; 885 *refcyc_per_req_delivery_cur = 0.0; 886 if (cur_src_width > 0) { 887 unsigned int cur_bit_per_pixel = 0; 888 889 if (cur_bpp == dm_cur_2bit) { 890 cur_req_size = 64; // byte 891 cur_bit_per_pixel = 2; 892 } else { // 32bit 893 cur_bit_per_pixel = 32; 894 if (cur_src_width >= 1 && cur_src_width <= 16) 895 cur_req_size = 64; 896 else if (cur_src_width >= 17 && cur_src_width <= 31) 897 cur_req_size = 128; 898 else 899 cur_req_size = 256; 900 } 901 902 cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0); 903 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) * (double) cur_req_width; 904 cur_req_per_width = cur_width_ub / (double) cur_req_width; 905 hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor 906 907 if (vratio_pre_l <= 1.0) 908 *refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq / (double) cur_req_per_width; 909 else 910 *refcyc_per_req_delivery_pre_cur = (double) refclk_freq_in_mhz * (double) cur_src_width / hscale_pixel_rate_l / (double) cur_req_per_width; 911 912 ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13)); 913 914 if (vratio_l <= 1.0) 915 *refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq / (double) cur_req_per_width; 916 else 917 *refcyc_per_req_delivery_cur = (double) refclk_freq_in_mhz * (double) cur_src_width / hscale_pixel_rate_l / (double) cur_req_per_width; 918 919 dml_print("DML_DLG: %s: cur_req_width = %d\n", __func__, cur_req_width); 920 dml_print("DML_DLG: %s: cur_width_ub = %3.2f\n", __func__, cur_width_ub); 921 dml_print("DML_DLG: %s: cur_req_per_width = %3.2f\n", __func__, cur_req_per_width); 922 dml_print("DML_DLG: %s: hactive_cur = %3.2f\n", __func__, hactive_cur); 923 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur = %3.2f\n", __func__, *refcyc_per_req_delivery_pre_cur); 924 dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur = %3.2f\n", __func__, *refcyc_per_req_delivery_cur); 925 926 ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13)); 927 } 928} 929 930// Note: currently taken in as is. 931// Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma. 932static void dml_rq_dlg_get_dlg_params( 933 struct display_mode_lib *mode_lib, 934 const display_e2e_pipe_params_st *e2e_pipe_param, 935 const unsigned int num_pipes, 936 const unsigned int pipe_idx, 937 display_dlg_regs_st *disp_dlg_regs, 938 display_ttu_regs_st *disp_ttu_regs, 939 const display_rq_dlg_params_st *rq_dlg_param, 940 const display_dlg_sys_params_st *dlg_sys_param, 941 const bool cstate_en, 942 const bool pstate_en, 943 const bool vm_en, 944 const bool ignore_viewport_pos, 945 const bool immediate_flip_support) 946{ 947 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; 948 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; 949 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; 950 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; 951 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; 952 unsigned int pipe_index_in_combine[DC__NUM_PIPES__MAX]; 953 954 // ------------------------- 955 // Section 1.15.2.1: OTG dependent Params 956 // ------------------------- 957 // Timing 958 unsigned int htotal = dst->htotal; 959 unsigned int hblank_end = dst->hblank_end; 960 unsigned int vblank_start = dst->vblank_start; 961 unsigned int vblank_end = dst->vblank_end; 962 963 double dppclk_freq_in_mhz = clks->dppclk_mhz; 964 double refclk_freq_in_mhz = clks->refclk_mhz; 965 double pclk_freq_in_mhz = dst->pixel_rate_mhz; 966 bool interlaced = dst->interlaced; 967 double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; 968 double min_ttu_vblank; 969 unsigned int dlg_vblank_start; 970 bool dual_plane; 971 unsigned int access_dir; 972 unsigned int vp_height_l; 973 unsigned int vp_width_l; 974 unsigned int vp_height_c; 975 unsigned int vp_width_c; 976 977 // Scaling 978 unsigned int htaps_l; 979 unsigned int htaps_c; 980 double hratio_l; 981 double hratio_c; 982 double vratio_l; 983 double vratio_c; 984 985 unsigned int swath_width_ub_l; 986 unsigned int dpte_groups_per_row_ub_l; 987 unsigned int swath_width_ub_c; 988 unsigned int dpte_groups_per_row_ub_c; 989 990 unsigned int meta_chunks_per_row_ub_l; 991 unsigned int meta_chunks_per_row_ub_c; 992 unsigned int vupdate_offset; 993 unsigned int vupdate_width; 994 unsigned int vready_offset; 995 996 unsigned int vstartup_start; 997 unsigned int dst_x_after_scaler; 998 unsigned int dst_y_after_scaler; 999 double dst_y_prefetch; 1000 double dst_y_per_vm_vblank; 1001 double dst_y_per_row_vblank; 1002 double dst_y_per_vm_flip; 1003 double dst_y_per_row_flip; 1004 double max_dst_y_per_vm_vblank; 1005 double max_dst_y_per_row_vblank; 1006 double vratio_pre_l; 1007 double vratio_pre_c; 1008 unsigned int req_per_swath_ub_l; 1009 unsigned int req_per_swath_ub_c; 1010 unsigned int meta_row_height_l; 1011 unsigned int meta_row_height_c; 1012 unsigned int swath_width_pixels_ub_l; 1013 unsigned int swath_width_pixels_ub_c; 1014 unsigned int scaler_rec_in_width_l; 1015 unsigned int scaler_rec_in_width_c; 1016 unsigned int dpte_row_height_l; 1017 unsigned int dpte_row_height_c; 1018 double hscale_pixel_rate_l; 1019 double hscale_pixel_rate_c; 1020 double min_hratio_fact_l; 1021 double min_hratio_fact_c; 1022 double refcyc_per_line_delivery_pre_l; 1023 double refcyc_per_line_delivery_pre_c; 1024 double refcyc_per_line_delivery_l; 1025 double refcyc_per_line_delivery_c; 1026 1027 double refcyc_per_req_delivery_pre_l; 1028 double refcyc_per_req_delivery_pre_c; 1029 double refcyc_per_req_delivery_l; 1030 double refcyc_per_req_delivery_c; 1031 1032 unsigned int full_recout_width; 1033 double refcyc_per_req_delivery_pre_cur0; 1034 double refcyc_per_req_delivery_cur0; 1035 double refcyc_per_req_delivery_pre_cur1; 1036 double refcyc_per_req_delivery_cur1; 1037 unsigned int vba__min_dst_y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // FROM VBA 1038 unsigned int vba__vready_after_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 1039 1040 float vba__refcyc_per_line_delivery_pre_l = get_refcyc_per_line_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 1041 float vba__refcyc_per_line_delivery_l = get_refcyc_per_line_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 1042 1043 float vba__refcyc_per_req_delivery_pre_l = get_refcyc_per_req_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 1044 float vba__refcyc_per_req_delivery_l = get_refcyc_per_req_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 1045 1046 memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); 1047 memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs)); 1048 1049 dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en); 1050 dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en); 1051 dml_print("DML_DLG: %s: vm_en = %d\n", __func__, vm_en); 1052 dml_print("DML_DLG: %s: ignore_viewport_pos = %d\n", __func__, ignore_viewport_pos); 1053 dml_print("DML_DLG: %s: immediate_flip_support = %d\n", __func__, immediate_flip_support); 1054 1055 dml_print("DML_DLG: %s: dppclk_freq_in_mhz = %3.2f\n", __func__, dppclk_freq_in_mhz); 1056 dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz); 1057 dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz); 1058 dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced); ASSERT(ref_freq_to_pix_freq < 4.0); 1059 1060 disp_dlg_regs->ref_freq_to_pix_freq = (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); 1061 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8)); 1062 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits 1063 1064 //set_prefetch_mode(mode_lib, cstate_en, pstate_en, ignore_viewport_pos, immediate_flip_support); 1065 min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 1066 1067 dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; 1068 disp_dlg_regs->min_dst_y_next_start_us = 1069 (vba__min_dst_y_next_start * dst->hactive) / (unsigned int) dst->pixel_rate_mhz; 1070 disp_dlg_regs->min_dst_y_next_start = vba__min_dst_y_next_start * dml_pow(2, 2); 1071 1072 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18)); 1073 1074 dml_print("DML_DLG: %s: min_ttu_vblank (us) = %3.2f\n", __func__, min_ttu_vblank); 1075 dml_print("DML_DLG: %s: min_dst_y_next_start = 0x%0x\n", __func__, disp_dlg_regs->min_dst_y_next_start); 1076 dml_print("DML_DLG: %s: dlg_vblank_start = 0x%0x\n", __func__, dlg_vblank_start); 1077 dml_print("DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n", __func__, ref_freq_to_pix_freq); 1078 dml_print("DML_DLG: %s: vba__min_dst_y_next_start = 0x%0x\n", __func__, vba__min_dst_y_next_start); 1079 1080 //old_impl_vs_vba_impl("min_dst_y_next_start", dlg_vblank_start, vba__min_dst_y_next_start); 1081 1082 // ------------------------- 1083 // Section 1.15.2.2: Prefetch, Active and TTU 1084 // ------------------------- 1085 // Prefetch Calc 1086 // Source 1087 dual_plane = is_dual_plane((enum source_format_class) (src->source_format)); 1088 access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed 1089 vp_height_l = src->viewport_height; 1090 vp_width_l = src->viewport_width; 1091 vp_height_c = src->viewport_height_c; 1092 vp_width_c = src->viewport_width_c; 1093 1094 // Scaling 1095 htaps_l = taps->htaps; 1096 htaps_c = taps->htaps_c; 1097 hratio_l = scl->hscl_ratio; 1098 hratio_c = scl->hscl_ratio_c; 1099 vratio_l = scl->vscl_ratio; 1100 vratio_c = scl->vscl_ratio_c; 1101 1102 swath_width_ub_l = rq_dlg_param->rq_l.swath_width_ub; 1103 dpte_groups_per_row_ub_l = rq_dlg_param->rq_l.dpte_groups_per_row_ub; 1104 swath_width_ub_c = rq_dlg_param->rq_c.swath_width_ub; 1105 dpte_groups_per_row_ub_c = rq_dlg_param->rq_c.dpte_groups_per_row_ub; 1106 1107 meta_chunks_per_row_ub_l = rq_dlg_param->rq_l.meta_chunks_per_row_ub; 1108 meta_chunks_per_row_ub_c = rq_dlg_param->rq_c.meta_chunks_per_row_ub; 1109 vupdate_offset = dst->vupdate_offset; 1110 vupdate_width = dst->vupdate_width; 1111 vready_offset = dst->vready_offset; 1112 1113 vstartup_start = dst->vstartup_start; 1114 if (interlaced) { 1115 if (vstartup_start / 2.0 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end / 2.0) 1116 disp_dlg_regs->vready_after_vcount0 = 1; 1117 else 1118 disp_dlg_regs->vready_after_vcount0 = 0; 1119 } else { 1120 if (vstartup_start - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end) 1121 disp_dlg_regs->vready_after_vcount0 = 1; 1122 else 1123 disp_dlg_regs->vready_after_vcount0 = 0; 1124 } 1125 1126 dml_print("DML_DLG: %s: vready_after_vcount0 = %d\n", __func__, disp_dlg_regs->vready_after_vcount0); 1127 dml_print("DML_DLG: %s: vba__vready_after_vcount0 = %d\n", __func__, vba__vready_after_vcount0); 1128 //old_impl_vs_vba_impl("vready_after_vcount0", disp_dlg_regs->vready_after_vcount0, vba__vready_after_vcount0); 1129 1130 if (interlaced) 1131 vstartup_start = vstartup_start / 2; 1132 1133 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 1134 dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 1135 1136 // do some adjustment on the dst_after scaler to account for odm combine mode 1137 dml_print("DML_DLG: %s: input dst_x_after_scaler = %d\n", __func__, dst_x_after_scaler); 1138 dml_print("DML_DLG: %s: input dst_y_after_scaler = %d\n", __func__, dst_y_after_scaler); 1139 1140 // need to figure out which side of odm combine we're in 1141 if (dst->odm_combine) { 1142 // figure out which pipes go together 1143 bool visited[DC__NUM_PIPES__MAX]; 1144 unsigned int i, j, k; 1145 1146 for (k = 0; k < num_pipes; ++k) { 1147 visited[k] = false; 1148 pipe_index_in_combine[k] = 0; 1149 } 1150 1151 for (i = 0; i < num_pipes; i++) { 1152 if (e2e_pipe_param[i].pipe.src.is_hsplit && !visited[i]) { 1153 1154 unsigned int grp = e2e_pipe_param[i].pipe.src.hsplit_grp; 1155 unsigned int grp_idx = 0; 1156 1157 for (j = i; j < num_pipes; j++) { 1158 if (e2e_pipe_param[j].pipe.src.hsplit_grp == grp && e2e_pipe_param[j].pipe.src.is_hsplit && !visited[j]) { 1159 pipe_index_in_combine[j] = grp_idx; 1160 dml_print("DML_DLG: %s: pipe[%d] is in grp %d idx %d\n", __func__, j, grp, grp_idx); 1161 grp_idx++; 1162 visited[j] = true; 1163 } 1164 } 1165 } 1166 } 1167 1168 } 1169 1170 if (dst->odm_combine == dm_odm_combine_mode_disabled) { 1171 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end * ref_freq_to_pix_freq); 1172 } else { 1173 unsigned int odm_combine_factor = (dst->odm_combine == dm_odm_combine_mode_2to1 ? 2 : 4); // TODO: We should really check that 4to1 is supported before setting it to 4 1174 unsigned int odm_pipe_index = pipe_index_in_combine[pipe_idx]; 1175 1176 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) (((double) hblank_end + odm_pipe_index * (double) dst->hactive / odm_combine_factor) * ref_freq_to_pix_freq); 1177 } ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13)); 1178 1179 dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal); 1180 dml_print("DML_DLG: %s: dst_x_after_scaler[%d] = %d\n", __func__, pipe_idx, dst_x_after_scaler); 1181 dml_print("DML_DLG: %s: dst_y_after_scaler[%d] = %d\n", __func__, pipe_idx, dst_y_after_scaler); 1182 1183 dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 1184 dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 1185 dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 1186 dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 1187 dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 1188 1189 max_dst_y_per_vm_vblank = 32.0; //U5.2 1190 max_dst_y_per_row_vblank = 16.0; //U4.2 1191 1192 // magic! 1193 if (htotal <= 75) { 1194 max_dst_y_per_vm_vblank = 100.0; 1195 max_dst_y_per_row_vblank = 100.0; 1196 } 1197 1198 dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch); 1199 dml_print("DML_DLG: %s: dst_y_per_vm_flip = %3.2f\n", __func__, dst_y_per_vm_flip); 1200 dml_print("DML_DLG: %s: dst_y_per_row_flip = %3.2f\n", __func__, dst_y_per_row_flip); 1201 dml_print("DML_DLG: %s: dst_y_per_vm_vblank = %3.2f\n", __func__, dst_y_per_vm_vblank); 1202 dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank); 1203 1204 ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank); ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank); 1205 1206 ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank)); 1207 1208 vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 1209 vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 1210 1211 dml_print("DML_DLG: %s: vratio_pre_l = %3.2f\n", __func__, vratio_pre_l); 1212 dml_print("DML_DLG: %s: vratio_pre_c = %3.2f\n", __func__, vratio_pre_c); 1213 1214 // Active 1215 req_per_swath_ub_l = rq_dlg_param->rq_l.req_per_swath_ub; 1216 req_per_swath_ub_c = rq_dlg_param->rq_c.req_per_swath_ub; 1217 meta_row_height_l = rq_dlg_param->rq_l.meta_row_height; 1218 meta_row_height_c = rq_dlg_param->rq_c.meta_row_height; 1219 swath_width_pixels_ub_l = 0; 1220 swath_width_pixels_ub_c = 0; 1221 scaler_rec_in_width_l = 0; 1222 scaler_rec_in_width_c = 0; 1223 dpte_row_height_l = rq_dlg_param->rq_l.dpte_row_height; 1224 dpte_row_height_c = rq_dlg_param->rq_c.dpte_row_height; 1225 1226 swath_width_pixels_ub_l = swath_width_ub_l; 1227 swath_width_pixels_ub_c = swath_width_ub_c; 1228 1229 if (hratio_l <= 1) 1230 min_hratio_fact_l = 2.0; 1231 else if (htaps_l <= 6) { 1232 if ((hratio_l * 2.0) > 4.0) 1233 min_hratio_fact_l = 4.0; 1234 else 1235 min_hratio_fact_l = hratio_l * 2.0; 1236 } else { 1237 if (hratio_l > 4.0) 1238 min_hratio_fact_l = 4.0; 1239 else 1240 min_hratio_fact_l = hratio_l; 1241 } 1242 1243 hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz; 1244 1245 dml_print("DML_DLG: %s: hratio_l = %3.2f\n", __func__, hratio_l); 1246 dml_print("DML_DLG: %s: min_hratio_fact_l = %3.2f\n", __func__, min_hratio_fact_l); 1247 dml_print("DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n", __func__, hscale_pixel_rate_l); 1248 1249 if (hratio_c <= 1) 1250 min_hratio_fact_c = 2.0; 1251 else if (htaps_c <= 6) { 1252 if ((hratio_c * 2.0) > 4.0) 1253 min_hratio_fact_c = 4.0; 1254 else 1255 min_hratio_fact_c = hratio_c * 2.0; 1256 } else { 1257 if (hratio_c > 4.0) 1258 min_hratio_fact_c = 4.0; 1259 else 1260 min_hratio_fact_c = hratio_c; 1261 } 1262 1263 hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz; 1264 1265 refcyc_per_line_delivery_pre_l = 0.; 1266 refcyc_per_line_delivery_pre_c = 0.; 1267 refcyc_per_line_delivery_l = 0.; 1268 refcyc_per_line_delivery_c = 0.; 1269 1270 refcyc_per_req_delivery_pre_l = 0.; 1271 refcyc_per_req_delivery_pre_c = 0.; 1272 refcyc_per_req_delivery_l = 0.; 1273 refcyc_per_req_delivery_c = 0.; 1274 1275 full_recout_width = 0; 1276 // In ODM 1277 if (src->is_hsplit) { 1278 // This "hack" is only allowed (and valid) for MPC combine. In ODM 1279 // combine, you MUST specify the full_recout_width...according to Oswin 1280 if (dst->full_recout_width == 0 && !dst->odm_combine) { 1281 dml_print("DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n", __func__); 1282 full_recout_width = dst->recout_width * 2; // assume half split for dcn1 1283 } else 1284 full_recout_width = dst->full_recout_width; 1285 } else 1286 full_recout_width = dst->recout_width; 1287 1288 // As of DCN2, mpc_combine and odm_combine are mutually exclusive 1289 refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery( 1290 mode_lib, 1291 refclk_freq_in_mhz, 1292 pclk_freq_in_mhz, 1293 dst->odm_combine, 1294 full_recout_width, 1295 dst->hactive, 1296 vratio_pre_l, 1297 hscale_pixel_rate_l, 1298 swath_width_pixels_ub_l, 1299 1); // per line 1300 1301 refcyc_per_line_delivery_l = get_refcyc_per_delivery( 1302 mode_lib, 1303 refclk_freq_in_mhz, 1304 pclk_freq_in_mhz, 1305 dst->odm_combine, 1306 full_recout_width, 1307 dst->hactive, 1308 vratio_l, 1309 hscale_pixel_rate_l, 1310 swath_width_pixels_ub_l, 1311 1); // per line 1312 1313 dml_print("DML_DLG: %s: full_recout_width = %d\n", __func__, full_recout_width); 1314 dml_print("DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n", __func__, hscale_pixel_rate_l); 1315 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n", __func__, refcyc_per_line_delivery_pre_l); 1316 dml_print("DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f\n", __func__, refcyc_per_line_delivery_l); 1317 dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_pre_l = %3.2f\n", __func__, vba__refcyc_per_line_delivery_pre_l); 1318 dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_l = %3.2f\n", __func__, vba__refcyc_per_line_delivery_l); 1319 1320 //old_impl_vs_vba_impl("refcyc_per_line_delivery_pre_l", refcyc_per_line_delivery_pre_l, vba__refcyc_per_line_delivery_pre_l); 1321 //old_impl_vs_vba_impl("refcyc_per_line_delivery_l", refcyc_per_line_delivery_l, vba__refcyc_per_line_delivery_l); 1322 1323 if (dual_plane) { 1324 float vba__refcyc_per_line_delivery_pre_c = get_refcyc_per_line_delivery_pre_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 1325 float vba__refcyc_per_line_delivery_c = get_refcyc_per_line_delivery_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 1326 1327 refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery( 1328 mode_lib, 1329 refclk_freq_in_mhz, 1330 pclk_freq_in_mhz, 1331 dst->odm_combine, 1332 full_recout_width, 1333 dst->hactive, 1334 vratio_pre_c, 1335 hscale_pixel_rate_c, 1336 swath_width_pixels_ub_c, 1337 1); // per line 1338 1339 refcyc_per_line_delivery_c = get_refcyc_per_delivery( 1340 mode_lib, 1341 refclk_freq_in_mhz, 1342 pclk_freq_in_mhz, 1343 dst->odm_combine, 1344 full_recout_width, 1345 dst->hactive, 1346 vratio_c, 1347 hscale_pixel_rate_c, 1348 swath_width_pixels_ub_c, 1349 1); // per line 1350 1351 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n", __func__, refcyc_per_line_delivery_pre_c); 1352 dml_print("DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f\n", __func__, refcyc_per_line_delivery_c); 1353 dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_pre_c = %3.2f\n", __func__, vba__refcyc_per_line_delivery_pre_c); 1354 dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_c = %3.2f\n", __func__, vba__refcyc_per_line_delivery_c); 1355 1356 //old_impl_vs_vba_impl("refcyc_per_line_delivery_pre_c", refcyc_per_line_delivery_pre_c, vba__refcyc_per_line_delivery_pre_c); 1357 //old_impl_vs_vba_impl("refcyc_per_line_delivery_c", refcyc_per_line_delivery_c, vba__refcyc_per_line_delivery_c); 1358 } 1359 1360 if (src->dynamic_metadata_enable && src->gpuvm) 1361 disp_dlg_regs->refcyc_per_vm_dmdata = get_refcyc_per_vm_dmdata_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 1362 1363 disp_dlg_regs->dmdata_dl_delta = get_dmdata_dl_delta_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 1364 1365 // TTU - Luma / Chroma 1366 if (access_dir) { // vertical access 1367 scaler_rec_in_width_l = vp_height_l; 1368 scaler_rec_in_width_c = vp_height_c; 1369 } else { 1370 scaler_rec_in_width_l = vp_width_l; 1371 scaler_rec_in_width_c = vp_width_c; 1372 } 1373 1374 refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery( 1375 mode_lib, 1376 refclk_freq_in_mhz, 1377 pclk_freq_in_mhz, 1378 dst->odm_combine, 1379 full_recout_width, 1380 dst->hactive, 1381 vratio_pre_l, 1382 hscale_pixel_rate_l, 1383 scaler_rec_in_width_l, 1384 req_per_swath_ub_l); // per req 1385 1386 refcyc_per_req_delivery_l = get_refcyc_per_delivery( 1387 mode_lib, 1388 refclk_freq_in_mhz, 1389 pclk_freq_in_mhz, 1390 dst->odm_combine, 1391 full_recout_width, 1392 dst->hactive, 1393 vratio_l, 1394 hscale_pixel_rate_l, 1395 scaler_rec_in_width_l, 1396 req_per_swath_ub_l); // per req 1397 1398 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n", __func__, refcyc_per_req_delivery_pre_l); 1399 dml_print("DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f\n", __func__, refcyc_per_req_delivery_l); 1400 dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_pre_l = %3.2f\n", __func__, vba__refcyc_per_req_delivery_pre_l); 1401 dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_l = %3.2f\n", __func__, vba__refcyc_per_req_delivery_l); 1402 1403 //old_impl_vs_vba_impl("refcyc_per_req_delivery_pre_l", refcyc_per_req_delivery_pre_l, vba__refcyc_per_req_delivery_pre_l); 1404 //old_impl_vs_vba_impl("refcyc_per_req_delivery_l", refcyc_per_req_delivery_l, vba__refcyc_per_req_delivery_l); 1405 1406 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); 1407 1408 if (dual_plane) { 1409 float vba__refcyc_per_req_delivery_pre_c = get_refcyc_per_req_delivery_pre_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 1410 float vba__refcyc_per_req_delivery_c = get_refcyc_per_req_delivery_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 1411 1412 refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery( 1413 mode_lib, 1414 refclk_freq_in_mhz, 1415 pclk_freq_in_mhz, 1416 dst->odm_combine, 1417 full_recout_width, 1418 dst->hactive, 1419 vratio_pre_c, 1420 hscale_pixel_rate_c, 1421 scaler_rec_in_width_c, 1422 req_per_swath_ub_c); // per req 1423 refcyc_per_req_delivery_c = get_refcyc_per_delivery( 1424 mode_lib, 1425 refclk_freq_in_mhz, 1426 pclk_freq_in_mhz, 1427 dst->odm_combine, 1428 full_recout_width, 1429 dst->hactive, 1430 vratio_c, 1431 hscale_pixel_rate_c, 1432 scaler_rec_in_width_c, 1433 req_per_swath_ub_c); // per req 1434 1435 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n", __func__, refcyc_per_req_delivery_pre_c); 1436 dml_print("DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f\n", __func__, refcyc_per_req_delivery_c); 1437 dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_pre_c = %3.2f\n", __func__, vba__refcyc_per_req_delivery_pre_c); 1438 dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_c = %3.2f\n", __func__, vba__refcyc_per_req_delivery_c); 1439 1440 //old_impl_vs_vba_impl("refcyc_per_req_delivery_pre_c", refcyc_per_req_delivery_pre_c, vba__refcyc_per_req_delivery_pre_c); 1441 //old_impl_vs_vba_impl("refcyc_per_req_delivery_c", refcyc_per_req_delivery_c, vba__refcyc_per_req_delivery_c); 1442 1443 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); 1444 } 1445 1446 // TTU - Cursor 1447 refcyc_per_req_delivery_pre_cur0 = 0.0; 1448 refcyc_per_req_delivery_cur0 = 0.0; 1449 1450 ASSERT(src->num_cursors <= 1); 1451 1452 if (src->num_cursors > 0) { 1453 float vba__refcyc_per_req_delivery_pre_cur0; 1454 float vba__refcyc_per_req_delivery_cur0; 1455 1456 calculate_ttu_cursor( 1457 mode_lib, 1458 &refcyc_per_req_delivery_pre_cur0, 1459 &refcyc_per_req_delivery_cur0, 1460 refclk_freq_in_mhz, 1461 ref_freq_to_pix_freq, 1462 hscale_pixel_rate_l, 1463 scl->hscl_ratio, 1464 vratio_pre_l, 1465 vratio_l, 1466 src->cur0_src_width, 1467 (enum cursor_bpp) (src->cur0_bpp)); 1468 1469 vba__refcyc_per_req_delivery_pre_cur0 = get_refcyc_per_cursor_req_delivery_pre_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 1470 vba__refcyc_per_req_delivery_cur0 = get_refcyc_per_cursor_req_delivery_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 1471 1472 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur0 = %3.2f\n", __func__, refcyc_per_req_delivery_pre_cur0); 1473 dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur0 = %3.2f\n", __func__, refcyc_per_req_delivery_cur0); 1474 dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_pre_cur0 = %3.2f\n", __func__, vba__refcyc_per_req_delivery_pre_cur0); 1475 dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_cur0 = %3.2f\n", __func__, vba__refcyc_per_req_delivery_cur0); 1476 1477 //old_impl_vs_vba_impl("refcyc_per_req_delivery_pre_cur0", refcyc_per_req_delivery_pre_cur0, vba__refcyc_per_req_delivery_pre_cur0); 1478 //old_impl_vs_vba_impl("refcyc_per_req_delivery_cur0", refcyc_per_req_delivery_cur0, vba__refcyc_per_req_delivery_cur0); 1479 } 1480 1481 refcyc_per_req_delivery_pre_cur1 = 0.0; 1482 refcyc_per_req_delivery_cur1 = 0.0; 1483 1484 // TTU - Misc 1485 // all hard-coded 1486 1487 // Assignment to register structures 1488 disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line 1489 ASSERT(disp_dlg_regs->dst_y_after_scaler < 8); 1490 disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk 1491 ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13)); 1492 disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); 1493 disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); 1494 disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); 1495 disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); 1496 disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2)); 1497 1498 disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); 1499 disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); 1500 1501 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_vblank); 1502 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_vblank); 1503 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_flip); 1504 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_flip); 1505 1506 disp_dlg_regs->refcyc_per_pte_group_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); 1507 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13)); 1508 1509 if (dual_plane) { 1510 disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_c); 1511 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13)); 1512 } 1513 1514 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); 1515 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); 1516 1517 disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now 1518 1519 disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l; 1520 disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l; 1521 1522 if (dual_plane) { 1523 disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c; 1524 disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; 1525 } 1526 1527 disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 1528 disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 1529 disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA 1530 disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA 1531 1532 // Clamp to max for now 1533 if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int) dml_pow(2, 23)) 1534 disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1; 1535 1536 if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int) dml_pow(2, 23)) 1537 disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1; 1538 1539 if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int) dml_pow(2, 23)) 1540 disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1; 1541 1542 if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int) dml_pow(2, 23)) 1543 disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; 1544 1545 disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * dml_pow(2, 2)); 1546 ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17)); 1547 if (dual_plane) { 1548 disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c / (double) vratio_c * dml_pow(2, 2)); 1549 if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) { 1550 dml_print( 1551 "DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n", 1552 __func__, 1553 disp_dlg_regs->dst_y_per_pte_row_nom_c, 1554 (unsigned int) dml_pow(2, 17) - 1); 1555 } 1556 } 1557 1558 disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * dml_pow(2, 2)); 1559 ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17)); 1560 1561 disp_dlg_regs->dst_y_per_meta_row_nom_c = (unsigned int) ((double) meta_row_height_c / (double) vratio_c * dml_pow(2, 2)); 1562 ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_c < (unsigned int)dml_pow(2, 17)); 1563 1564 disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq 1565 / (double) dpte_groups_per_row_ub_l); 1566 if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) 1567 disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; 1568 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq 1569 / (double) meta_chunks_per_row_ub_l); 1570 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) 1571 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; 1572 1573 if (dual_plane) { 1574 disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int) ((double) dpte_row_height_c / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq 1575 / (double) dpte_groups_per_row_ub_c); 1576 if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) 1577 disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; 1578 1579 // TODO: Is this the right calculation? Does htotal need to be halved? 1580 disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int) ((double) meta_row_height_c / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq 1581 / (double) meta_chunks_per_row_ub_c); 1582 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) 1583 disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; 1584 } 1585 1586 disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, 1); 1587 disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l, 1); 1588 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13)); 1589 1590 disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c, 1); 1591 disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c, 1); 1592 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13)); 1593 1594 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; 1595 disp_dlg_regs->dst_y_offset_cur0 = 0; 1596 disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; 1597 disp_dlg_regs->dst_y_offset_cur1 = 0; 1598 1599 disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off 1600 1601 disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l * dml_pow(2, 10)); 1602 disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l * dml_pow(2, 10)); 1603 disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10)); 1604 disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c * dml_pow(2, 10)); 1605 disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); 1606 disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10)); 1607 disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); 1608 disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 * dml_pow(2, 10)); 1609 1610 disp_ttu_regs->qos_level_low_wm = 0; 1611 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); 1612 1613 disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal * ref_freq_to_pix_freq); 1614 ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14)); 1615 1616 disp_ttu_regs->qos_level_flip = 14; 1617 disp_ttu_regs->qos_level_fixed_l = 8; 1618 disp_ttu_regs->qos_level_fixed_c = 8; 1619 disp_ttu_regs->qos_level_fixed_cur0 = 8; 1620 disp_ttu_regs->qos_ramp_disable_l = 0; 1621 disp_ttu_regs->qos_ramp_disable_c = 0; 1622 disp_ttu_regs->qos_ramp_disable_cur0 = 0; 1623 1624 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; 1625 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); 1626 1627 print__ttu_regs_st(mode_lib, disp_ttu_regs); 1628 print__dlg_regs_st(mode_lib, disp_dlg_regs); 1629} 1630 1631void dml314_rq_dlg_get_dlg_reg( 1632 struct display_mode_lib *mode_lib, 1633 display_dlg_regs_st *dlg_regs, 1634 display_ttu_regs_st *ttu_regs, 1635 const display_e2e_pipe_params_st *e2e_pipe_param, 1636 const unsigned int num_pipes, 1637 const unsigned int pipe_idx, 1638 const bool cstate_en, 1639 const bool pstate_en, 1640 const bool vm_en, 1641 const bool ignore_viewport_pos, 1642 const bool immediate_flip_support) 1643{ 1644 display_rq_params_st rq_param = {0}; 1645 display_dlg_sys_params_st dlg_sys_param = {0}; 1646 1647 // Get watermark and Tex. 1648 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); 1649 dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib, e2e_pipe_param, num_pipes); 1650 dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes); 1651 dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes); 1652 dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes); 1653 dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes); 1654 dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, e2e_pipe_param, num_pipes); 1655 dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, e2e_pipe_param, num_pipes); 1656 1657 print__dlg_sys_params_st(mode_lib, &dlg_sys_param); 1658 1659 // system parameter calculation done 1660 1661 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); 1662 dml_rq_dlg_get_rq_params(mode_lib, &rq_param, &e2e_pipe_param[pipe_idx].pipe); 1663 dml_rq_dlg_get_dlg_params( 1664 mode_lib, 1665 e2e_pipe_param, 1666 num_pipes, 1667 pipe_idx, 1668 dlg_regs, 1669 ttu_regs, 1670 &rq_param.dlg, 1671 &dlg_sys_param, 1672 cstate_en, 1673 pstate_en, 1674 vm_en, 1675 ignore_viewport_pos, 1676 immediate_flip_support); 1677 dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx); 1678}
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