dcn301_fpu.c

  1/*
  2 * Copyright 2019-2021 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25#include "resource.h"
 26#include "clk_mgr.h"
 27#include "dcn20/dcn20_resource.h"
 28#include "dcn301/dcn301_resource.h"
 29#include "clk_mgr/dcn301/vg_clk_mgr.h"
 30
 31#include "dml/dcn20/dcn20_fpu.h"
 32#include "dcn301_fpu.h"
 33
 34#define TO_DCN301_RES_POOL(pool)\
 35	container_of(pool, struct dcn301_resource_pool, base)
 36
 37/* Based on: //vidip/dc/dcn3/doc/architecture/DCN3x_Display_Mode.xlsm#83 */
 38struct _vcs_dpi_ip_params_st dcn3_01_ip = {
 39	.odm_capable = 1,
 40	.gpuvm_enable = 1,
 41	.hostvm_enable = 1,
 42	.gpuvm_max_page_table_levels = 1,
 43	.hostvm_max_page_table_levels = 2,
 44	.hostvm_cached_page_table_levels = 0,
 45	.pte_group_size_bytes = 2048,
 46	.num_dsc = 3,
 47	.rob_buffer_size_kbytes = 184,
 48	.det_buffer_size_kbytes = 184,
 49	.dpte_buffer_size_in_pte_reqs_luma = 64,
 50	.dpte_buffer_size_in_pte_reqs_chroma = 32,
 51	.pde_proc_buffer_size_64k_reqs = 48,
 52	.dpp_output_buffer_pixels = 2560,
 53	.opp_output_buffer_lines = 1,
 54	.pixel_chunk_size_kbytes = 8,
 55	.meta_chunk_size_kbytes = 2,
 56	.writeback_chunk_size_kbytes = 8,
 57	.line_buffer_size_bits = 789504,
 58	.is_line_buffer_bpp_fixed = 0,  // ?
 59	.line_buffer_fixed_bpp = 48,     // ?
 60	.dcc_supported = true,
 61	.writeback_interface_buffer_size_kbytes = 90,
 62	.writeback_line_buffer_buffer_size = 656640,
 63	.max_line_buffer_lines = 12,
 64	.writeback_luma_buffer_size_kbytes = 12,  // writeback_line_buffer_buffer_size = 656640
 65	.writeback_chroma_buffer_size_kbytes = 8,
 66	.writeback_chroma_line_buffer_width_pixels = 4,
 67	.writeback_max_hscl_ratio = 1,
 68	.writeback_max_vscl_ratio = 1,
 69	.writeback_min_hscl_ratio = 1,
 70	.writeback_min_vscl_ratio = 1,
 71	.writeback_max_hscl_taps = 1,
 72	.writeback_max_vscl_taps = 1,
 73	.writeback_line_buffer_luma_buffer_size = 0,
 74	.writeback_line_buffer_chroma_buffer_size = 14643,
 75	.cursor_buffer_size = 8,
 76	.cursor_chunk_size = 2,
 77	.max_num_otg = 4,
 78	.max_num_dpp = 4,
 79	.max_num_wb = 1,
 80	.max_dchub_pscl_bw_pix_per_clk = 4,
 81	.max_pscl_lb_bw_pix_per_clk = 2,
 82	.max_lb_vscl_bw_pix_per_clk = 4,
 83	.max_vscl_hscl_bw_pix_per_clk = 4,
 84	.max_hscl_ratio = 6,
 85	.max_vscl_ratio = 6,
 86	.hscl_mults = 4,
 87	.vscl_mults = 4,
 88	.max_hscl_taps = 8,
 89	.max_vscl_taps = 8,
 90	.dispclk_ramp_margin_percent = 1,
 91	.underscan_factor = 1.11,
 92	.min_vblank_lines = 32,
 93	.dppclk_delay_subtotal = 46,
 94	.dynamic_metadata_vm_enabled = true,
 95	.dppclk_delay_scl_lb_only = 16,
 96	.dppclk_delay_scl = 50,
 97	.dppclk_delay_cnvc_formatter = 27,
 98	.dppclk_delay_cnvc_cursor = 6,
 99	.dispclk_delay_subtotal = 119,
100	.dcfclk_cstate_latency = 5.2, // SRExitTime
101	.max_inter_dcn_tile_repeaters = 8,
102	.max_num_hdmi_frl_outputs = 0,
103	.odm_combine_4to1_supported = true,
104
105	.xfc_supported = false,
106	.xfc_fill_bw_overhead_percent = 10.0,
107	.xfc_fill_constant_bytes = 0,
108	.gfx7_compat_tiling_supported = 0,
109	.number_of_cursors = 1,
110};
111
112struct _vcs_dpi_soc_bounding_box_st dcn3_01_soc = {
113	.clock_limits = {
114		{
115			.state = 0,
116			.dram_speed_mts = 2400.0,
117			.fabricclk_mhz = 600,
118			.socclk_mhz = 278.0,
119			.dcfclk_mhz = 400.0,
120			.dscclk_mhz = 206.0,
121			.dppclk_mhz = 1015.0,
122			.dispclk_mhz = 1015.0,
123			.phyclk_mhz = 600.0,
124		},
125
126		{
127			.state = 1,
128			.dram_speed_mts = 2400.0,
129			.fabricclk_mhz = 688,
130			.socclk_mhz = 278.0,
131			.dcfclk_mhz = 400.0,
132			.dscclk_mhz = 206.0,
133			.dppclk_mhz = 1015.0,
134			.dispclk_mhz = 1015.0,
135			.phyclk_mhz = 600.0,
136		},
137
138		{
139			.state = 2,
140			.dram_speed_mts = 4267.0,
141			.fabricclk_mhz = 1067,
142			.socclk_mhz = 278.0,
143			.dcfclk_mhz = 608.0,
144			.dscclk_mhz = 296.0,
145			.dppclk_mhz = 1015.0,
146			.dispclk_mhz = 1015.0,
147			.phyclk_mhz = 810.0,
148		},
149
150		{
151			.state = 3,
152			.dram_speed_mts = 4267.0,
153			.fabricclk_mhz = 1067,
154			.socclk_mhz = 715.0,
155			.dcfclk_mhz = 676.0,
156			.dscclk_mhz = 338.0,
157			.dppclk_mhz = 1015.0,
158			.dispclk_mhz = 1015.0,
159			.phyclk_mhz = 810.0,
160		},
161
162		{
163			.state = 4,
164			.dram_speed_mts = 4267.0,
165			.fabricclk_mhz = 1067,
166			.socclk_mhz = 953.0,
167			.dcfclk_mhz = 810.0,
168			.dscclk_mhz = 338.0,
169			.dppclk_mhz = 1015.0,
170			.dispclk_mhz = 1015.0,
171			.phyclk_mhz = 810.0,
172		},
173	},
174
175	.sr_exit_time_us = 9.0,
176	.sr_enter_plus_exit_time_us = 11.0,
177	.urgent_latency_us = 4.0,
178	.urgent_latency_pixel_data_only_us = 4.0,
179	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
180	.urgent_latency_vm_data_only_us = 4.0,
181	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
182	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
183	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
184	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
185	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
186	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
187	.max_avg_sdp_bw_use_normal_percent = 60.0,
188	.max_avg_dram_bw_use_normal_percent = 60.0,
189	.writeback_latency_us = 12.0,
190	.max_request_size_bytes = 256,
191	.dram_channel_width_bytes = 4,
192	.fabric_datapath_to_dcn_data_return_bytes = 32,
193	.dcn_downspread_percent = 0.5,
194	.downspread_percent = 0.38,
195	.dram_page_open_time_ns = 50.0,
196	.dram_rw_turnaround_time_ns = 17.5,
197	.dram_return_buffer_per_channel_bytes = 8192,
198	.round_trip_ping_latency_dcfclk_cycles = 191,
199	.urgent_out_of_order_return_per_channel_bytes = 4096,
200	.channel_interleave_bytes = 256,
201	.num_banks = 8,
202	.num_chans = 4,
203	.gpuvm_min_page_size_bytes = 4096,
204	.hostvm_min_page_size_bytes = 4096,
205	.dram_clock_change_latency_us = 23.84,
206	.writeback_dram_clock_change_latency_us = 23.0,
207	.return_bus_width_bytes = 64,
208	.dispclk_dppclk_vco_speed_mhz = 3550,
209	.xfc_bus_transport_time_us = 20,      // ?
210	.xfc_xbuf_latency_tolerance_us = 4,  // ?
211	.use_urgent_burst_bw = 1,            // ?
212	.num_states = 5,
213	.do_urgent_latency_adjustment = false,
214	.urgent_latency_adjustment_fabric_clock_component_us = 0,
215	.urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
216};
217
218struct wm_table ddr4_wm_table = {
219	.entries = {
220		{
221			.wm_inst = WM_A,
222			.wm_type = WM_TYPE_PSTATE_CHG,
223			.pstate_latency_us = 11.72,
224			.sr_exit_time_us = 6.09,
225			.sr_enter_plus_exit_time_us = 7.14,
226			.valid = true,
227		},
228		{
229			.wm_inst = WM_B,
230			.wm_type = WM_TYPE_PSTATE_CHG,
231			.pstate_latency_us = 11.72,
232			.sr_exit_time_us = 10.12,
233			.sr_enter_plus_exit_time_us = 11.48,
234			.valid = true,
235		},
236		{
237			.wm_inst = WM_C,
238			.wm_type = WM_TYPE_PSTATE_CHG,
239			.pstate_latency_us = 11.72,
240			.sr_exit_time_us = 10.12,
241			.sr_enter_plus_exit_time_us = 11.48,
242			.valid = true,
243		},
244		{
245			.wm_inst = WM_D,
246			.wm_type = WM_TYPE_PSTATE_CHG,
247			.pstate_latency_us = 11.72,
248			.sr_exit_time_us = 10.12,
249			.sr_enter_plus_exit_time_us = 11.48,
250			.valid = true,
251		},
252	}
253};
254
255struct wm_table lpddr5_wm_table = {
256	.entries = {
257		{
258			.wm_inst = WM_A,
259			.wm_type = WM_TYPE_PSTATE_CHG,
260			.pstate_latency_us = 11.65333,
261			.sr_exit_time_us = 13.5,
262			.sr_enter_plus_exit_time_us = 16.5,
263			.valid = true,
264		},
265		{
266			.wm_inst = WM_B,
267			.wm_type = WM_TYPE_PSTATE_CHG,
268			.pstate_latency_us = 11.65333,
269			.sr_exit_time_us = 13.5,
270			.sr_enter_plus_exit_time_us = 16.5,
271			.valid = true,
272		},
273		{
274			.wm_inst = WM_C,
275			.wm_type = WM_TYPE_PSTATE_CHG,
276			.pstate_latency_us = 11.65333,
277			.sr_exit_time_us = 13.5,
278			.sr_enter_plus_exit_time_us = 16.5,
279			.valid = true,
280		},
281		{
282			.wm_inst = WM_D,
283			.wm_type = WM_TYPE_PSTATE_CHG,
284			.pstate_latency_us = 11.65333,
285			.sr_exit_time_us = 13.5,
286			.sr_enter_plus_exit_time_us = 16.5,
287			.valid = true,
288		},
289	}
290};
291
292static void calculate_wm_set_for_vlevel(int vlevel,
293		struct wm_range_table_entry *table_entry,
294		struct dcn_watermarks *wm_set,
295		struct display_mode_lib *dml,
296		display_e2e_pipe_params_st *pipes,
297		int pipe_cnt)
298{
299	double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
300
301	ASSERT(vlevel < dml->soc.num_states);
302	/* only pipe 0 is read for voltage and dcf/soc clocks */
303	pipes[0].clks_cfg.voltage = vlevel;
304	pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
305	pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
306
307	dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
308	dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
309	dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
310
311	wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
312	wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
313	wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
314	wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
315	wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
316	wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
317	wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
318	wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
319	dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
320
321}
322
323void dcn301_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
324{
325	struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;
326	struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool);
327	struct clk_limit_table *clk_table = &bw_params->clk_table;
328	unsigned int i, closest_clk_lvl;
329	int j = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0;
330
331	dc_assert_fp_enabled();
332
333	memcpy(s, dcn3_01_soc.clock_limits, sizeof(dcn3_01_soc.clock_limits));
334
335	/* Default clock levels are used for diags, which may lead to overclocking. */
336	dcn3_01_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
337	dcn3_01_ip.max_num_dpp = pool->base.pipe_count;
338	dcn3_01_soc.num_chans = bw_params->num_channels;
339
340	ASSERT(clk_table->num_entries);
341
342	/* Prepass to find max clocks independent of voltage level. */
343	for (i = 0; i < clk_table->num_entries; ++i) {
344		if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
345			max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
346		if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
347			max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
348	}
349
350	for (i = 0; i < clk_table->num_entries; i++) {
351		/* loop backwards*/
352		for (closest_clk_lvl = 0, j = dcn3_01_soc.num_states - 1; j >= 0; j--) {
353			if ((unsigned int) dcn3_01_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
354				closest_clk_lvl = j;
355				break;
356			}
357		}
358
359		s[i].state = i;
360		s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
361		s[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
362		s[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
363		s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
364
365		/* Clocks independent of voltage level. */
366		s[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
367			dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
368
369		s[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
370			dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
371
372		s[i].dram_bw_per_chan_gbps =
373			dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
374		s[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
375		s[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
376		s[i].phyclk_d18_mhz =
377			dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
378		s[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
379	}
380
381	if (clk_table->num_entries) {
382		dcn3_01_soc.num_states = clk_table->num_entries;
383		/* duplicate last level */
384		s[dcn3_01_soc.num_states] =
385			dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1];
386		s[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states;
387	}
388
389	memcpy(dcn3_01_soc.clock_limits, s, sizeof(dcn3_01_soc.clock_limits));
390
391	dcn3_01_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
392	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
393
394	if ((int)(dcn3_01_soc.dram_clock_change_latency_us * 1000)
395				!= dc->debug.dram_clock_change_latency_ns
396			&& dc->debug.dram_clock_change_latency_ns) {
397		dcn3_01_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000.0;
398	}
399	dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);
400}
401
402void dcn301_fpu_set_wm_ranges(int i,
403	struct pp_smu_wm_range_sets *ranges,
404	struct _vcs_dpi_soc_bounding_box_st *loaded_bb)
405{
406	dc_assert_fp_enabled();
407
408	ranges->reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
409	ranges->reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
410}
411
412void dcn301_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info)
413{
414	dc_assert_fp_enabled();
415
416	if (bb_info.dram_clock_change_latency_100ns > 0)
417		dcn3_01_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
418
419	if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
420		dcn3_01_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
421
422	if (bb_info.dram_sr_exit_latency_100ns > 0)
423		dcn3_01_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
424}
425
426void dcn301_fpu_calculate_wm_and_dlg(struct dc *dc,
427		struct dc_state *context,
428		display_e2e_pipe_params_st *pipes,
429		int pipe_cnt,
430		int vlevel_req)
431{
432	int i, pipe_idx;
433	int vlevel, vlevel_max;
434	struct wm_range_table_entry *table_entry;
435	struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
436
437	ASSERT(bw_params);
438	dc_assert_fp_enabled();
439
440	vlevel_max = bw_params->clk_table.num_entries - 1;
441
442	/* WM Set D */
443	table_entry = &bw_params->wm_table.entries[WM_D];
444	if (table_entry->wm_type == WM_TYPE_RETRAINING)
445		vlevel = 0;
446	else
447		vlevel = vlevel_max;
448	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
449						&context->bw_ctx.dml, pipes, pipe_cnt);
450	/* WM Set C */
451	table_entry = &bw_params->wm_table.entries[WM_C];
452	vlevel = clamp(vlevel_req, 2, vlevel_max);
453	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
454						&context->bw_ctx.dml, pipes, pipe_cnt);
455	/* WM Set B */
456	table_entry = &bw_params->wm_table.entries[WM_B];
457	vlevel = clamp(vlevel_req, 1, vlevel_max);
458	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
459						&context->bw_ctx.dml, pipes, pipe_cnt);
460
461	/* WM Set A */
462	table_entry = &bw_params->wm_table.entries[WM_A];
463	vlevel = min(vlevel_req, vlevel_max);
464	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
465						&context->bw_ctx.dml, pipes, pipe_cnt);
466
467	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
468		if (!context->res_ctx.pipe_ctx[i].stream)
469			continue;
470
471		pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
472		pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
473
474		if (dc->config.forced_clocks) {
475			pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
476			pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
477		}
478		if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
479			pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
480		if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
481			pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
482		pipe_idx++;
483	}
484
485	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
486}