dcn30_fpu.h

 1/*
 2 * Copyright 2020-2021 Advanced Micro Devices, Inc.
 3 *
 4 * Permission is hereby granted, free of charge, to any person obtaining a
 5 * copy of this software and associated documentation files (the "Software"),
 6 * to deal in the Software without restriction, including without limitation
 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 8 * and/or sell copies of the Software, and to permit persons to whom the
 9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DCN30_FPU_H__
27#define __DCN30_FPU_H__
28
29#include "core_types.h"
30#include "dcn20/dcn20_optc.h"
31
32void dcn30_fpu_populate_dml_writeback_from_context(
33		struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
34
35void dcn30_fpu_set_mcif_arb_params(struct mcif_arb_params *wb_arb_params,
36	struct display_mode_lib *dml,
37	display_e2e_pipe_params_st *pipes,
38	int pipe_cnt,
39	int cur_pipe);
40
41void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
42
43void dcn30_fpu_calculate_wm_and_dlg(
44		struct dc *dc, struct dc_state *context,
45		display_e2e_pipe_params_st *pipes,
46		int pipe_cnt,
47		int vlevel);
48
49void dcn30_fpu_update_dram_channel_width_bytes(struct dc *dc);
50
51void dcn30_fpu_update_max_clk(struct dc_bounding_box_max_clk *dcn30_bb_max_clk);
52
53void dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
54		unsigned int *optimal_dcfclk,
55		unsigned int *optimal_fclk);
56
57void dcn30_fpu_update_bw_bounding_box(struct dc *dc,
58	struct clk_bw_params *bw_params,
59	struct dc_bounding_box_max_clk *dcn30_bb_max_clk,
60	unsigned int *dcfclk_mhz,
61	unsigned int *dram_speed_mts);
62
63int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,
64							    struct dc_state *context,
65							    display_e2e_pipe_params_st *pipes,
66							    int pipe_cnt,
67							    int vlevel);
68
69void dcn3_fpu_build_wm_range_table(struct clk_mgr *base);
70
71void patch_dcn30_soc_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *dcn3_0_ip);
72
73#endif /* __DCN30_FPU_H__*/