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dcn30_fpu.c
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linux-6.19.14/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
1/* 2 * Copyright 2020-2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25#include "resource.h" 26#include "clk_mgr.h" 27#include "reg_helper.h" 28#include "dcn_calc_math.h" 29#include "dcn20/dcn20_resource.h" 30#include "dcn30/dcn30_resource.h" 31 32#include "clk_mgr/dcn30/dcn30_smu11_driver_if.h" 33#include "display_mode_vba_30.h" 34#include "dcn30_fpu.h" 35 36#define REG(reg)\ 37 optc1->tg_regs->reg 38 39#define CTX \ 40 optc1->base.ctx 41 42#undef FN 43#define FN(reg_name, field_name) \ 44 optc1->tg_shift->field_name, optc1->tg_mask->field_name 45 46 47struct _vcs_dpi_ip_params_st dcn3_0_ip = { 48 .use_min_dcfclk = 0, 49 .clamp_min_dcfclk = 0, 50 .odm_capable = 1, 51 .gpuvm_enable = 0, 52 .hostvm_enable = 0, 53 .gpuvm_max_page_table_levels = 4, 54 .hostvm_max_page_table_levels = 4, 55 .hostvm_cached_page_table_levels = 0, 56 .pte_group_size_bytes = 2048, 57 .num_dsc = 6, 58 .rob_buffer_size_kbytes = 184, 59 .det_buffer_size_kbytes = 184, 60 .dpte_buffer_size_in_pte_reqs_luma = 84, 61 .pde_proc_buffer_size_64k_reqs = 48, 62 .dpp_output_buffer_pixels = 2560, 63 .opp_output_buffer_lines = 1, 64 .pixel_chunk_size_kbytes = 8, 65 .pte_enable = 1, 66 .max_page_table_levels = 2, 67 .pte_chunk_size_kbytes = 2, // ? 68 .meta_chunk_size_kbytes = 2, 69 .writeback_chunk_size_kbytes = 8, 70 .line_buffer_size_bits = 789504, 71 .is_line_buffer_bpp_fixed = 0, // ? 72 .line_buffer_fixed_bpp = 0, // ? 73 .dcc_supported = true, 74 .writeback_interface_buffer_size_kbytes = 90, 75 .writeback_line_buffer_buffer_size = 0, 76 .max_line_buffer_lines = 12, 77 .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 656640 78 .writeback_chroma_buffer_size_kbytes = 8, 79 .writeback_chroma_line_buffer_width_pixels = 4, 80 .writeback_max_hscl_ratio = 1, 81 .writeback_max_vscl_ratio = 1, 82 .writeback_min_hscl_ratio = 1, 83 .writeback_min_vscl_ratio = 1, 84 .writeback_max_hscl_taps = 1, 85 .writeback_max_vscl_taps = 1, 86 .writeback_line_buffer_luma_buffer_size = 0, 87 .writeback_line_buffer_chroma_buffer_size = 14643, 88 .cursor_buffer_size = 8, 89 .cursor_chunk_size = 2, 90 .max_num_otg = 6, 91 .max_num_dpp = 6, 92 .max_num_wb = 1, 93 .max_dchub_pscl_bw_pix_per_clk = 4, 94 .max_pscl_lb_bw_pix_per_clk = 2, 95 .max_lb_vscl_bw_pix_per_clk = 4, 96 .max_vscl_hscl_bw_pix_per_clk = 4, 97 .max_hscl_ratio = 6, 98 .max_vscl_ratio = 6, 99 .hscl_mults = 4, 100 .vscl_mults = 4, 101 .max_hscl_taps = 8, 102 .max_vscl_taps = 8, 103 .dispclk_ramp_margin_percent = 1, 104 .underscan_factor = 1.11, 105 .min_vblank_lines = 32, 106 .dppclk_delay_subtotal = 46, 107 .dynamic_metadata_vm_enabled = true, 108 .dppclk_delay_scl_lb_only = 16, 109 .dppclk_delay_scl = 50, 110 .dppclk_delay_cnvc_formatter = 27, 111 .dppclk_delay_cnvc_cursor = 6, 112 .dispclk_delay_subtotal = 119, 113 .dcfclk_cstate_latency = 5.2, // SRExitTime 114 .max_inter_dcn_tile_repeaters = 8, 115 .max_num_hdmi_frl_outputs = 1, 116 .odm_combine_4to1_supported = true, 117 118 .xfc_supported = false, 119 .xfc_fill_bw_overhead_percent = 10.0, 120 .xfc_fill_constant_bytes = 0, 121 .gfx7_compat_tiling_supported = 0, 122 .number_of_cursors = 1, 123}; 124 125struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = { 126 .clock_limits = { 127 { 128 .state = 0, 129 .dispclk_mhz = 562.0, 130 .dppclk_mhz = 300.0, 131 .phyclk_mhz = 300.0, 132 .phyclk_d18_mhz = 667.0, 133 .dscclk_mhz = 405.6, 134 }, 135 }, 136 137 .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */ 138 .num_states = 1, 139 .sr_exit_time_us = 15.5, 140 .sr_enter_plus_exit_time_us = 20, 141 .urgent_latency_us = 4.0, 142 .urgent_latency_pixel_data_only_us = 4.0, 143 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 144 .urgent_latency_vm_data_only_us = 4.0, 145 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 146 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 147 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 148 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 149 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, 150 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 151 .max_avg_sdp_bw_use_normal_percent = 60.0, 152 .max_avg_dram_bw_use_normal_percent = 40.0, 153 .writeback_latency_us = 12.0, 154 .max_request_size_bytes = 256, 155 .fabric_datapath_to_dcn_data_return_bytes = 64, 156 .dcn_downspread_percent = 0.5, 157 .downspread_percent = 0.38, 158 .dram_page_open_time_ns = 50.0, 159 .dram_rw_turnaround_time_ns = 17.5, 160 .dram_return_buffer_per_channel_bytes = 8192, 161 .round_trip_ping_latency_dcfclk_cycles = 191, 162 .urgent_out_of_order_return_per_channel_bytes = 4096, 163 .channel_interleave_bytes = 256, 164 .num_banks = 8, 165 .gpuvm_min_page_size_bytes = 4096, 166 .hostvm_min_page_size_bytes = 4096, 167 .dram_clock_change_latency_us = 404, 168 .dummy_pstate_latency_us = 5, 169 .writeback_dram_clock_change_latency_us = 23.0, 170 .return_bus_width_bytes = 64, 171 .dispclk_dppclk_vco_speed_mhz = 3650, 172 .xfc_bus_transport_time_us = 20, // ? 173 .xfc_xbuf_latency_tolerance_us = 4, // ? 174 .use_urgent_burst_bw = 1, // ? 175 .do_urgent_latency_adjustment = true, 176 .urgent_latency_adjustment_fabric_clock_component_us = 1.0, 177 .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000, 178}; 179 180 181void dcn30_fpu_populate_dml_writeback_from_context( 182 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) 183{ 184 int pipe_cnt, i, j; 185 double max_calc_writeback_dispclk; 186 double writeback_dispclk; 187 struct writeback_st dout_wb = {0}; 188 189 dc_assert_fp_enabled(); 190 191 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 192 struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream; 193 194 if (!stream) 195 continue; 196 max_calc_writeback_dispclk = 0; 197 198 /* Set writeback information */ 199 pipes[pipe_cnt].dout.wb_enable = 0; 200 pipes[pipe_cnt].dout.num_active_wb = 0; 201 for (j = 0; j < stream->num_wb_info; j++) { 202 struct dc_writeback_info *wb_info = &stream->writeback_info[j]; 203 204 if (wb_info->wb_enabled && wb_info->writeback_source_plane && 205 (wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) { 206 pipes[pipe_cnt].dout.wb_enable = 1; 207 pipes[pipe_cnt].dout.num_active_wb++; 208 dout_wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_en ? 209 wb_info->dwb_params.cnv_params.crop_height : 210 wb_info->dwb_params.cnv_params.src_height; 211 dout_wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_en ? 212 wb_info->dwb_params.cnv_params.crop_width : 213 wb_info->dwb_params.cnv_params.src_width; 214 dout_wb.wb_dst_width = wb_info->dwb_params.dest_width; 215 dout_wb.wb_dst_height = wb_info->dwb_params.dest_height; 216 217 /* For IP that doesn't support WB scaling, set h/v taps to 1 to avoid DML validation failure */ 218 if (dc->dml.ip.writeback_max_hscl_taps > 1) { 219 dout_wb.wb_htaps_luma = wb_info->dwb_params.scaler_taps.h_taps; 220 dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps; 221 } else { 222 dout_wb.wb_htaps_luma = 1; 223 dout_wb.wb_vtaps_luma = 1; 224 } 225 dout_wb.wb_htaps_chroma = 0; 226 dout_wb.wb_vtaps_chroma = 0; 227 dout_wb.wb_hratio = wb_info->dwb_params.cnv_params.crop_en ? 228 (double)wb_info->dwb_params.cnv_params.crop_width / 229 (double)wb_info->dwb_params.dest_width : 230 (double)wb_info->dwb_params.cnv_params.src_width / 231 (double)wb_info->dwb_params.dest_width; 232 dout_wb.wb_vratio = wb_info->dwb_params.cnv_params.crop_en ? 233 (double)wb_info->dwb_params.cnv_params.crop_height / 234 (double)wb_info->dwb_params.dest_height : 235 (double)wb_info->dwb_params.cnv_params.src_height / 236 (double)wb_info->dwb_params.dest_height; 237 if (wb_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB || 238 wb_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA) 239 dout_wb.wb_pixel_format = dm_444_64; 240 else 241 dout_wb.wb_pixel_format = dm_444_32; 242 243 /* Workaround for cases where multiple writebacks are connected to same plane 244 * In which case, need to compute worst case and set the associated writeback parameters 245 * This workaround is necessary due to DML computation assuming only 1 set of writeback 246 * parameters per pipe 247 */ 248 writeback_dispclk = dml30_CalculateWriteBackDISPCLK( 249 dout_wb.wb_pixel_format, 250 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz, 251 dout_wb.wb_hratio, 252 dout_wb.wb_vratio, 253 dout_wb.wb_htaps_luma, 254 dout_wb.wb_vtaps_luma, 255 dout_wb.wb_src_width, 256 dout_wb.wb_dst_width, 257 pipes[pipe_cnt].pipe.dest.htotal, 258 dc->current_state->bw_ctx.dml.ip.writeback_line_buffer_buffer_size); 259 260 if (writeback_dispclk > max_calc_writeback_dispclk) { 261 max_calc_writeback_dispclk = writeback_dispclk; 262 pipes[pipe_cnt].dout.wb = dout_wb; 263 } 264 } 265 } 266 267 pipe_cnt++; 268 } 269} 270 271void dcn30_fpu_set_mcif_arb_params(struct mcif_arb_params *wb_arb_params, 272 struct display_mode_lib *dml, 273 display_e2e_pipe_params_st *pipes, 274 int pipe_cnt, 275 int cur_pipe) 276{ 277 int i; 278 279 dc_assert_fp_enabled(); 280 281 for (i = 0; i < ARRAY_SIZE(wb_arb_params->cli_watermark); i++) { 282 wb_arb_params->cli_watermark[i] = get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000; 283 wb_arb_params->pstate_watermark[i] = get_wm_writeback_dram_clock_change(dml, pipes, pipe_cnt) * 1000; 284 } 285 286 wb_arb_params->dram_speed_change_duration = dml->vba.WritebackAllowDRAMClockChangeEndPosition[cur_pipe] * pipes[0].clks_cfg.refclk_mhz; /* num_clock_cycles = us * MHz */ 287} 288 289void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) 290{ 291 292 dc_assert_fp_enabled(); 293 294 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) { 295 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || 296 context->bw_ctx.dml.soc.dram_clock_change_latency_us == 0) 297 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 298 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us; 299 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us; 300 } 301} 302 303void dcn30_fpu_calculate_wm_and_dlg( 304 struct dc *dc, struct dc_state *context, 305 display_e2e_pipe_params_st *pipes, 306 int pipe_cnt, 307 int vlevel) 308{ 309 int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; 310 int i, pipe_idx; 311 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb]; 312 bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_change_unsupported; 313 unsigned int dummy_latency_index = 0; 314 struct dc_stream_status *stream_status = NULL; 315 316 dc_assert_fp_enabled(); 317 318 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; 319 for (i = 0; i < context->stream_count; i++) { 320 stream_status = NULL; 321 if (context->streams[i]) 322 stream_status = dc_state_get_stream_status(context, context->streams[i]); 323 if (stream_status) 324 stream_status->fpo_in_use = false; 325 } 326 327 if (!pstate_en) { 328 /* only when the mclk switch can not be natural, is the fw based vblank stretch attempted */ 329 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = 330 dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context); 331 332 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { 333 dummy_latency_index = dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(dc, 334 context, pipes, pipe_cnt, vlevel); 335 336 /* After calling dcn30_find_dummy_latency_index_for_fw_based_mclk_switch 337 * we reinstate the original dram_clock_change_latency_us on the context 338 * and all variables that may have changed up to this point, except the 339 * newly found dummy_latency_index 340 */ 341 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 342 dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, 343 DC_VALIDATE_MODE_AND_PROGRAMMING, true); 344 maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; 345 dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 346 pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_change_unsupported; 347 } 348 } 349 350 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) 351 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; 352 353 pipes[0].clks_cfg.voltage = vlevel; 354 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 355 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 356 357 /* Set B: 358 * DCFCLK: 1GHz or min required above 1GHz 359 * FCLK/UCLK: Max 360 */ 361 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { 362 if (vlevel == 0) { 363 pipes[0].clks_cfg.voltage = 1; 364 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz; 365 } 366 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us; 367 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us; 368 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us; 369 } 370 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 371 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 372 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 373 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 374 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 375 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 376 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 377 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 378 379 pipes[0].clks_cfg.voltage = vlevel; 380 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 381 382 /* Set D: 383 * DCFCLK: Min Required 384 * FCLK(proportional to UCLK): 1GHz or Max 385 * MALL stutter, sr_enter_exit = 4, sr_exit = 2us 386 */ 387 /* 388 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) { 389 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us; 390 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us; 391 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us; 392 } 393 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 394 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 395 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 396 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 397 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 398 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 399 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 400 context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 401 */ 402 403 /* Set C: 404 * DCFCLK: Min Required 405 * FCLK(proportional to UCLK): 1GHz or Max 406 * pstate latency overridden to 5us 407 */ 408 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { 409 unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed; 410 unsigned int min_dram_speed_mts_margin = 160; 411 412 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 413 dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us; 414 415 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] == 416 dm_dram_clock_change_unsupported) { 417 int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries - 1; 418 419 min_dram_speed_mts = 420 dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16; 421 } 422 423 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { 424 /* find largest table entry that is lower than dram speed, 425 * but lower than DPM0 still uses DPM0 426 */ 427 for (dummy_latency_index = 3; dummy_latency_index > 0; dummy_latency_index--) 428 if (min_dram_speed_mts + min_dram_speed_mts_margin > 429 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts) 430 break; 431 } 432 433 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 434 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; 435 436 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us; 437 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us; 438 } 439 440 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 441 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 442 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 443 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 444 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 445 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 446 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 447 context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 448 449 if (!pstate_en) { 450 /* The only difference between A and C is p-state latency, if p-state is not supported we want to 451 * calculate DLG based on dummy p-state latency, and max out the set A p-state watermark 452 */ 453 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c; 454 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0; 455 } else { 456 /* Set A: 457 * DCFCLK: Min Required 458 * FCLK(proportional to UCLK): 1GHz or Max 459 * 460 * Set A calculated last so that following calculations are based on Set A 461 */ 462 dc->res_pool->funcs->update_soc_for_wm_a(dc, context); 463 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 464 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 465 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 466 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 467 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 468 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 469 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 470 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 471 } 472 473 context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod; 474 475 /* Make set D = set A until set D is enabled */ 476 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; 477 478 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 479 if (!context->res_ctx.pipe_ctx[i].stream) 480 continue; 481 482 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); 483 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 484 485 if (dc->config.forced_clocks) { 486 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; 487 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; 488 } 489 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) 490 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; 491 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 492 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; 493 494 pipe_idx++; 495 } 496 497 // WA: restrict FPO to use first non-strobe mode (NV24 BW issue) 498 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && 499 dc->dml.soc.num_chans <= 4 && 500 context->bw_ctx.dml.vba.DRAMSpeed <= 1700 && 501 context->bw_ctx.dml.vba.DRAMSpeed >= 1500) { 502 503 for (i = 0; i < dc->dml.soc.num_states; i++) { 504 if (dc->dml.soc.clock_limits[i].dram_speed_mts > 1700) { 505 context->bw_ctx.dml.vba.DRAMSpeed = dc->dml.soc.clock_limits[i].dram_speed_mts; 506 break; 507 } 508 } 509 } 510 511 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 512 513 if (!pstate_en) 514 /* Restore full p-state latency */ 515 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 516 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 517 518 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) 519 dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(dc, context); 520} 521 522void dcn30_fpu_update_dram_channel_width_bytes(struct dc *dc) 523{ 524 dc_assert_fp_enabled(); 525 526 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) 527 dcn3_0_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; 528} 529 530void dcn30_fpu_update_max_clk(struct dc_bounding_box_max_clk *dcn30_bb_max_clk) 531{ 532 dc_assert_fp_enabled(); 533 534 if (!dcn30_bb_max_clk->max_dcfclk_mhz) 535 dcn30_bb_max_clk->max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz; 536 if (!dcn30_bb_max_clk->max_dispclk_mhz) 537 dcn30_bb_max_clk->max_dispclk_mhz = dcn3_0_soc.clock_limits[0].dispclk_mhz; 538 if (!dcn30_bb_max_clk->max_dppclk_mhz) 539 dcn30_bb_max_clk->max_dppclk_mhz = dcn3_0_soc.clock_limits[0].dppclk_mhz; 540 if (!dcn30_bb_max_clk->max_phyclk_mhz) 541 dcn30_bb_max_clk->max_phyclk_mhz = dcn3_0_soc.clock_limits[0].phyclk_mhz; 542} 543 544void dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, 545 unsigned int *optimal_dcfclk, 546 unsigned int *optimal_fclk) 547{ 548 double bw_from_dram, bw_from_dram1, bw_from_dram2; 549 550 dc_assert_fp_enabled(); 551 552 bw_from_dram1 = uclk_mts * dcn3_0_soc.num_chans * 553 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_dram_bw_use_normal_percent / 100); 554 bw_from_dram2 = uclk_mts * dcn3_0_soc.num_chans * 555 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100); 556 557 bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; 558 559 if (optimal_fclk) 560 *optimal_fclk = bw_from_dram / 561 (dcn3_0_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100)); 562 563 if (optimal_dcfclk) 564 *optimal_dcfclk = bw_from_dram / 565 (dcn3_0_soc.return_bus_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100)); 566} 567 568void dcn30_fpu_update_bw_bounding_box(struct dc *dc, 569 struct clk_bw_params *bw_params, 570 struct dc_bounding_box_max_clk *dcn30_bb_max_clk, 571 unsigned int *dcfclk_mhz, 572 unsigned int *dram_speed_mts) 573{ 574 unsigned int i; 575 576 dc_assert_fp_enabled(); 577 578 dcn3_0_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 579 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 580 581 for (i = 0; i < dcn3_0_soc.num_states; i++) { 582 dcn3_0_soc.clock_limits[i].state = i; 583 dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; 584 dcn3_0_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; 585 dcn3_0_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; 586 587 /* Fill all states with max values of all other clocks */ 588 dcn3_0_soc.clock_limits[i].dispclk_mhz = dcn30_bb_max_clk->max_dispclk_mhz; 589 dcn3_0_soc.clock_limits[i].dppclk_mhz = dcn30_bb_max_clk->max_dppclk_mhz; 590 dcn3_0_soc.clock_limits[i].phyclk_mhz = dcn30_bb_max_clk->max_phyclk_mhz; 591 dcn3_0_soc.clock_limits[i].dtbclk_mhz = dcn3_0_soc.clock_limits[0].dtbclk_mhz; 592 /* These clocks cannot come from bw_params, always fill from dcn3_0_soc[1] */ 593 /* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */ 594 dcn3_0_soc.clock_limits[i].phyclk_d18_mhz = dcn3_0_soc.clock_limits[0].phyclk_d18_mhz; 595 dcn3_0_soc.clock_limits[i].socclk_mhz = dcn3_0_soc.clock_limits[0].socclk_mhz; 596 dcn3_0_soc.clock_limits[i].dscclk_mhz = dcn3_0_soc.clock_limits[0].dscclk_mhz; 597 } 598 /* re-init DML with updated bb */ 599 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30); 600 if (dc->current_state) 601 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30); 602 603} 604 605/** 606 * dcn30_find_dummy_latency_index_for_fw_based_mclk_switch() - Finds 607 * dummy_latency_index when MCLK switching using firmware based vblank stretch 608 * is enabled. This function will iterate through the table of dummy pstate 609 * latencies until the lowest value that allows 610 * dm_allow_self_refresh_and_mclk_switch to happen is found 611 * 612 * @dc: Current DC state 613 * @context: new dc state 614 * @pipes: DML pipe params 615 * @pipe_cnt: number of DML pipes 616 * @vlevel: Voltage level calculated by DML 617 * 618 * Return: lowest dummy_latency_index value 619 */ 620int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, 621 struct dc_state *context, 622 display_e2e_pipe_params_st *pipes, 623 int pipe_cnt, 624 int vlevel) 625{ 626 const int max_latency_table_entries = 4; 627 int dummy_latency_index = 0; 628 629 dc_assert_fp_enabled(); 630 631 while (dummy_latency_index < max_latency_table_entries) { 632 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 633 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; 634 dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, 635 DC_VALIDATE_MODE_AND_PROGRAMMING, true); 636 637 if (context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank == 638 dm_allow_self_refresh_and_mclk_switch) 639 break; 640 641 dummy_latency_index++; 642 } 643 644 if (dummy_latency_index == max_latency_table_entries) { 645 ASSERT(dummy_latency_index != max_latency_table_entries); 646 /* If the execution gets here, it means dummy p_states are 647 * not possible. This should never happen and would mean 648 * something is severely wrong. 649 * Here we reset dummy_latency_index to 3, because it is 650 * better to have underflows than system crashes. 651 */ 652 dummy_latency_index = 3; 653 } 654 655 return dummy_latency_index; 656} 657 658void dcn3_fpu_build_wm_range_table(struct clk_mgr *base) 659{ 660 /* defaults */ 661 double pstate_latency_us = base->ctx->dc->dml.soc.dram_clock_change_latency_us; 662 double sr_exit_time_us = base->ctx->dc->dml.soc.sr_exit_time_us; 663 double sr_enter_plus_exit_time_us = base->ctx->dc->dml.soc.sr_enter_plus_exit_time_us; 664 uint16_t min_uclk_mhz = base->bw_params->clk_table.entries[0].memclk_mhz; 665 666 dc_assert_fp_enabled(); 667 668 /* Set A - Normal - default values*/ 669 base->bw_params->wm_table.nv_entries[WM_A].valid = true; 670 base->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; 671 base->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; 672 base->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; 673 base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; 674 base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 0; 675 base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; 676 base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz; 677 base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; 678 679 /* Set B - Performance - higher minimum clocks */ 680// base->bw_params->wm_table.nv_entries[WM_B].valid = true; 681// base->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us; 682// base->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us; 683// base->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; 684// base->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; 685// base->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = TUNED VALUE; 686// base->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF; 687// base->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = TUNED VALUE; 688// base->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF; 689 690 /* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */ 691 base->bw_params->wm_table.nv_entries[WM_C].valid = true; 692 base->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 0; 693 base->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us; 694 base->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; 695 base->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE; 696 base->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = 0; 697 base->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF; 698 base->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz; 699 base->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF; 700 base->bw_params->dummy_pstate_table[0].dram_speed_mts = 1600; 701 base->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 38; 702 base->bw_params->dummy_pstate_table[1].dram_speed_mts = 8000; 703 base->bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9; 704 base->bw_params->dummy_pstate_table[2].dram_speed_mts = 10000; 705 base->bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8; 706 base->bw_params->dummy_pstate_table[3].dram_speed_mts = 16000; 707 base->bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5; 708 709 /* Set D - MALL - SR enter and exit times adjusted for MALL */ 710 base->bw_params->wm_table.nv_entries[WM_D].valid = true; 711 base->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = pstate_latency_us; 712 base->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = 2; 713 base->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = 4; 714 base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL; 715 base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = 0; 716 base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF; 717 base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz; 718 base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF; 719} 720 721void patch_dcn30_soc_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *dcn3_0_ip) 722{ 723 dc_assert_fp_enabled(); 724 725 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 726 struct bp_soc_bb_info bb_info = {0}; 727 728 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 729 if (bb_info.dram_clock_change_latency_100ns > 0) 730 dcn3_0_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10; 731 732 if (bb_info.dram_sr_enter_exit_latency_100ns > 0) 733 dcn3_0_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10; 734 735 if (bb_info.dram_sr_exit_latency_100ns > 0) 736 dcn3_0_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10; 737 } 738 } 739}
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