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display_rq_dlg_calc_20.c
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linux-6.19.14/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1/* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#include "../display_mode_lib.h" 27#include "../display_mode_vba.h" 28#include "display_rq_dlg_calc_20.h" 29 30// Function: dml20_rq_dlg_get_rq_params 31// Calculate requestor related parameters that register definition agnostic 32// (i.e. this layer does try to separate real values from register definition) 33// Input: 34// pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.) 35// Output: 36// rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.) 37// 38static void dml20_rq_dlg_get_rq_params( 39 struct display_mode_lib *mode_lib, 40 display_rq_params_st *rq_param, 41 const display_pipe_source_params_st *pipe_src_param); 42 43// Function: dml20_rq_dlg_get_dlg_params 44// Calculate deadline related parameters 45// 46static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 47 const display_e2e_pipe_params_st *e2e_pipe_param, 48 const unsigned int num_pipes, 49 const unsigned int pipe_idx, 50 display_dlg_regs_st *disp_dlg_regs, 51 display_ttu_regs_st *disp_ttu_regs, 52 const display_rq_dlg_params_st *rq_dlg_param, 53 const display_dlg_sys_params_st *dlg_sys_param, 54 const bool cstate_en, 55 const bool pstate_en); 56/* 57 * NOTE: 58 * This file is gcc-parseable HW gospel, coming straight from HW engineers. 59 * 60 * It doesn't adhere to Linux kernel style and sometimes will do things in odd 61 * ways. Unless there is something clearly wrong with it the code should 62 * remain as-is as it provides us with a guarantee from HW that it is correct. 63 */ 64 65static void calculate_ttu_cursor(struct display_mode_lib *mode_lib, 66 double *refcyc_per_req_delivery_pre_cur, 67 double *refcyc_per_req_delivery_cur, 68 double refclk_freq_in_mhz, 69 double ref_freq_to_pix_freq, 70 double hscale_pixel_rate_l, 71 double hscl_ratio, 72 double vratio_pre_l, 73 double vratio_l, 74 unsigned int cur_width, 75 enum cursor_bpp cur_bpp); 76 77#include "../dml_inline_defs.h" 78 79static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma) 80{ 81 unsigned int ret_val = 1; 82 83 if (source_format == dm_444_16) { 84 if (!is_chroma) 85 ret_val = 2; 86 } else if (source_format == dm_444_32) { 87 if (!is_chroma) 88 ret_val = 4; 89 } else if (source_format == dm_444_64) { 90 if (!is_chroma) 91 ret_val = 8; 92 } else if (source_format == dm_420_8) { 93 if (is_chroma) 94 ret_val = 2; 95 else 96 ret_val = 1; 97 } else if (source_format == dm_420_10) { 98 if (is_chroma) 99 ret_val = 4; 100 else 101 ret_val = 2; 102 } else if (source_format == dm_444_8) { 103 ret_val = 1; 104 } 105 return ret_val; 106} 107 108static bool is_dual_plane(enum source_format_class source_format) 109{ 110 bool ret_val = false; 111 112 if ((source_format == dm_420_8) || (source_format == dm_420_10)) 113 ret_val = true; 114 115 return ret_val; 116} 117 118static double get_refcyc_per_delivery(struct display_mode_lib *mode_lib, 119 double refclk_freq_in_mhz, 120 double pclk_freq_in_mhz, 121 bool odm_combine, 122 unsigned int recout_width, 123 unsigned int hactive, 124 double vratio, 125 double hscale_pixel_rate, 126 unsigned int delivery_width, 127 unsigned int req_per_swath_ub) 128{ 129 double refcyc_per_delivery = 0.0; 130 131 if (vratio <= 1.0) { 132 if (odm_combine) 133 refcyc_per_delivery = (double) refclk_freq_in_mhz 134 * dml_min((double) recout_width, (double) hactive / 2.0) 135 / pclk_freq_in_mhz / (double) req_per_swath_ub; 136 else 137 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width 138 / pclk_freq_in_mhz / (double) req_per_swath_ub; 139 } else { 140 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width 141 / (double) hscale_pixel_rate / (double) req_per_swath_ub; 142 } 143 144 dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz); 145 dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz); 146 dml_print("DML_DLG: %s: recout_width = %d\n", __func__, recout_width); 147 dml_print("DML_DLG: %s: vratio = %3.2f\n", __func__, vratio); 148 dml_print("DML_DLG: %s: req_per_swath_ub = %d\n", __func__, req_per_swath_ub); 149 dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery); 150 151 return refcyc_per_delivery; 152 153} 154 155static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size) 156{ 157 if (tile_size == dm_256k_tile) 158 return (256 * 1024); 159 else if (tile_size == dm_64k_tile) 160 return (64 * 1024); 161 else 162 return (4 * 1024); 163} 164 165static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib, 166 display_data_rq_regs_st *rq_regs, 167 const display_data_rq_sizing_params_st *rq_sizing) 168{ 169 dml_print("DML_DLG: %s: rq_sizing param\n", __func__); 170 print__data_rq_sizing_params_st(mode_lib, rq_sizing); 171 172 rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10; 173 174 if (rq_sizing->min_chunk_bytes == 0) 175 rq_regs->min_chunk_size = 0; 176 else 177 rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1; 178 179 rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10; 180 if (rq_sizing->min_meta_chunk_bytes == 0) 181 rq_regs->min_meta_chunk_size = 0; 182 else 183 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1; 184 185 rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6; 186 rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6; 187} 188 189static void extract_rq_regs(struct display_mode_lib *mode_lib, 190 display_rq_regs_st *rq_regs, 191 const display_rq_params_st *rq_param) 192{ 193 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; 194 unsigned int detile_buf_plane1_addr = 0; 195 196 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); 197 198 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), 199 1) - 3; 200 201 if (rq_param->yuv420) { 202 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); 203 rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), 204 1) - 3; 205 } 206 207 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); 208 rq_regs->rq_regs_c.swath_height = dml_log2(rq_param->dlg.rq_c.swath_height); 209 210 // TODO: take the max between luma, chroma chunk size? 211 // okay for now, as we are setting chunk_bytes to 8kb anyways 212 if (rq_param->sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb 213 rq_regs->drq_expansion_mode = 0; 214 } else { 215 rq_regs->drq_expansion_mode = 2; 216 } 217 rq_regs->prq_expansion_mode = 1; 218 rq_regs->mrq_expansion_mode = 1; 219 rq_regs->crq_expansion_mode = 1; 220 221 if (rq_param->yuv420) { 222 if ((double) rq_param->misc.rq_l.stored_swath_bytes 223 / (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { 224 detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma 225 } else { 226 detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 227 256, 228 0) / 64.0; // 2/3 to chroma 229 } 230 } 231 rq_regs->plane1_base_address = detile_buf_plane1_addr; 232} 233 234static void handle_det_buf_split(struct display_mode_lib *mode_lib, 235 display_rq_params_st *rq_param, 236 const display_pipe_source_params_st *pipe_src_param) 237{ 238 unsigned int total_swath_bytes = 0; 239 unsigned int swath_bytes_l = 0; 240 unsigned int swath_bytes_c = 0; 241 unsigned int full_swath_bytes_packed_l = 0; 242 unsigned int full_swath_bytes_packed_c = 0; 243 bool req128_l = false; 244 bool req128_c = false; 245 bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear); 246 bool surf_vert = (pipe_src_param->source_scan == dm_vert); 247 unsigned int log2_swath_height_l = 0; 248 unsigned int log2_swath_height_c = 0; 249 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; 250 251 full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes; 252 full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes; 253 254 if (rq_param->yuv420_10bpc) { 255 full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2 / 3, 256 256, 257 1) + 256; 258 full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2 / 3, 259 256, 260 1) + 256; 261 } 262 263 if (rq_param->yuv420) { 264 total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c; 265 266 if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request 267 req128_l = false; 268 req128_c = false; 269 swath_bytes_l = full_swath_bytes_packed_l; 270 swath_bytes_c = full_swath_bytes_packed_c; 271 } else { //128b request (for luma only for yuv420 8bpc) 272 req128_l = true; 273 req128_c = false; 274 swath_bytes_l = full_swath_bytes_packed_l / 2; 275 swath_bytes_c = full_swath_bytes_packed_c; 276 } 277 // Note: assumption, the config that pass in will fit into 278 // the detiled buffer. 279 } else { 280 total_swath_bytes = 2 * full_swath_bytes_packed_l; 281 282 if (total_swath_bytes <= detile_buf_size_in_bytes) 283 req128_l = false; 284 else 285 req128_l = true; 286 287 swath_bytes_l = total_swath_bytes; 288 swath_bytes_c = 0; 289 } 290 rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l; 291 rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c; 292 293 if (surf_linear) { 294 log2_swath_height_l = 0; 295 log2_swath_height_c = 0; 296 } else { 297 unsigned int swath_height_l; 298 unsigned int swath_height_c; 299 300 if (!surf_vert) { 301 swath_height_l = rq_param->misc.rq_l.blk256_height; 302 swath_height_c = rq_param->misc.rq_c.blk256_height; 303 } else { 304 swath_height_l = rq_param->misc.rq_l.blk256_width; 305 swath_height_c = rq_param->misc.rq_c.blk256_width; 306 } 307 308 if (swath_height_l > 0) 309 log2_swath_height_l = dml_log2(swath_height_l); 310 311 if (req128_l && log2_swath_height_l > 0) 312 log2_swath_height_l -= 1; 313 314 if (swath_height_c > 0) 315 log2_swath_height_c = dml_log2(swath_height_c); 316 } 317 318 rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l; 319 rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c; 320 321 dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l); 322 dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c); 323 dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n", 324 __func__, 325 full_swath_bytes_packed_l); 326 dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n", 327 __func__, 328 full_swath_bytes_packed_c); 329} 330 331static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, 332 display_data_rq_dlg_params_st *rq_dlg_param, 333 display_data_rq_misc_params_st *rq_misc_param, 334 display_data_rq_sizing_params_st *rq_sizing_param, 335 unsigned int vp_width, 336 unsigned int vp_height, 337 unsigned int data_pitch, 338 unsigned int meta_pitch, 339 unsigned int source_format, 340 unsigned int tiling, 341 unsigned int macro_tile_size, 342 unsigned int source_scan, 343 unsigned int is_chroma) 344{ 345 bool surf_linear = (tiling == dm_sw_linear); 346 bool surf_vert = (source_scan == dm_vert); 347 348 unsigned int bytes_per_element; 349 unsigned int bytes_per_element_y = get_bytes_per_element((enum source_format_class)(source_format), 350 false); 351 unsigned int bytes_per_element_c = get_bytes_per_element((enum source_format_class)(source_format), 352 true); 353 354 unsigned int blk256_width = 0; 355 unsigned int blk256_height = 0; 356 357 unsigned int blk256_width_y = 0; 358 unsigned int blk256_height_y = 0; 359 unsigned int blk256_width_c = 0; 360 unsigned int blk256_height_c = 0; 361 unsigned int log2_bytes_per_element; 362 unsigned int log2_blk256_width; 363 unsigned int log2_blk256_height; 364 unsigned int blk_bytes; 365 unsigned int log2_blk_bytes; 366 unsigned int log2_blk_height; 367 unsigned int log2_blk_width; 368 unsigned int log2_meta_req_bytes; 369 unsigned int log2_meta_req_height; 370 unsigned int log2_meta_req_width; 371 unsigned int meta_req_width; 372 unsigned int meta_req_height; 373 unsigned int log2_meta_row_height; 374 unsigned int meta_row_width_ub; 375 unsigned int log2_meta_chunk_bytes; 376 unsigned int log2_meta_chunk_height; 377 378 //full sized meta chunk width in unit of data elements 379 unsigned int log2_meta_chunk_width; 380 unsigned int log2_min_meta_chunk_bytes; 381 unsigned int min_meta_chunk_width; 382 unsigned int meta_chunk_width; 383 unsigned int meta_chunk_per_row_int; 384 unsigned int meta_row_remainder; 385 unsigned int meta_chunk_threshold; 386 unsigned int meta_blk_bytes; 387 unsigned int meta_blk_height; 388 unsigned int meta_blk_width; 389 unsigned int meta_surface_bytes; 390 unsigned int vmpg_bytes; 391 unsigned int meta_pte_req_per_frame_ub; 392 unsigned int meta_pte_bytes_per_frame_ub; 393 const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes); 394 const unsigned int dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma; 395 const unsigned int pde_proc_buffer_size_64k_reqs = 396 mode_lib->ip.pde_proc_buffer_size_64k_reqs; 397 398 unsigned int log2_vmpg_height = 0; 399 unsigned int log2_vmpg_width = 0; 400 unsigned int log2_dpte_req_height_ptes = 0; 401 unsigned int log2_dpte_req_height = 0; 402 unsigned int log2_dpte_req_width = 0; 403 unsigned int log2_dpte_row_height_linear = 0; 404 unsigned int log2_dpte_row_height = 0; 405 unsigned int log2_dpte_group_width = 0; 406 unsigned int dpte_row_width_ub = 0; 407 unsigned int dpte_req_height = 0; 408 unsigned int dpte_req_width = 0; 409 unsigned int dpte_group_width = 0; 410 unsigned int log2_dpte_group_bytes = 0; 411 unsigned int log2_dpte_group_length = 0; 412 unsigned int pde_buf_entries; 413 bool yuv420 = (source_format == dm_420_8 || source_format == dm_420_10); 414 415 Calculate256BBlockSizes((enum source_format_class)(source_format), 416 (enum dm_swizzle_mode)(tiling), 417 bytes_per_element_y, 418 bytes_per_element_c, 419 &blk256_height_y, 420 &blk256_height_c, 421 &blk256_width_y, 422 &blk256_width_c); 423 424 if (!is_chroma) { 425 blk256_width = blk256_width_y; 426 blk256_height = blk256_height_y; 427 bytes_per_element = bytes_per_element_y; 428 } else { 429 blk256_width = blk256_width_c; 430 blk256_height = blk256_height_c; 431 bytes_per_element = bytes_per_element_c; 432 } 433 434 log2_bytes_per_element = dml_log2(bytes_per_element); 435 436 dml_print("DML_DLG: %s: surf_linear = %d\n", __func__, surf_linear); 437 dml_print("DML_DLG: %s: surf_vert = %d\n", __func__, surf_vert); 438 dml_print("DML_DLG: %s: blk256_width = %d\n", __func__, blk256_width); 439 dml_print("DML_DLG: %s: blk256_height = %d\n", __func__, blk256_height); 440 441 log2_blk256_width = dml_log2((double) blk256_width); 442 log2_blk256_height = dml_log2((double) blk256_height); 443 blk_bytes = surf_linear ? 444 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size); 445 log2_blk_bytes = dml_log2((double) blk_bytes); 446 447 // remember log rule 448 // "+" in log is multiply 449 // "-" in log is divide 450 // "/2" is like square root 451 // blk is vertical biased 452 if (tiling != dm_sw_linear) 453 log2_blk_height = log2_blk256_height 454 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); 455 else 456 log2_blk_height = 0; // blk height of 1 457 458 log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height; 459 460 if (!surf_vert) { 461 rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1) 462 + blk256_width; 463 rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width; 464 } else { 465 rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_height - 1, blk256_height, 1) 466 + blk256_height; 467 rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height; 468 } 469 470 if (!surf_vert) 471 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height 472 * bytes_per_element; 473 else 474 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width 475 * bytes_per_element; 476 477 rq_misc_param->blk256_height = blk256_height; 478 rq_misc_param->blk256_width = blk256_width; 479 480 // ------- 481 // meta 482 // ------- 483 log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element 484 485 // each 64b meta request for dcn is 8x8 meta elements and 486 // a meta element covers one 256b block of the data surface. 487 log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256 488 log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element 489 - log2_meta_req_height; 490 meta_req_width = 1 << log2_meta_req_width; 491 meta_req_height = 1 << log2_meta_req_height; 492 493 // the dimensions of a meta row are meta_row_width x meta_row_height in elements. 494 // calculate upper bound of the meta_row_width 495 if (!surf_vert) { 496 log2_meta_row_height = log2_meta_req_height; 497 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) 498 + meta_req_width; 499 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; 500 } else { 501 log2_meta_row_height = log2_meta_req_width; 502 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) 503 + meta_req_height; 504 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; 505 } 506 rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64; 507 508 rq_dlg_param->meta_row_height = 1 << log2_meta_row_height; 509 510 log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes); 511 log2_meta_chunk_height = log2_meta_row_height; 512 513 //full sized meta chunk width in unit of data elements 514 log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element 515 - log2_meta_chunk_height; 516 log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes); 517 min_meta_chunk_width = 1 518 << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element 519 - log2_meta_chunk_height); 520 meta_chunk_width = 1 << log2_meta_chunk_width; 521 meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width); 522 meta_row_remainder = meta_row_width_ub % meta_chunk_width; 523 meta_chunk_threshold = 0; 524 meta_blk_bytes = 4096; 525 meta_blk_height = blk256_height * 64; 526 meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height; 527 meta_surface_bytes = meta_pitch 528 * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) + meta_blk_height) 529 * bytes_per_element / 256; 530 vmpg_bytes = mode_lib->soc.vmm_page_size_bytes; 531 meta_pte_req_per_frame_ub = (dml_round_to_multiple(meta_surface_bytes - vmpg_bytes, 532 8 * vmpg_bytes, 533 1) + 8 * vmpg_bytes) / (8 * vmpg_bytes); 534 meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request 535 rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub; 536 537 dml_print("DML_DLG: %s: meta_blk_height = %d\n", __func__, meta_blk_height); 538 dml_print("DML_DLG: %s: meta_blk_width = %d\n", __func__, meta_blk_width); 539 dml_print("DML_DLG: %s: meta_surface_bytes = %d\n", __func__, meta_surface_bytes); 540 dml_print("DML_DLG: %s: meta_pte_req_per_frame_ub = %d\n", 541 __func__, 542 meta_pte_req_per_frame_ub); 543 dml_print("DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n", 544 __func__, 545 meta_pte_bytes_per_frame_ub); 546 547 if (!surf_vert) 548 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; 549 else 550 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; 551 552 if (meta_row_remainder <= meta_chunk_threshold) 553 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1; 554 else 555 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2; 556 557 // ------ 558 // dpte 559 // ------ 560 if (surf_linear) { 561 log2_vmpg_height = 0; // one line high 562 } else { 563 log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height; 564 } 565 log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height; 566 567 // only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4. 568 if (surf_linear) { //one 64B PTE request returns 8 PTEs 569 log2_dpte_req_height_ptes = 0; 570 log2_dpte_req_width = log2_vmpg_width + 3; 571 log2_dpte_req_height = 0; 572 } else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size 573 //one 64B req gives 8x1 PTEs for 4KB tile 574 log2_dpte_req_height_ptes = 0; 575 log2_dpte_req_width = log2_blk_width + 3; 576 log2_dpte_req_height = log2_blk_height + 0; 577 } else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB 578 //two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB 579 log2_dpte_req_height_ptes = 4; 580 log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width 581 log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height 582 } else { //64KB page size and must 64KB tile block 583 //one 64B req gives 8x1 PTEs for 64KB tile 584 log2_dpte_req_height_ptes = 0; 585 log2_dpte_req_width = log2_blk_width + 3; 586 log2_dpte_req_height = log2_blk_height + 0; 587 } 588 589 // The dpte request dimensions in data elements is dpte_req_width x dpte_req_height 590 // log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent 591 // That depends on the pte shape (i.e. 8x1, 4x2, 2x4) 592 //log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes; 593 //log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes; 594 dpte_req_height = 1 << log2_dpte_req_height; 595 dpte_req_width = 1 << log2_dpte_req_width; 596 597 // calculate pitch dpte row buffer can hold 598 // round the result down to a power of two. 599 pde_buf_entries = yuv420 ? (pde_proc_buffer_size_64k_reqs >> 1) : pde_proc_buffer_size_64k_reqs; 600 if (surf_linear) { 601 unsigned int dpte_row_height; 602 603 log2_dpte_row_height_linear = dml_floor(dml_log2(dml_min(64 * 1024 * pde_buf_entries 604 / bytes_per_element, 605 dpte_buf_in_pte_reqs 606 * dpte_req_width) 607 / data_pitch), 608 1); 609 610 ASSERT(log2_dpte_row_height_linear >= 3); 611 612 if (log2_dpte_row_height_linear > 7) 613 log2_dpte_row_height_linear = 7; 614 615 log2_dpte_row_height = log2_dpte_row_height_linear; 616 // For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary. 617 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering. 618 dpte_row_height = 1 << log2_dpte_row_height; 619 dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1, 620 dpte_req_width, 621 1) + dpte_req_width; 622 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; 623 } else { 624 // the upper bound of the dpte_row_width without dependency on viewport position follows. 625 // for tiled mode, row height is the same as req height and row store up to vp size upper bound 626 if (!surf_vert) { 627 log2_dpte_row_height = log2_dpte_req_height; 628 dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1) 629 + dpte_req_width; 630 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; 631 } else { 632 log2_dpte_row_height = 633 (log2_blk_width < log2_dpte_req_width) ? 634 log2_blk_width : log2_dpte_req_width; 635 dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1) 636 + dpte_req_height; 637 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height; 638 } 639 } 640 if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB 641 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request 642 else 643 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request 644 645 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; 646 647 // the dpte_group_bytes is reduced for the specific case of vertical 648 // access of a tile surface that has dpte request of 8x1 ptes. 649 if (!surf_linear && (log2_dpte_req_height_ptes == 0) && surf_vert) //reduced, in this case, will have page fault within a group 650 rq_sizing_param->dpte_group_bytes = 512; 651 else 652 //full size 653 rq_sizing_param->dpte_group_bytes = 2048; 654 655 //since pte request size is 64byte, the number of data pte requests per full sized group is as follows. 656 log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes); 657 log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests 658 659 // full sized data pte group width in elements 660 if (!surf_vert) 661 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width; 662 else 663 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height; 664 665 //But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B 666 if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB 667 log2_dpte_group_width = log2_dpte_group_width - 1; 668 669 dpte_group_width = 1 << log2_dpte_group_width; 670 671 // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, 672 // the upper bound for the dpte groups per row is as follows. 673 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, 674 1); 675} 676 677static void get_surf_rq_param(struct display_mode_lib *mode_lib, 678 display_data_rq_sizing_params_st *rq_sizing_param, 679 display_data_rq_dlg_params_st *rq_dlg_param, 680 display_data_rq_misc_params_st *rq_misc_param, 681 const display_pipe_source_params_st *pipe_src_param, 682 bool is_chroma) 683{ 684 unsigned int vp_width = 0; 685 unsigned int vp_height = 0; 686 unsigned int data_pitch = 0; 687 unsigned int meta_pitch = 0; 688 unsigned int ppe = 1; 689 690 // TODO check if ppe apply for both luma and chroma in 422 case 691 if (is_chroma) { 692 vp_width = pipe_src_param->viewport_width_c / ppe; 693 vp_height = pipe_src_param->viewport_height_c; 694 data_pitch = pipe_src_param->data_pitch_c; 695 meta_pitch = pipe_src_param->meta_pitch_c; 696 } else { 697 vp_width = pipe_src_param->viewport_width / ppe; 698 vp_height = pipe_src_param->viewport_height; 699 data_pitch = pipe_src_param->data_pitch; 700 meta_pitch = pipe_src_param->meta_pitch; 701 } 702 703 rq_sizing_param->chunk_bytes = 8192; 704 705 if (rq_sizing_param->chunk_bytes == 64 * 1024) 706 rq_sizing_param->min_chunk_bytes = 0; 707 else 708 rq_sizing_param->min_chunk_bytes = 1024; 709 710 rq_sizing_param->meta_chunk_bytes = 2048; 711 rq_sizing_param->min_meta_chunk_bytes = 256; 712 713 rq_sizing_param->mpte_group_bytes = 2048; 714 715 get_meta_and_pte_attr(mode_lib, 716 rq_dlg_param, 717 rq_misc_param, 718 rq_sizing_param, 719 vp_width, 720 vp_height, 721 data_pitch, 722 meta_pitch, 723 pipe_src_param->source_format, 724 pipe_src_param->sw_mode, 725 pipe_src_param->macro_tile_size, 726 pipe_src_param->source_scan, 727 is_chroma); 728} 729 730static void dml20_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, 731 display_rq_params_st *rq_param, 732 const display_pipe_source_params_st *pipe_src_param) 733{ 734 // get param for luma surface 735 rq_param->yuv420 = pipe_src_param->source_format == dm_420_8 736 || pipe_src_param->source_format == dm_420_10; 737 rq_param->yuv420_10bpc = pipe_src_param->source_format == dm_420_10; 738 739 get_surf_rq_param(mode_lib, 740 &(rq_param->sizing.rq_l), 741 &(rq_param->dlg.rq_l), 742 &(rq_param->misc.rq_l), 743 pipe_src_param, 744 0); 745 746 if (is_dual_plane((enum source_format_class)(pipe_src_param->source_format))) { 747 // get param for chroma surface 748 get_surf_rq_param(mode_lib, 749 &(rq_param->sizing.rq_c), 750 &(rq_param->dlg.rq_c), 751 &(rq_param->misc.rq_c), 752 pipe_src_param, 753 1); 754 } 755 756 // calculate how to split the det buffer space between luma and chroma 757 handle_det_buf_split(mode_lib, rq_param, pipe_src_param); 758 print__rq_params_st(mode_lib, rq_param); 759} 760 761void dml20_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, 762 display_rq_regs_st *rq_regs, 763 const display_pipe_params_st *pipe_param) 764{ 765 display_rq_params_st rq_param = {0}; 766 767 memset(rq_regs, 0, sizeof(*rq_regs)); 768 dml20_rq_dlg_get_rq_params(mode_lib, &rq_param, &pipe_param->src); 769 extract_rq_regs(mode_lib, rq_regs, &rq_param); 770 771 print__rq_regs_st(mode_lib, rq_regs); 772} 773 774// Note: currently taken in as is. 775// Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma. 776static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 777 const display_e2e_pipe_params_st *e2e_pipe_param, 778 const unsigned int num_pipes, 779 const unsigned int pipe_idx, 780 display_dlg_regs_st *disp_dlg_regs, 781 display_ttu_regs_st *disp_ttu_regs, 782 const display_rq_dlg_params_st *rq_dlg_param, 783 const display_dlg_sys_params_st *dlg_sys_param, 784 const bool cstate_en, 785 const bool pstate_en) 786{ 787 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; 788 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; 789 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; 790 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; 791 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; 792 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; 793 794 // ------------------------- 795 // Section 1.15.2.1: OTG dependent Params 796 // ------------------------- 797 // Timing 798 unsigned int htotal = dst->htotal; 799// unsigned int hblank_start = dst.hblank_start; // TODO: Remove 800 unsigned int hblank_end = dst->hblank_end; 801 unsigned int vblank_start = dst->vblank_start; 802 unsigned int vblank_end = dst->vblank_end; 803 unsigned int min_vblank = mode_lib->ip.min_vblank_lines; 804 805 double dppclk_freq_in_mhz = clks->dppclk_mhz; 806 double dispclk_freq_in_mhz = clks->dispclk_mhz; 807 double refclk_freq_in_mhz = clks->refclk_mhz; 808 double pclk_freq_in_mhz = dst->pixel_rate_mhz; 809 bool interlaced = dst->interlaced; 810 811 double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; 812 813 double min_dcfclk_mhz; 814 double t_calc_us; 815 double min_ttu_vblank; 816 817 double min_dst_y_ttu_vblank; 818 unsigned int dlg_vblank_start; 819 bool dual_plane; 820 unsigned int access_dir; 821 unsigned int vp_height_l; 822 unsigned int vp_width_l; 823 unsigned int vp_height_c; 824 unsigned int vp_width_c; 825 826 // Scaling 827 unsigned int htaps_l; 828 unsigned int htaps_c; 829 double hratio_l; 830 double hratio_c; 831 double vratio_l; 832 double vratio_c; 833 bool scl_enable; 834 835 double line_time_in_us; 836 // double vinit_l; 837 // double vinit_c; 838 // double vinit_bot_l; 839 // double vinit_bot_c; 840 841 // unsigned int swath_height_l; 842 unsigned int swath_width_ub_l; 843 // unsigned int dpte_bytes_per_row_ub_l; 844 unsigned int dpte_groups_per_row_ub_l; 845 // unsigned int meta_pte_bytes_per_frame_ub_l; 846 // unsigned int meta_bytes_per_row_ub_l; 847 848 // unsigned int swath_height_c; 849 unsigned int swath_width_ub_c; 850 // unsigned int dpte_bytes_per_row_ub_c; 851 unsigned int dpte_groups_per_row_ub_c; 852 853 unsigned int meta_chunks_per_row_ub_l; 854 unsigned int meta_chunks_per_row_ub_c; 855 unsigned int vupdate_offset; 856 unsigned int vupdate_width; 857 unsigned int vready_offset; 858 859 unsigned int dppclk_delay_subtotal; 860 unsigned int dispclk_delay_subtotal; 861 unsigned int pixel_rate_delay_subtotal; 862 863 unsigned int vstartup_start; 864 unsigned int dst_x_after_scaler; 865 unsigned int dst_y_after_scaler; 866 double line_wait; 867 double dst_y_prefetch; 868 double dst_y_per_vm_vblank; 869 double dst_y_per_row_vblank; 870 double dst_y_per_vm_flip; 871 double dst_y_per_row_flip; 872 double min_dst_y_per_vm_vblank; 873 double min_dst_y_per_row_vblank; 874 double lsw; 875 double vratio_pre_l; 876 double vratio_pre_c; 877 unsigned int req_per_swath_ub_l; 878 unsigned int req_per_swath_ub_c; 879 unsigned int meta_row_height_l; 880 unsigned int meta_row_height_c; 881 unsigned int swath_width_pixels_ub_l; 882 unsigned int swath_width_pixels_ub_c; 883 unsigned int scaler_rec_in_width_l; 884 unsigned int scaler_rec_in_width_c; 885 unsigned int dpte_row_height_l; 886 unsigned int dpte_row_height_c; 887 double hscale_pixel_rate_l; 888 double hscale_pixel_rate_c; 889 double min_hratio_fact_l; 890 double min_hratio_fact_c; 891 double refcyc_per_line_delivery_pre_l; 892 double refcyc_per_line_delivery_pre_c; 893 double refcyc_per_line_delivery_l; 894 double refcyc_per_line_delivery_c; 895 896 double refcyc_per_req_delivery_pre_l; 897 double refcyc_per_req_delivery_pre_c; 898 double refcyc_per_req_delivery_l; 899 double refcyc_per_req_delivery_c; 900 901 unsigned int full_recout_width; 902 double refcyc_per_req_delivery_pre_cur0; 903 double refcyc_per_req_delivery_cur0; 904 double refcyc_per_req_delivery_pre_cur1; 905 double refcyc_per_req_delivery_cur1; 906 907 memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); 908 memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs)); 909 910 dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en); 911 dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en); 912 913 dml_print("DML_DLG: %s: dppclk_freq_in_mhz = %3.2f\n", __func__, dppclk_freq_in_mhz); 914 dml_print("DML_DLG: %s: dispclk_freq_in_mhz = %3.2f\n", __func__, dispclk_freq_in_mhz); 915 dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz); 916 dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz); 917 dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced); 918 ASSERT(ref_freq_to_pix_freq < 4.0); 919 920 disp_dlg_regs->ref_freq_to_pix_freq = 921 (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); 922 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal 923 * dml_pow(2, 8)); 924 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits 925 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end 926 * (double) ref_freq_to_pix_freq); 927 ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13)); 928 929 min_dcfclk_mhz = dlg_sys_param->deepsleep_dcfclk_mhz; 930 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); 931 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 932 933 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal; 934 dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; 935 936 disp_dlg_regs->min_dst_y_next_start = (unsigned int) ((double) dlg_vblank_start * dml_pow(2, 2)); 937 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18)); 938 939 dml_print("DML_DLG: %s: min_dcfclk_mhz = %3.2f\n", 940 __func__, 941 min_dcfclk_mhz); 942 dml_print("DML_DLG: %s: min_ttu_vblank = %3.2f\n", 943 __func__, 944 min_ttu_vblank); 945 dml_print("DML_DLG: %s: min_dst_y_ttu_vblank = %3.2f\n", 946 __func__, 947 min_dst_y_ttu_vblank); 948 dml_print("DML_DLG: %s: t_calc_us = %3.2f\n", 949 __func__, 950 t_calc_us); 951 dml_print("DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x\n", 952 __func__, 953 disp_dlg_regs->min_dst_y_next_start); 954 dml_print("DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n", 955 __func__, 956 ref_freq_to_pix_freq); 957 958 // ------------------------- 959 // Section 1.15.2.2: Prefetch, Active and TTU 960 // ------------------------- 961 // Prefetch Calc 962 // Source 963// dcc_en = src.dcc; 964 dual_plane = is_dual_plane((enum source_format_class)(src->source_format)); 965 access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed 966// bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0); 967// bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1); 968 vp_height_l = src->viewport_height; 969 vp_width_l = src->viewport_width; 970 vp_height_c = src->viewport_height_c; 971 vp_width_c = src->viewport_width_c; 972 973 // Scaling 974 htaps_l = taps->htaps; 975 htaps_c = taps->htaps_c; 976 hratio_l = scl->hscl_ratio; 977 hratio_c = scl->hscl_ratio_c; 978 vratio_l = scl->vscl_ratio; 979 vratio_c = scl->vscl_ratio_c; 980 scl_enable = scl->scl_enable; 981 982 line_time_in_us = (htotal / pclk_freq_in_mhz); 983// vinit_l = scl.vinit; 984// vinit_c = scl.vinit_c; 985// vinit_bot_l = scl.vinit_bot; 986// vinit_bot_c = scl.vinit_bot_c; 987 988// unsigned int swath_height_l = rq_dlg_param->rq_l.swath_height; 989 swath_width_ub_l = rq_dlg_param->rq_l.swath_width_ub; 990// unsigned int dpte_bytes_per_row_ub_l = rq_dlg_param->rq_l.dpte_bytes_per_row_ub; 991 dpte_groups_per_row_ub_l = rq_dlg_param->rq_l.dpte_groups_per_row_ub; 992// unsigned int meta_pte_bytes_per_frame_ub_l = rq_dlg_param->rq_l.meta_pte_bytes_per_frame_ub; 993// unsigned int meta_bytes_per_row_ub_l = rq_dlg_param->rq_l.meta_bytes_per_row_ub; 994 995// unsigned int swath_height_c = rq_dlg_param->rq_c.swath_height; 996 swath_width_ub_c = rq_dlg_param->rq_c.swath_width_ub; 997 // dpte_bytes_per_row_ub_c = rq_dlg_param->rq_c.dpte_bytes_per_row_ub; 998 dpte_groups_per_row_ub_c = rq_dlg_param->rq_c.dpte_groups_per_row_ub; 999 1000 meta_chunks_per_row_ub_l = rq_dlg_param->rq_l.meta_chunks_per_row_ub; 1001 meta_chunks_per_row_ub_c = rq_dlg_param->rq_c.meta_chunks_per_row_ub; 1002 vupdate_offset = dst->vupdate_offset; 1003 vupdate_width = dst->vupdate_width; 1004 vready_offset = dst->vready_offset; 1005 1006 dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal; 1007 dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal; 1008 1009 if (scl_enable) 1010 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl; 1011 else 1012 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only; 1013 1014 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter 1015 + src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor; 1016 1017 if (dout->dsc_enable) { 1018 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1019 1020 dispclk_delay_subtotal += dsc_delay; 1021 } 1022 1023 pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz 1024 + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; 1025 1026 vstartup_start = dst->vstartup_start; 1027 if (interlaced) { 1028 if (vstartup_start / 2.0 1029 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal 1030 <= vblank_end / 2.0) 1031 disp_dlg_regs->vready_after_vcount0 = 1; 1032 else 1033 disp_dlg_regs->vready_after_vcount0 = 0; 1034 } else { 1035 if (vstartup_start 1036 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal 1037 <= vblank_end) 1038 disp_dlg_regs->vready_after_vcount0 = 1; 1039 else 1040 disp_dlg_regs->vready_after_vcount0 = 0; 1041 } 1042 1043 // TODO: Where is this coming from? 1044 if (interlaced) 1045 vstartup_start = vstartup_start / 2; 1046 1047 // TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp? 1048 if (vstartup_start >= min_vblank) { 1049 dml_print("WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n", 1050 __func__, 1051 vblank_start, 1052 vblank_end); 1053 dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n", 1054 __func__, 1055 vstartup_start, 1056 min_vblank); 1057 min_vblank = vstartup_start + 1; 1058 dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n", 1059 __func__, 1060 vstartup_start, 1061 min_vblank); 1062 } 1063 1064 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1065 dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1066 1067 dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal); 1068 dml_print("DML_DLG: %s: pixel_rate_delay_subtotal = %d\n", 1069 __func__, 1070 pixel_rate_delay_subtotal); 1071 dml_print("DML_DLG: %s: dst_x_after_scaler = %d\n", 1072 __func__, 1073 dst_x_after_scaler); 1074 dml_print("DML_DLG: %s: dst_y_after_scaler = %d\n", 1075 __func__, 1076 dst_y_after_scaler); 1077 1078 // Lwait 1079 line_wait = mode_lib->soc.urgent_latency_us; 1080 if (cstate_en) 1081 line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait); 1082 if (pstate_en) 1083 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us 1084 + mode_lib->soc.urgent_latency_us, 1085 line_wait); 1086 line_wait = line_wait / line_time_in_us; 1087 1088 dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1089 dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch); 1090 1091 dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib, 1092 e2e_pipe_param, 1093 num_pipes, 1094 pipe_idx); 1095 dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib, 1096 e2e_pipe_param, 1097 num_pipes, 1098 pipe_idx); 1099 dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1100 dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1101 1102 min_dst_y_per_vm_vblank = 8.0; 1103 min_dst_y_per_row_vblank = 16.0; 1104 1105 // magic! 1106 if (htotal <= 75) { 1107 min_vblank = 300; 1108 min_dst_y_per_vm_vblank = 100.0; 1109 min_dst_y_per_row_vblank = 100.0; 1110 } 1111 1112 dml_print("DML_DLG: %s: dst_y_per_vm_vblank = %3.2f\n", __func__, dst_y_per_vm_vblank); 1113 dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank); 1114 1115 ASSERT(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank); 1116 ASSERT(dst_y_per_row_vblank < min_dst_y_per_row_vblank); 1117 1118 ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank)); 1119 lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank); 1120 1121 dml_print("DML_DLG: %s: lsw = %3.2f\n", __func__, lsw); 1122 1123 vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1124 vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1125 1126 dml_print("DML_DLG: %s: vratio_pre_l=%3.2f\n", __func__, vratio_pre_l); 1127 dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c); 1128 1129 // Active 1130 req_per_swath_ub_l = rq_dlg_param->rq_l.req_per_swath_ub; 1131 req_per_swath_ub_c = rq_dlg_param->rq_c.req_per_swath_ub; 1132 meta_row_height_l = rq_dlg_param->rq_l.meta_row_height; 1133 meta_row_height_c = rq_dlg_param->rq_c.meta_row_height; 1134 swath_width_pixels_ub_l = 0; 1135 swath_width_pixels_ub_c = 0; 1136 scaler_rec_in_width_l = 0; 1137 scaler_rec_in_width_c = 0; 1138 dpte_row_height_l = rq_dlg_param->rq_l.dpte_row_height; 1139 dpte_row_height_c = rq_dlg_param->rq_c.dpte_row_height; 1140 1141 swath_width_pixels_ub_l = swath_width_ub_l; 1142 swath_width_pixels_ub_c = swath_width_ub_c; 1143 1144 if (htaps_l <= 1) 1145 min_hratio_fact_l = 2.0; 1146 else if (htaps_l <= 6) { 1147 if ((hratio_l * 2.0) > 4.0) 1148 min_hratio_fact_l = 4.0; 1149 else 1150 min_hratio_fact_l = hratio_l * 2.0; 1151 } else { 1152 if (hratio_l > 4.0) 1153 min_hratio_fact_l = 4.0; 1154 else 1155 min_hratio_fact_l = hratio_l; 1156 } 1157 1158 hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz; 1159 1160 if (htaps_c <= 1) 1161 min_hratio_fact_c = 2.0; 1162 else if (htaps_c <= 6) { 1163 if ((hratio_c * 2.0) > 4.0) 1164 min_hratio_fact_c = 4.0; 1165 else 1166 min_hratio_fact_c = hratio_c * 2.0; 1167 } else { 1168 if (hratio_c > 4.0) 1169 min_hratio_fact_c = 4.0; 1170 else 1171 min_hratio_fact_c = hratio_c; 1172 } 1173 1174 hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz; 1175 1176 refcyc_per_line_delivery_pre_l = 0.; 1177 refcyc_per_line_delivery_pre_c = 0.; 1178 refcyc_per_line_delivery_l = 0.; 1179 refcyc_per_line_delivery_c = 0.; 1180 1181 refcyc_per_req_delivery_pre_l = 0.; 1182 refcyc_per_req_delivery_pre_c = 0.; 1183 refcyc_per_req_delivery_l = 0.; 1184 refcyc_per_req_delivery_c = 0.; 1185 1186 full_recout_width = 0; 1187 // In ODM 1188 if (src->is_hsplit) { 1189 // This "hack" is only allowed (and valid) for MPC combine. In ODM 1190 // combine, you MUST specify the full_recout_width...according to Oswin 1191 if (dst->full_recout_width == 0 && !dst->odm_combine) { 1192 dml_print("DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n", 1193 __func__); 1194 full_recout_width = dst->recout_width * 2; // assume half split for dcn1 1195 } else 1196 full_recout_width = dst->full_recout_width; 1197 } else 1198 full_recout_width = dst->recout_width; 1199 1200 // As of DCN2, mpc_combine and odm_combine are mutually exclusive 1201 refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(mode_lib, 1202 refclk_freq_in_mhz, 1203 pclk_freq_in_mhz, 1204 dst->odm_combine, 1205 full_recout_width, 1206 dst->hactive, 1207 vratio_pre_l, 1208 hscale_pixel_rate_l, 1209 swath_width_pixels_ub_l, 1210 1); // per line 1211 1212 refcyc_per_line_delivery_l = get_refcyc_per_delivery(mode_lib, 1213 refclk_freq_in_mhz, 1214 pclk_freq_in_mhz, 1215 dst->odm_combine, 1216 full_recout_width, 1217 dst->hactive, 1218 vratio_l, 1219 hscale_pixel_rate_l, 1220 swath_width_pixels_ub_l, 1221 1); // per line 1222 1223 dml_print("DML_DLG: %s: full_recout_width = %d\n", 1224 __func__, 1225 full_recout_width); 1226 dml_print("DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n", 1227 __func__, 1228 hscale_pixel_rate_l); 1229 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n", 1230 __func__, 1231 refcyc_per_line_delivery_pre_l); 1232 dml_print("DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f\n", 1233 __func__, 1234 refcyc_per_line_delivery_l); 1235 1236 if (dual_plane) { 1237 refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(mode_lib, 1238 refclk_freq_in_mhz, 1239 pclk_freq_in_mhz, 1240 dst->odm_combine, 1241 full_recout_width, 1242 dst->hactive, 1243 vratio_pre_c, 1244 hscale_pixel_rate_c, 1245 swath_width_pixels_ub_c, 1246 1); // per line 1247 1248 refcyc_per_line_delivery_c = get_refcyc_per_delivery(mode_lib, 1249 refclk_freq_in_mhz, 1250 pclk_freq_in_mhz, 1251 dst->odm_combine, 1252 full_recout_width, 1253 dst->hactive, 1254 vratio_c, 1255 hscale_pixel_rate_c, 1256 swath_width_pixels_ub_c, 1257 1); // per line 1258 1259 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n", 1260 __func__, 1261 refcyc_per_line_delivery_pre_c); 1262 dml_print("DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f\n", 1263 __func__, 1264 refcyc_per_line_delivery_c); 1265 } 1266 1267 // TTU - Luma / Chroma 1268 if (access_dir) { // vertical access 1269 scaler_rec_in_width_l = vp_height_l; 1270 scaler_rec_in_width_c = vp_height_c; 1271 } else { 1272 scaler_rec_in_width_l = vp_width_l; 1273 scaler_rec_in_width_c = vp_width_c; 1274 } 1275 1276 refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(mode_lib, 1277 refclk_freq_in_mhz, 1278 pclk_freq_in_mhz, 1279 dst->odm_combine, 1280 full_recout_width, 1281 dst->hactive, 1282 vratio_pre_l, 1283 hscale_pixel_rate_l, 1284 scaler_rec_in_width_l, 1285 req_per_swath_ub_l); // per req 1286 refcyc_per_req_delivery_l = get_refcyc_per_delivery(mode_lib, 1287 refclk_freq_in_mhz, 1288 pclk_freq_in_mhz, 1289 dst->odm_combine, 1290 full_recout_width, 1291 dst->hactive, 1292 vratio_l, 1293 hscale_pixel_rate_l, 1294 scaler_rec_in_width_l, 1295 req_per_swath_ub_l); // per req 1296 1297 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n", 1298 __func__, 1299 refcyc_per_req_delivery_pre_l); 1300 dml_print("DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f\n", 1301 __func__, 1302 refcyc_per_req_delivery_l); 1303 1304 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); 1305 ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); 1306 1307 if (dual_plane) { 1308 refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(mode_lib, 1309 refclk_freq_in_mhz, 1310 pclk_freq_in_mhz, 1311 dst->odm_combine, 1312 full_recout_width, 1313 dst->hactive, 1314 vratio_pre_c, 1315 hscale_pixel_rate_c, 1316 scaler_rec_in_width_c, 1317 req_per_swath_ub_c); // per req 1318 refcyc_per_req_delivery_c = get_refcyc_per_delivery(mode_lib, 1319 refclk_freq_in_mhz, 1320 pclk_freq_in_mhz, 1321 dst->odm_combine, 1322 full_recout_width, 1323 dst->hactive, 1324 vratio_c, 1325 hscale_pixel_rate_c, 1326 scaler_rec_in_width_c, 1327 req_per_swath_ub_c); // per req 1328 1329 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n", 1330 __func__, 1331 refcyc_per_req_delivery_pre_c); 1332 dml_print("DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f\n", 1333 __func__, 1334 refcyc_per_req_delivery_c); 1335 1336 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); 1337 ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); 1338 } 1339 1340 // TTU - Cursor 1341 refcyc_per_req_delivery_pre_cur0 = 0.0; 1342 refcyc_per_req_delivery_cur0 = 0.0; 1343 if (src->num_cursors > 0) { 1344 calculate_ttu_cursor(mode_lib, 1345 &refcyc_per_req_delivery_pre_cur0, 1346 &refcyc_per_req_delivery_cur0, 1347 refclk_freq_in_mhz, 1348 ref_freq_to_pix_freq, 1349 hscale_pixel_rate_l, 1350 scl->hscl_ratio, 1351 vratio_pre_l, 1352 vratio_l, 1353 src->cur0_src_width, 1354 (enum cursor_bpp)(src->cur0_bpp)); 1355 } 1356 1357 refcyc_per_req_delivery_pre_cur1 = 0.0; 1358 refcyc_per_req_delivery_cur1 = 0.0; 1359 if (src->num_cursors > 1) { 1360 calculate_ttu_cursor(mode_lib, 1361 &refcyc_per_req_delivery_pre_cur1, 1362 &refcyc_per_req_delivery_cur1, 1363 refclk_freq_in_mhz, 1364 ref_freq_to_pix_freq, 1365 hscale_pixel_rate_l, 1366 scl->hscl_ratio, 1367 vratio_pre_l, 1368 vratio_l, 1369 src->cur1_src_width, 1370 (enum cursor_bpp)(src->cur1_bpp)); 1371 } 1372 1373 // TTU - Misc 1374 // all hard-coded 1375 1376 // Assignment to register structures 1377 disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line 1378 disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk 1379 ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13)); 1380 disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); 1381 disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); 1382 disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); 1383 disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); 1384 disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2)); 1385 1386 disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); 1387 disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); 1388 1389 disp_dlg_regs->refcyc_per_pte_group_vblank_l = 1390 (unsigned int) (dst_y_per_row_vblank * (double) htotal 1391 * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); 1392 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13)); 1393 1394 if (dual_plane) { 1395 disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank 1396 * (double) htotal * ref_freq_to_pix_freq 1397 / (double) dpte_groups_per_row_ub_c); 1398 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c 1399 < (unsigned int) dml_pow(2, 13)); 1400 } 1401 1402 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = 1403 (unsigned int) (dst_y_per_row_vblank * (double) htotal 1404 * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); 1405 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); 1406 1407 disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = 1408 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now 1409 1410 disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal 1411 * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l; 1412 disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal 1413 * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l; 1414 1415 if (dual_plane) { 1416 disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip 1417 * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c; 1418 disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip 1419 * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; 1420 } 1421 1422 disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l 1423 / (double) vratio_l * dml_pow(2, 2)); 1424 ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17)); 1425 1426 if (dual_plane) { 1427 disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c 1428 / (double) vratio_c * dml_pow(2, 2)); 1429 if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) { 1430 dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n", 1431 __func__, 1432 disp_dlg_regs->dst_y_per_pte_row_nom_c, 1433 (unsigned int) dml_pow(2, 17) - 1); 1434 } 1435 } 1436 1437 disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l 1438 / (double) vratio_l * dml_pow(2, 2)); 1439 ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17)); 1440 1441 disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now 1442 1443 disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l 1444 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq 1445 / (double) dpte_groups_per_row_ub_l); 1446 if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) 1447 disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; 1448 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l 1449 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq 1450 / (double) meta_chunks_per_row_ub_l); 1451 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) 1452 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; 1453 1454 if (dual_plane) { 1455 disp_dlg_regs->refcyc_per_pte_group_nom_c = 1456 (unsigned int) ((double) dpte_row_height_c / (double) vratio_c 1457 * (double) htotal * ref_freq_to_pix_freq 1458 / (double) dpte_groups_per_row_ub_c); 1459 if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) 1460 disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; 1461 1462 // TODO: Is this the right calculation? Does htotal need to be halved? 1463 disp_dlg_regs->refcyc_per_meta_chunk_nom_c = 1464 (unsigned int) ((double) meta_row_height_c / (double) vratio_c 1465 * (double) htotal * ref_freq_to_pix_freq 1466 / (double) meta_chunks_per_row_ub_c); 1467 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) 1468 disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; 1469 } 1470 1471 disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, 1472 1); 1473 disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l, 1474 1); 1475 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13)); 1476 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13)); 1477 1478 disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c, 1479 1); 1480 disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c, 1481 1); 1482 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13)); 1483 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13)); 1484 1485 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; 1486 disp_dlg_regs->dst_y_offset_cur0 = 0; 1487 disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; 1488 disp_dlg_regs->dst_y_offset_cur1 = 0; 1489 1490 disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off 1491 1492 disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l 1493 * dml_pow(2, 10)); 1494 disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l 1495 * dml_pow(2, 10)); 1496 disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c 1497 * dml_pow(2, 10)); 1498 disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c 1499 * dml_pow(2, 10)); 1500 disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = 1501 (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); 1502 disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 1503 * dml_pow(2, 10)); 1504 disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = 1505 (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); 1506 disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 1507 * dml_pow(2, 10)); 1508 disp_ttu_regs->qos_level_low_wm = 0; 1509 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); 1510 disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal 1511 * ref_freq_to_pix_freq); 1512 /*ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));*/ 1513 1514 disp_ttu_regs->qos_level_flip = 14; 1515 disp_ttu_regs->qos_level_fixed_l = 8; 1516 disp_ttu_regs->qos_level_fixed_c = 8; 1517 disp_ttu_regs->qos_level_fixed_cur0 = 8; 1518 disp_ttu_regs->qos_ramp_disable_l = 0; 1519 disp_ttu_regs->qos_ramp_disable_c = 0; 1520 disp_ttu_regs->qos_ramp_disable_cur0 = 0; 1521 1522 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; 1523 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); 1524 1525 print__ttu_regs_st(mode_lib, disp_ttu_regs); 1526 print__dlg_regs_st(mode_lib, disp_dlg_regs); 1527} 1528 1529void dml20_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, 1530 display_dlg_regs_st *dlg_regs, 1531 display_ttu_regs_st *ttu_regs, 1532 const display_e2e_pipe_params_st *e2e_pipe_param, 1533 const unsigned int num_pipes, 1534 const unsigned int pipe_idx, 1535 const bool cstate_en, 1536 const bool pstate_en, 1537 const bool vm_en, 1538 const bool ignore_viewport_pos, 1539 const bool immediate_flip_support) 1540{ 1541 display_rq_params_st rq_param = {0}; 1542 display_dlg_sys_params_st dlg_sys_param = {0}; 1543 1544 // Get watermark and Tex. 1545 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); 1546 dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib, 1547 e2e_pipe_param, 1548 num_pipes); 1549 dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes); 1550 dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes); 1551 dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes); 1552 dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes); 1553 dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, 1554 e2e_pipe_param, 1555 num_pipes); 1556 dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, 1557 e2e_pipe_param, 1558 num_pipes); 1559 1560 print__dlg_sys_params_st(mode_lib, &dlg_sys_param); 1561 1562 // system parameter calculation done 1563 1564 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); 1565 dml20_rq_dlg_get_rq_params(mode_lib, &rq_param, &e2e_pipe_param[pipe_idx].pipe.src); 1566 dml20_rq_dlg_get_dlg_params(mode_lib, 1567 e2e_pipe_param, 1568 num_pipes, 1569 pipe_idx, 1570 dlg_regs, 1571 ttu_regs, 1572 &rq_param.dlg, 1573 &dlg_sys_param, 1574 cstate_en, 1575 pstate_en); 1576 dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx); 1577} 1578 1579static void calculate_ttu_cursor(struct display_mode_lib *mode_lib, 1580 double *refcyc_per_req_delivery_pre_cur, 1581 double *refcyc_per_req_delivery_cur, 1582 double refclk_freq_in_mhz, 1583 double ref_freq_to_pix_freq, 1584 double hscale_pixel_rate_l, 1585 double hscl_ratio, 1586 double vratio_pre_l, 1587 double vratio_l, 1588 unsigned int cur_width, 1589 enum cursor_bpp cur_bpp) 1590{ 1591 unsigned int cur_src_width = cur_width; 1592 unsigned int cur_req_size = 0; 1593 unsigned int cur_req_width = 0; 1594 double cur_width_ub = 0.0; 1595 double cur_req_per_width = 0.0; 1596 double hactive_cur = 0.0; 1597 1598 ASSERT(cur_src_width <= 256); 1599 1600 *refcyc_per_req_delivery_pre_cur = 0.0; 1601 *refcyc_per_req_delivery_cur = 0.0; 1602 if (cur_src_width > 0) { 1603 unsigned int cur_bit_per_pixel = 0; 1604 1605 if (cur_bpp == dm_cur_2bit) { 1606 cur_req_size = 64; // byte 1607 cur_bit_per_pixel = 2; 1608 } else { // 32bit 1609 cur_bit_per_pixel = 32; 1610 if (cur_src_width >= 1 && cur_src_width <= 16) 1611 cur_req_size = 64; 1612 else if (cur_src_width >= 17 && cur_src_width <= 31) 1613 cur_req_size = 128; 1614 else 1615 cur_req_size = 256; 1616 } 1617 1618 cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0); 1619 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) 1620 * (double) cur_req_width; 1621 cur_req_per_width = cur_width_ub / (double) cur_req_width; 1622 hactive_cur = (double) cur_src_width / hscl_ratio; // TODO: oswin to think about what to do for cursor 1623 1624 if (vratio_pre_l <= 1.0) { 1625 *refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq 1626 / (double) cur_req_per_width; 1627 } else { 1628 *refcyc_per_req_delivery_pre_cur = (double) refclk_freq_in_mhz 1629 * (double) cur_src_width / hscale_pixel_rate_l 1630 / (double) cur_req_per_width; 1631 } 1632 1633 ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13)); 1634 1635 if (vratio_l <= 1.0) { 1636 *refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq 1637 / (double) cur_req_per_width; 1638 } else { 1639 *refcyc_per_req_delivery_cur = (double) refclk_freq_in_mhz 1640 * (double) cur_src_width / hscale_pixel_rate_l 1641 / (double) cur_req_per_width; 1642 } 1643 1644 dml_print("DML_DLG: %s: cur_req_width = %d\n", 1645 __func__, 1646 cur_req_width); 1647 dml_print("DML_DLG: %s: cur_width_ub = %3.2f\n", 1648 __func__, 1649 cur_width_ub); 1650 dml_print("DML_DLG: %s: cur_req_per_width = %3.2f\n", 1651 __func__, 1652 cur_req_per_width); 1653 dml_print("DML_DLG: %s: hactive_cur = %3.2f\n", 1654 __func__, 1655 hactive_cur); 1656 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur = %3.2f\n", 1657 __func__, 1658 *refcyc_per_req_delivery_pre_cur); 1659 dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur = %3.2f\n", 1660 __func__, 1661 *refcyc_per_req_delivery_cur); 1662 1663 ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13)); 1664 } 1665}
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