dcn401_dio_stream_encoder.c

  1/*
  2 * Copyright 2021 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 *  and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26
 27#include "dc_bios_types.h"
 28#include "dcn30/dcn30_dio_stream_encoder.h"
 29#include "dcn32/dcn32_dio_stream_encoder.h"
 30#include "dcn35/dcn35_dio_stream_encoder.h"
 31
 32#include "dcn401_dio_stream_encoder.h"
 33#include "reg_helper.h"
 34#include "hw_shared.h"
 35#include "link_service.h"
 36#include "dpcd_defs.h"
 37
 38#define DC_LOGGER \
 39		enc1->base.ctx->logger
 40
 41#define REG(reg)\
 42	(enc1->regs->reg)
 43
 44#undef FN
 45#define FN(reg_name, field_name) \
 46	enc1->se_shift->field_name, enc1->se_mask->field_name
 47
 48#define VBI_LINE_0 0
 49#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
 50
 51#define CTX \
 52	enc1->base.ctx
 53
 54
 55
 56static void enc401_dp_set_odm_combine(
 57	struct stream_encoder *enc,
 58	bool odm_combine)
 59{
 60}
 61
 62/* setup stream encoder in dvi mode */
 63void enc401_stream_encoder_dvi_set_stream_attribute(
 64	struct stream_encoder *enc,
 65	struct dc_crtc_timing *crtc_timing,
 66	bool is_dual_link)
 67{
 68	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 69
 70	if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
 71		struct bp_encoder_control cntl = {0};
 72
 73		cntl.action = ENCODER_CONTROL_SETUP;
 74		cntl.engine_id = enc1->base.id;
 75		cntl.signal = is_dual_link ?
 76			SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
 77		cntl.enable_dp_audio = false;
 78		cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
 79		cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
 80
 81		if (enc1->base.bp->funcs->encoder_control(
 82				enc1->base.bp, &cntl) != BP_RESULT_OK)
 83			return;
 84
 85	} else {
 86
 87		//Set pattern for clock channel, default vlue 0x63 does not work
 88		REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
 89
 90		//DIG_BE_TMDS_DVI_MODE : TMDS-DVI mode is already set in link_encoder_setup
 91
 92		//DIG_SOURCE_SELECT is already set in dig_connect_to_otg
 93
 94		/* DIG_START is removed from the register spec */
 95	}
 96
 97	ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
 98	ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
 99	enc401_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
100}
101
102/* setup stream encoder in hdmi mode */
103void enc401_stream_encoder_hdmi_set_stream_attribute(
104	struct stream_encoder *enc,
105	struct dc_crtc_timing *crtc_timing,
106	int actual_pix_clk_khz,
107	bool enable_audio)
108{
109	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
110
111	if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
112		struct bp_encoder_control cntl = {0};
113
114		cntl.action = ENCODER_CONTROL_SETUP;
115		cntl.engine_id = enc1->base.id;
116		cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
117		cntl.enable_dp_audio = enable_audio;
118		cntl.pixel_clock = actual_pix_clk_khz;
119		cntl.lanes_number = LANE_COUNT_FOUR;
120
121		if (enc1->base.bp->funcs->encoder_control(
122				enc1->base.bp, &cntl) != BP_RESULT_OK)
123			return;
124
125	} else {
126
127		//Set pattern for clock channel, default vlue 0x63 does not work
128		REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
129
130		//DIG_BE_TMDS_HDMI_MODE : TMDS-HDMI mode is already set in link_encoder_setup
131
132		//DIG_SOURCE_SELECT is already set in dig_connect_to_otg
133
134		/* DIG_START is removed from the register spec */
135	}
136
137	/* Configure pixel encoding */
138	enc401_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
139
140	/* setup HDMI engine */
141	REG_UPDATE_6(HDMI_CONTROL,
142		HDMI_PACKET_GEN_VERSION, 1,
143		HDMI_KEEPOUT_MODE, 1,
144		HDMI_DEEP_COLOR_ENABLE, 0,
145		HDMI_DATA_SCRAMBLE_EN, 0,
146		HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1,
147		HDMI_CLOCK_CHANNEL_RATE, 0);
148
149	/* Configure color depth */
150	switch (crtc_timing->display_color_depth) {
151	case COLOR_DEPTH_888:
152		REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
153		break;
154	case COLOR_DEPTH_101010:
155		if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
156			REG_UPDATE_2(HDMI_CONTROL,
157					HDMI_DEEP_COLOR_DEPTH, 1,
158					HDMI_DEEP_COLOR_ENABLE, 0);
159		} else {
160			REG_UPDATE_2(HDMI_CONTROL,
161					HDMI_DEEP_COLOR_DEPTH, 1,
162					HDMI_DEEP_COLOR_ENABLE, 1);
163			}
164		break;
165	case COLOR_DEPTH_121212:
166		if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
167			REG_UPDATE_2(HDMI_CONTROL,
168					HDMI_DEEP_COLOR_DEPTH, 2,
169					HDMI_DEEP_COLOR_ENABLE, 0);
170		} else {
171			REG_UPDATE_2(HDMI_CONTROL,
172					HDMI_DEEP_COLOR_DEPTH, 2,
173					HDMI_DEEP_COLOR_ENABLE, 1);
174			}
175		break;
176	case COLOR_DEPTH_161616:
177		REG_UPDATE_2(HDMI_CONTROL,
178				HDMI_DEEP_COLOR_DEPTH, 3,
179				HDMI_DEEP_COLOR_ENABLE, 1);
180		break;
181	default:
182		break;
183	}
184
185	if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
186		/* enable HDMI data scrambler
187		 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
188		 * Clock channel frequency is 1/4 of character rate.
189		 */
190		REG_UPDATE_2(HDMI_CONTROL,
191			HDMI_DATA_SCRAMBLE_EN, 1,
192			HDMI_CLOCK_CHANNEL_RATE, 1);
193	} else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
194
195		/* TODO: New feature for DCE11, still need to implement */
196
197		/* enable HDMI data scrambler
198		 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
199		 * Clock channel frequency is the same
200		 * as character rate
201		 */
202		REG_UPDATE_2(HDMI_CONTROL,
203			HDMI_DATA_SCRAMBLE_EN, 1,
204			HDMI_CLOCK_CHANNEL_RATE, 0);
205	}
206
207
208	/* Enable transmission of General Control packet on every frame */
209	REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
210		HDMI_GC_CONT, 1,
211		HDMI_GC_SEND, 1,
212		HDMI_NULL_SEND, 1);
213
214	/* Disable Audio Content Protection packet transmission */
215	REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);
216	/* following belongs to audio */
217	/* Enable Audio InfoFrame packet transmission. */
218	REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
219
220	/* update double-buffered AUDIO_INFO registers immediately */
221	ASSERT(enc->afmt);
222	enc->afmt->funcs->audio_info_immediate_update(enc->afmt);
223
224	/* Select line number on which to send Audio InfoFrame packets */
225	REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
226				VBI_LINE_0 + 2);
227
228	/* set HDMI GC AVMUTE */
229	REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
230}
231
232void enc401_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container)
233{
234	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
235
236	// The naming of this field is confusing, what it means is the output mode of otg, which
237	// is the input mode of the dig
238	switch (pix_per_container)	{
239	case 2:
240		REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x1);
241		break;
242	case 4:
243		REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x2);
244		break;
245	case 8:
246		REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x3);
247		break;
248	default:
249		REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x0);
250		break;
251	}
252}
253
254static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
255{
256	bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
257
258	two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
259			&& !timing->dsc_cfg.ycbcr422_simple);
260	return two_pix;
261}
262
263void enc401_stream_encoder_dp_unblank(
264		struct dc_link *link,
265		struct stream_encoder *enc,
266		const struct encoder_unblank_param *param)
267{
268	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
269
270	if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
271		uint32_t n_vid = 0x8000;
272		uint32_t m_vid;
273		uint32_t pix_per_container = 1;
274		uint64_t m_vid_l = n_vid;
275
276		/* YCbCr 4:2:0 or YCbCr4:2:2 simple + DSC: Computed VID_M will be 2X the input rate */
277		if (is_two_pixels_per_containter(&param->timing)) {
278			pix_per_container = 2;
279		}
280
281		/* M / N = Fstream / Flink
282		 * m_vid / n_vid = pixel rate / link rate
283		 */
284		m_vid_l *= param->timing.pix_clk_100hz / pix_per_container / 10;
285		m_vid_l = div_u64(m_vid_l,
286			param->link_settings.link_rate
287				* LINK_RATE_REF_FREQ_IN_KHZ);
288
289		m_vid = (uint32_t) m_vid_l;
290
291		/* enable auto measurement */
292
293		REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
294
295		/* auto measurement need 1 full 0x8000 symbol cycle to kick in,
296		 * therefore program initial value for Mvid and Nvid
297		 */
298
299		REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
300
301		REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
302
303		/* reduce jitter based on read rate */
304		switch (param->pix_per_cycle)	{
305		case 2:
306			REG_UPDATE(DP_VID_TIMING, DP_VID_N_INTERVAL, 0x1);
307			break;
308		case 4:
309			REG_UPDATE(DP_VID_TIMING, DP_VID_N_INTERVAL, 0x2);
310			break;
311		case 8:
312			REG_UPDATE(DP_VID_TIMING, DP_VID_N_INTERVAL, 0x3);
313			break;
314		default:
315			REG_UPDATE(DP_VID_TIMING, DP_VID_N_INTERVAL, 0x0);
316			break;
317		}
318
319		REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
320	}
321
322	/* make sure stream is disabled before resetting steer fifo */
323	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);
324	REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000);
325
326	/* DIG_START is removed from the register spec */
327
328	/* switch DP encoder to CRTC data, but reset it the fifo first. It may happen
329	 * that it overflows during mode transition, and sometimes doesn't recover.
330	 */
331	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1);
332	udelay(10);
333
334	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
335
336	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_ENABLE, 1);
337
338	REG_UPDATE_2(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 1, DP_VID_STREAM_DIS_DEFER, 2);
339	udelay(200);
340
341	/* DIG Resync FIFO now needs to be explicitly enabled
342	 */
343	/* read start level = 0 will bring underflow / overflow and DIG_FIFO_ERROR = 1
344	 * so set it to 1/2 full = 7 before reset as suggested by hardware team.
345	 */
346	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7);
347
348	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1);
349
350	REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000);
351
352	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 0);
353
354	REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 10, 5000);
355
356	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1);
357
358	/* wait 100us for DIG/DP logic to prime
359	 * (i.e. a few video lines)
360	 */
361	udelay(100);
362
363	/* the hardware would start sending video at the start of the next DP
364	 * frame (i.e. rising edge of the vblank).
365	 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
366	 * register has no effect on enable transition! HW always guarantees
367	 * VID_STREAM enable at start of next frame, and this is not
368	 * programmable
369	 */
370
371	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
372
373	link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);
374}
375
376/* this function read dsc related register fields to be logged later in dcn10_log_hw_state
377 * into a dcn_dsc_state struct.
378 */
379void enc401_read_state(struct stream_encoder *enc, struct enc_state *s)
380{
381	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
382
383	//if dsc is enabled, continue to read
384	REG_GET(DP_PIXEL_FORMAT, PIXEL_ENCODING_TYPE, &s->dsc_mode);
385
386	if (s->dsc_mode) {
387		REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num);
388
389		REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference);
390		REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num);
391
392		REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable);
393		REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
394	}
395}
396
397void enc401_stream_encoder_enable(
398	struct stream_encoder *enc,
399	enum signal_type signal,
400	bool enable)
401{
402	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
403	if (enable) {
404		switch (signal) {
405		case SIGNAL_TYPE_DVI_SINGLE_LINK:
406		case SIGNAL_TYPE_DVI_DUAL_LINK:
407			/* TMDS-DVI */
408			REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_MODE, 2);
409			break;
410		case SIGNAL_TYPE_HDMI_TYPE_A:
411			/* TMDS-HDMI */
412			REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_MODE, 3);
413			break;
414		case SIGNAL_TYPE_DISPLAY_PORT_MST:
415			/* DP MST */
416			REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_MODE, 5);
417			break;
418		case SIGNAL_TYPE_EDP:
419		case SIGNAL_TYPE_DISPLAY_PORT:
420		case SIGNAL_TYPE_VIRTUAL:
421			/* DP SST */
422			REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_MODE, 0);
423			break;
424		default:
425			/* invalid mode ! */
426			ASSERT_CRITICAL(false);
427		}
428
429		REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_CLK_EN, 1);
430		REG_UPDATE(DIG_FE_EN_CNTL, DIG_FE_ENABLE, 1);
431	} else {
432		REG_UPDATE(DIG_FE_EN_CNTL, DIG_FE_ENABLE, 0);
433		REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_CLK_EN, 0);
434	}
435}
436
437void enc401_stream_encoder_dp_set_stream_attribute(
438	struct stream_encoder *enc,
439	struct dc_crtc_timing *crtc_timing,
440	enum dc_color_space output_color_space,
441	bool use_vsc_sdp_for_colorimetry,
442	uint32_t enable_sdp_splitting)
443{
444	uint32_t h_active_start;
445	uint32_t v_active_start;
446	uint32_t misc0 = 0;
447	uint32_t misc1 = 0;
448	uint32_t h_blank;
449	uint32_t h_back_porch;
450	uint8_t colorimetry_bpc;
451	uint8_t dp_pixel_encoding = 0;
452	uint8_t dp_component_depth = 0;
453	uint8_t dp_translate_pixel_enc = 0;
454	// Fix set but not used warnings
455	//uint8_t dp_pixel_encoding_type = 0;
456	uint8_t dp_compressed_pixel_format = 0;
457
458	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
459	struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
460
461	if (hw_crtc_timing.flags.INTERLACE) {
462		/*the input timing is in VESA spec format with Interlace flag =1*/
463		hw_crtc_timing.v_total /= 2;
464		hw_crtc_timing.v_border_top /= 2;
465		hw_crtc_timing.v_addressable /= 2;
466		hw_crtc_timing.v_border_bottom /= 2;
467		hw_crtc_timing.v_front_porch /= 2;
468		hw_crtc_timing.v_sync_width /= 2;
469	}
470
471
472	/* set pixel encoding */
473	switch (hw_crtc_timing.pixel_encoding) {
474	case PIXEL_ENCODING_YCBCR422:
475		dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR422;
476		break;
477	case PIXEL_ENCODING_YCBCR444:
478		dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR444;
479
480		if (hw_crtc_timing.flags.Y_ONLY)
481			if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)
482				/* HW testing only, no use case yet.
483				 * Color depth of Y-only could be
484				 * 8, 10, 12, 16 bits
485				 */
486				dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_Y_ONLY;
487
488		/* Note: DP_MSA_MISC1 bit 7 is the indicator
489		 * of Y-only mode.
490		 * This bit is set in HW if register
491		 * DP_PIXEL_ENCODING is programmed to 0x4
492		 */
493		break;
494	case PIXEL_ENCODING_YCBCR420:
495		dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420;
496		break;
497	default:
498		dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444;
499		break;
500	}
501
502	misc1 = REG_READ(DP_MSA_MISC);
503	/* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used.
504	 * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the
505	 * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7,
506	 * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care").
507	 */
508	if (use_vsc_sdp_for_colorimetry)
509		misc1 = misc1 | 0x40;
510	else
511		misc1 = misc1 & ~0x40;
512
513	/* set color depth */
514	switch (hw_crtc_timing.display_color_depth) {
515	case COLOR_DEPTH_666:
516		dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
517		break;
518	case COLOR_DEPTH_888:
519		dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_8BPC;
520		break;
521	case COLOR_DEPTH_101010:
522		dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_10BPC;
523		break;
524	case COLOR_DEPTH_121212:
525		dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_12BPC;
526		break;
527	case COLOR_DEPTH_161616:
528		dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_16BPC;
529		break;
530	default:
531		dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
532		break;
533	}
534
535	if (hw_crtc_timing.flags.DSC) {
536		// Fix set but not used error
537		//dp_pixel_encoding_type = 1;
538		switch (hw_crtc_timing.pixel_encoding) {
539		case PIXEL_ENCODING_YCBCR444:
540			dp_compressed_pixel_format = 0;
541			break;
542		case PIXEL_ENCODING_YCBCR422:
543			dp_compressed_pixel_format = 1;
544			if (hw_crtc_timing.dsc_cfg.ycbcr422_simple)
545				dp_compressed_pixel_format = 0;
546			break;
547		case PIXEL_ENCODING_YCBCR420:
548			dp_compressed_pixel_format = 1;
549			break;
550		default:
551			dp_compressed_pixel_format = 0;
552			break;
553		}
554	} else {
555		// Fix set but not used error
556		//dp_pixel_encoding_type = 0;
557		switch (dp_pixel_encoding) {
558		case DP_PIXEL_ENCODING_TYPE_RGB444:
559			dp_translate_pixel_enc = 0;
560			break;
561		case DP_PIXEL_ENCODING_TYPE_YCBCR422:
562			dp_translate_pixel_enc = 1;
563			break;
564		case DP_PIXEL_ENCODING_TYPE_YCBCR444:
565			dp_translate_pixel_enc = 0;
566			break;
567		case DP_PIXEL_ENCODING_TYPE_Y_ONLY:
568			dp_translate_pixel_enc = 3;
569			break;
570		case DP_PIXEL_ENCODING_TYPE_YCBCR420:
571			dp_translate_pixel_enc = 2;
572			break;
573		default:
574			ASSERT(0);
575			break;
576		}
577	}
578	/* Set DP pixel encoding and component depth */
579	REG_UPDATE_4(DP_PIXEL_FORMAT,
580			PIXEL_ENCODING_TYPE, hw_crtc_timing.flags.DSC ? 1 : 0,
581			UNCOMPRESSED_PIXEL_FORMAT, dp_translate_pixel_enc,
582			UNCOMPRESSED_COMPONENT_DEPTH, dp_component_depth,
583			COMPRESSED_PIXEL_FORMAT, dp_compressed_pixel_format);
584
585	/* set dynamic range and YCbCr range */
586
587	switch (hw_crtc_timing.display_color_depth) {
588	case COLOR_DEPTH_666:
589		colorimetry_bpc = 0;
590		break;
591	case COLOR_DEPTH_888:
592		colorimetry_bpc = 1;
593		break;
594	case COLOR_DEPTH_101010:
595		colorimetry_bpc = 2;
596		break;
597	case COLOR_DEPTH_121212:
598		colorimetry_bpc = 3;
599		break;
600	default:
601		colorimetry_bpc = 0;
602		break;
603	}
604
605	misc0 = colorimetry_bpc << 5;
606
607	switch (output_color_space) {
608	case COLOR_SPACE_SRGB:
609		misc1 = misc1 & ~0x80; /* bit7 = 0*/
610		break;
611	case COLOR_SPACE_SRGB_LIMITED:
612		misc0 = misc0 | 0x8; /* bit3=1 */
613		misc1 = misc1 & ~0x80; /* bit7 = 0*/
614		break;
615	case COLOR_SPACE_YCBCR601:
616	case COLOR_SPACE_YCBCR601_LIMITED:
617		misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
618		misc1 = misc1 & ~0x80; /* bit7 = 0*/
619		if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
620			misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
621		else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
622			misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
623		break;
624	case COLOR_SPACE_YCBCR709:
625	case COLOR_SPACE_YCBCR709_LIMITED:
626		misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
627		misc1 = misc1 & ~0x80; /* bit7 = 0*/
628		if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
629			misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
630		else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
631			misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
632		break;
633	case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
634	case COLOR_SPACE_2020_RGB_FULLRANGE:
635	case COLOR_SPACE_2020_YCBCR_LIMITED:
636	case COLOR_SPACE_XR_RGB:
637	case COLOR_SPACE_MSREF_SCRGB:
638	case COLOR_SPACE_ADOBERGB:
639	case COLOR_SPACE_DCIP3:
640	case COLOR_SPACE_XV_YCC_709:
641	case COLOR_SPACE_XV_YCC_601:
642	case COLOR_SPACE_DISPLAYNATIVE:
643	case COLOR_SPACE_DOLBYVISION:
644	case COLOR_SPACE_APPCTRL:
645	case COLOR_SPACE_CUSTOMPOINTS:
646	case COLOR_SPACE_UNKNOWN:
647	case COLOR_SPACE_YCBCR709_BLACK:
648	default:
649		/* do nothing */
650		break;
651	}
652
653	REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
654	REG_WRITE(DP_MSA_MISC, misc1);   /* MSA_MISC1 */
655
656	/* dcn new register
657	 * dc_crtc_timing is vesa dmt struct. data from edid
658	 */
659	REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
660			DP_MSA_HTOTAL, hw_crtc_timing.h_total,
661			DP_MSA_VTOTAL, hw_crtc_timing.v_total);
662
663	/* calculate from vesa timing parameters
664	 * h_active_start related to leading edge of sync
665	 */
666
667	h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
668			hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
669
670	h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
671			hw_crtc_timing.h_sync_width;
672
673	/* start at beginning of left border */
674	h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
675
676
677	v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
678			hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
679			hw_crtc_timing.v_front_porch;
680
681
682	/* start at beginning of left border */
683	REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
684		DP_MSA_HSTART, h_active_start,
685		DP_MSA_VSTART, v_active_start);
686
687	REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
688			DP_MSA_HSYNCWIDTH,
689			hw_crtc_timing.h_sync_width,
690			DP_MSA_HSYNCPOLARITY,
691			!hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,
692			DP_MSA_VSYNCWIDTH,
693			hw_crtc_timing.v_sync_width,
694			DP_MSA_VSYNCPOLARITY,
695			!hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY);
696
697	/* HWDITH include border or overscan */
698	REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
699		DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +
700		hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
701		DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +
702		hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
703
704	REG_UPDATE(DP_SEC_FRAMING4,
705		DP_SST_SDP_SPLITTING, enable_sdp_splitting);
706}
707
708void enc401_stream_encoder_map_to_link(
709		struct stream_encoder *enc,
710		uint32_t stream_enc_inst,
711		uint32_t link_enc_inst)
712{
713	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
714
715	REG_UPDATE(STREAM_MAPPER_CONTROL,
716				DIG_STREAM_LINK_TARGET, link_enc_inst);
717}
718
719static const struct stream_encoder_funcs dcn401_str_enc_funcs = {
720	.dp_set_odm_combine =
721		enc401_dp_set_odm_combine,
722	.dp_set_stream_attribute =
723		enc401_stream_encoder_dp_set_stream_attribute,
724	.hdmi_set_stream_attribute =
725		enc401_stream_encoder_hdmi_set_stream_attribute,
726	.dvi_set_stream_attribute =
727		enc401_stream_encoder_dvi_set_stream_attribute,
728	.set_throttled_vcp_size =
729		enc1_stream_encoder_set_throttled_vcp_size,
730	.update_hdmi_info_packets =
731		enc3_stream_encoder_update_hdmi_info_packets,
732	.stop_hdmi_info_packets =
733		enc3_stream_encoder_stop_hdmi_info_packets,
734	.update_dp_info_packets_sdp_line_num =
735		enc3_stream_encoder_update_dp_info_packets_sdp_line_num,
736	.update_dp_info_packets =
737		enc3_stream_encoder_update_dp_info_packets,
738	.stop_dp_info_packets =
739		enc1_stream_encoder_stop_dp_info_packets,
740	.dp_blank =
741		enc1_stream_encoder_dp_blank,
742	.dp_unblank =
743		enc401_stream_encoder_dp_unblank,
744	.audio_mute_control = enc3_audio_mute_control,
745
746	.dp_audio_setup = enc3_se_dp_audio_setup,
747	.dp_audio_enable = enc3_se_dp_audio_enable,
748	.dp_audio_disable = enc1_se_dp_audio_disable,
749
750	.hdmi_audio_setup = enc3_se_hdmi_audio_setup,
751	.hdmi_audio_disable = enc1_se_hdmi_audio_disable,
752	.setup_stereo_sync  = enc1_setup_stereo_sync,
753	.set_avmute = enc1_stream_encoder_set_avmute,
754	.dig_connect_to_otg = enc1_dig_connect_to_otg,
755	.dig_source_otg = enc1_dig_source_otg,
756
757	.dp_get_pixel_format  = enc1_stream_encoder_dp_get_pixel_format,
758
759	.enc_read_state = enc401_read_state,
760	.dp_set_dsc_config = NULL,
761	.dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet,
762	.set_dynamic_metadata = enc401_set_dynamic_metadata,
763	.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
764	.enable_stream = enc401_stream_encoder_enable,
765
766	.set_input_mode = enc401_set_dig_input_mode,
767	.enable_fifo = enc35_enable_fifo,
768	.disable_fifo = enc35_disable_fifo,
769	.map_stream_to_link = enc401_stream_encoder_map_to_link,
770};
771
772void dcn401_dio_stream_encoder_construct(
773	struct dcn10_stream_encoder *enc1,
774	struct dc_context *ctx,
775	struct dc_bios *bp,
776	enum engine_id eng_id,
777	struct vpg *vpg,
778	struct afmt *afmt,
779	const struct dcn10_stream_enc_registers *regs,
780	const struct dcn10_stream_encoder_shift *se_shift,
781	const struct dcn10_stream_encoder_mask *se_mask)
782{
783	enc1->base.funcs = &dcn401_str_enc_funcs;
784	enc1->base.ctx = ctx;
785	enc1->base.id = eng_id;
786	enc1->base.bp = bp;
787	enc1->base.vpg = vpg;
788	enc1->base.afmt = afmt;
789	enc1->regs = regs;
790	enc1->se_shift = se_shift;
791	enc1->se_mask = se_mask;
792	enc1->base.stream_enc_inst = vpg->inst;
793}
794
795void enc401_set_dynamic_metadata(struct stream_encoder *enc,
796		bool enable_dme,
797		uint32_t hubp_requestor_id,
798		enum dynamic_metadata_mode dmdata_mode)
799{
800	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
801
802	if (enable_dme) {
803		REG_UPDATE_2(DME_CONTROL,
804				METADATA_HUBP_REQUESTOR_ID, hubp_requestor_id,
805				METADATA_STREAM_TYPE, (dmdata_mode == dmdata_dolby_vision) ? 1 : 0);
806
807		/* Use default line reference DP_SOF for bringup.
808		 * Should use OTG_SOF for DRR cases
809		 */
810		if (dmdata_mode == dmdata_dp)
811			REG_UPDATE_3(DP_SEC_METADATA_TRANSMISSION,
812					DP_SEC_METADATA_PACKET_ENABLE, 1,
813					DP_SEC_METADATA_PACKET_LINE_REFERENCE, 0,
814					DP_SEC_METADATA_PACKET_LINE, 20);
815		else {
816			REG_UPDATE_3(HDMI_METADATA_PACKET_CONTROL,
817					HDMI_METADATA_PACKET_ENABLE, 1,
818					HDMI_METADATA_PACKET_LINE_REFERENCE, 0,
819					HDMI_METADATA_PACKET_LINE, 2);
820
821			if (dmdata_mode == dmdata_dolby_vision)
822				REG_UPDATE(HDMI_CONTROL,
823						DOLBY_VISION_EN, 1);
824		}
825
826		REG_UPDATE(DME_CONTROL,
827				METADATA_ENGINE_EN, 1);
828	} else {
829		REG_UPDATE(DME_CONTROL,
830				METADATA_ENGINE_EN, 0);
831
832		if (dmdata_mode == dmdata_dp)
833			REG_UPDATE(DP_SEC_METADATA_TRANSMISSION,
834					DP_SEC_METADATA_PACKET_ENABLE, 0);
835		else {
836			REG_UPDATE(HDMI_METADATA_PACKET_CONTROL,
837					HDMI_METADATA_PACKET_ENABLE, 0);
838			REG_UPDATE(HDMI_CONTROL,
839					DOLBY_VISION_EN, 0);
840		}
841	}
842}
843void enc401_stream_encoder_set_stream_attribute_helper(
844		struct dcn10_stream_encoder *enc1,
845		struct dc_crtc_timing *crtc_timing)
846{
847	switch (crtc_timing->pixel_encoding) {
848	case PIXEL_ENCODING_YCBCR422:
849		REG_UPDATE(HDMI_CONTROL, TMDS_PIXEL_ENCODING, 1);
850		break;
851	default:
852		REG_UPDATE(HDMI_CONTROL, TMDS_PIXEL_ENCODING, 0);
853		break;
854	}
855	REG_UPDATE(HDMI_CONTROL, TMDS_COLOR_FORMAT, 0);
856}