dcn30_dio_stream_encoder.c

  1/*
  2 * Copyright 2020 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 *  and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26
 27#include "dc_bios_types.h"
 28#include "dcn30_dio_stream_encoder.h"
 29#include "reg_helper.h"
 30#include "hw_shared.h"
 31#include "dc.h"
 32
 33#define DC_LOGGER \
 34		enc1->base.ctx->logger
 35
 36#define REG(reg)\
 37	(enc1->regs->reg)
 38
 39#undef FN
 40#define FN(reg_name, field_name) \
 41	enc1->se_shift->field_name, enc1->se_mask->field_name
 42
 43#define VBI_LINE_0 0
 44#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
 45
 46#define CTX \
 47	enc1->base.ctx
 48
 49
 50void enc3_update_hdmi_info_packet(
 51	struct dcn10_stream_encoder *enc1,
 52	uint32_t packet_index,
 53	const struct dc_info_packet *info_packet)
 54{
 55	uint32_t cont, send, line;
 56
 57	if (info_packet->valid) {
 58		enc1->base.vpg->funcs->update_generic_info_packet(
 59				enc1->base.vpg,
 60				packet_index,
 61				info_packet,
 62				true);
 63
 64		/* enable transmission of packet(s) -
 65		 * packet transmission begins on the next frame */
 66		cont = 1;
 67		/* send packet(s) every frame */
 68		send = 1;
 69		/* select line number to send packets on */
 70		line = 2;
 71	} else {
 72		cont = 0;
 73		send = 0;
 74		line = 0;
 75	}
 76
 77	/* DP_SEC_GSP[x]_LINE_REFERENCE - keep default value REFER_TO_DP_SOF */
 78
 79	/* choose which generic packet control to use */
 80	switch (packet_index) {
 81	case 0:
 82		REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
 83				HDMI_GENERIC0_CONT, cont,
 84				HDMI_GENERIC0_SEND, send);
 85		REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1,
 86				HDMI_GENERIC0_LINE, line);
 87		break;
 88	case 1:
 89		REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
 90				HDMI_GENERIC1_CONT, cont,
 91				HDMI_GENERIC1_SEND, send);
 92		REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1,
 93				HDMI_GENERIC1_LINE, line);
 94		break;
 95	case 2:
 96		REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
 97				HDMI_GENERIC2_CONT, cont,
 98				HDMI_GENERIC2_SEND, send);
 99		REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2,
100				HDMI_GENERIC2_LINE, line);
101		break;
102	case 3:
103		REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
104				HDMI_GENERIC3_CONT, cont,
105				HDMI_GENERIC3_SEND, send);
106		REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2,
107				HDMI_GENERIC3_LINE, line);
108		break;
109	case 4:
110		REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
111				HDMI_GENERIC4_CONT, cont,
112				HDMI_GENERIC4_SEND, send);
113		REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3,
114				HDMI_GENERIC4_LINE, line);
115		break;
116	case 5:
117		REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
118				HDMI_GENERIC5_CONT, cont,
119				HDMI_GENERIC5_SEND, send);
120		REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3,
121				HDMI_GENERIC5_LINE, line);
122		break;
123	case 6:
124		REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
125				HDMI_GENERIC6_CONT, cont,
126				HDMI_GENERIC6_SEND, send);
127		REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4,
128				HDMI_GENERIC6_LINE, line);
129		break;
130	case 7:
131		REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
132				HDMI_GENERIC7_CONT, cont,
133				HDMI_GENERIC7_SEND, send);
134		REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4,
135				HDMI_GENERIC7_LINE, line);
136		break;
137	case 8:
138		REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
139				HDMI_GENERIC8_CONT, cont,
140				HDMI_GENERIC8_SEND, send);
141		REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL7,
142				HDMI_GENERIC8_LINE, line);
143		break;
144	case 9:
145		REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
146				HDMI_GENERIC9_CONT, cont,
147				HDMI_GENERIC9_SEND, send);
148		REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL7,
149				HDMI_GENERIC9_LINE, line);
150		break;
151	case 10:
152		REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
153				HDMI_GENERIC10_CONT, cont,
154				HDMI_GENERIC10_SEND, send);
155		REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL8,
156				HDMI_GENERIC10_LINE, line);
157		break;
158	case 11:
159		REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
160				HDMI_GENERIC11_CONT, cont,
161				HDMI_GENERIC11_SEND, send);
162		REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL8,
163				HDMI_GENERIC11_LINE, line);
164		break;
165	case 12:
166		REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
167				HDMI_GENERIC12_CONT, cont,
168				HDMI_GENERIC12_SEND, send);
169		REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL9,
170				HDMI_GENERIC12_LINE, line);
171		break;
172	case 13:
173		REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
174				HDMI_GENERIC13_CONT, cont,
175				HDMI_GENERIC13_SEND, send);
176		REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL9,
177				HDMI_GENERIC13_LINE, line);
178		break;
179	case 14:
180		REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
181				HDMI_GENERIC14_CONT, cont,
182				HDMI_GENERIC14_SEND, send);
183		REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL10,
184				HDMI_GENERIC14_LINE, line);
185		break;
186	default:
187		/* invalid HW packet index */
188		DC_LOG_WARNING(
189			"Invalid HW packet index: %s()\n",
190			__func__);
191		return;
192	}
193}
194
195void enc3_stream_encoder_update_hdmi_info_packets(
196	struct stream_encoder *enc,
197	const struct encoder_info_frame *info_frame)
198{
199	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
200
201	/* for bring up, disable dp double  TODO */
202	REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
203	REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
204
205	/*Always add mandatory packets first followed by optional ones*/
206	enc3_update_hdmi_info_packet(enc1, 0, &info_frame->avi);
207	enc3_update_hdmi_info_packet(enc1, 5, &info_frame->hfvsif);
208	enc3_update_hdmi_info_packet(enc1, 2, &info_frame->gamut);
209	enc3_update_hdmi_info_packet(enc1, 1, &info_frame->vendor);
210	enc3_update_hdmi_info_packet(enc1, 3, &info_frame->spd);
211	enc3_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd);
212	enc3_update_hdmi_info_packet(enc1, 6, &info_frame->vtem);
213}
214
215void enc3_stream_encoder_stop_hdmi_info_packets(
216	struct stream_encoder *enc)
217{
218	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
219
220	/* stop generic packets 0,1 on HDMI */
221	REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
222		HDMI_GENERIC0_CONT, 0,
223		HDMI_GENERIC0_SEND, 0,
224		HDMI_GENERIC1_CONT, 0,
225		HDMI_GENERIC1_SEND, 0);
226	REG_SET_2(HDMI_GENERIC_PACKET_CONTROL1, 0,
227		HDMI_GENERIC0_LINE, 0,
228		HDMI_GENERIC1_LINE, 0);
229
230	/* stop generic packets 2,3 on HDMI */
231	REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
232		HDMI_GENERIC2_CONT, 0,
233		HDMI_GENERIC2_SEND, 0,
234		HDMI_GENERIC3_CONT, 0,
235		HDMI_GENERIC3_SEND, 0);
236	REG_SET_2(HDMI_GENERIC_PACKET_CONTROL2, 0,
237		HDMI_GENERIC2_LINE, 0,
238		HDMI_GENERIC3_LINE, 0);
239
240	/* stop generic packets 4,5 on HDMI */
241	REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
242		HDMI_GENERIC4_CONT, 0,
243		HDMI_GENERIC4_SEND, 0,
244		HDMI_GENERIC5_CONT, 0,
245		HDMI_GENERIC5_SEND, 0);
246	REG_SET_2(HDMI_GENERIC_PACKET_CONTROL3, 0,
247		HDMI_GENERIC4_LINE, 0,
248		HDMI_GENERIC5_LINE, 0);
249
250	/* stop generic packets 6,7 on HDMI */
251	REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
252		HDMI_GENERIC6_CONT, 0,
253		HDMI_GENERIC6_SEND, 0,
254		HDMI_GENERIC7_CONT, 0,
255		HDMI_GENERIC7_SEND, 0);
256	REG_SET_2(HDMI_GENERIC_PACKET_CONTROL4, 0,
257		HDMI_GENERIC6_LINE, 0,
258		HDMI_GENERIC7_LINE, 0);
259
260	/* stop generic packets 8,9 on HDMI */
261	REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0,
262		HDMI_GENERIC8_CONT, 0,
263		HDMI_GENERIC8_SEND, 0,
264		HDMI_GENERIC9_CONT, 0,
265		HDMI_GENERIC9_SEND, 0);
266	REG_SET_2(HDMI_GENERIC_PACKET_CONTROL7, 0,
267		HDMI_GENERIC8_LINE, 0,
268		HDMI_GENERIC9_LINE, 0);
269
270	/* stop generic packets 10,11 on HDMI */
271	REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0,
272		HDMI_GENERIC10_CONT, 0,
273		HDMI_GENERIC10_SEND, 0,
274		HDMI_GENERIC11_CONT, 0,
275		HDMI_GENERIC11_SEND, 0);
276	REG_SET_2(HDMI_GENERIC_PACKET_CONTROL8, 0,
277		HDMI_GENERIC10_LINE, 0,
278		HDMI_GENERIC11_LINE, 0);
279
280	/* stop generic packets 12,13 on HDMI */
281	REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0,
282		HDMI_GENERIC12_CONT, 0,
283		HDMI_GENERIC12_SEND, 0,
284		HDMI_GENERIC13_CONT, 0,
285		HDMI_GENERIC13_SEND, 0);
286	REG_SET_2(HDMI_GENERIC_PACKET_CONTROL9, 0,
287		HDMI_GENERIC12_LINE, 0,
288		HDMI_GENERIC13_LINE, 0);
289
290	/* stop generic packet 14 on HDMI */
291	REG_SET_2(HDMI_GENERIC_PACKET_CONTROL6, 0,
292		HDMI_GENERIC14_CONT, 0,
293		HDMI_GENERIC14_SEND, 0);
294	REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL10,
295		HDMI_GENERIC14_LINE, 0);
296}
297
298/* Set DSC-related configuration.
299 *   dsc_mode: 0 disables DSC, other values enable DSC in specified format
300 *   sc_bytes_per_pixel: Bytes per pixel in u3.28 format
301 *   dsc_slice_width: Slice width in pixels
302 */
303static void enc3_dp_set_dsc_config(struct stream_encoder *enc,
304					enum optc_dsc_mode dsc_mode,
305					uint32_t dsc_bytes_per_pixel,
306					uint32_t dsc_slice_width)
307{
308	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
309
310	REG_UPDATE_2(DP_DSC_CNTL,
311			DP_DSC_MODE, dsc_mode,
312			DP_DSC_SLICE_WIDTH, dsc_slice_width);
313
314	REG_SET(DP_DSC_BYTES_PER_PIXEL, 0,
315		DP_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel);
316}
317
318
319void enc3_dp_set_dsc_pps_info_packet(struct stream_encoder *enc,
320					bool enable,
321					uint8_t *dsc_packed_pps,
322					bool immediate_update)
323{
324	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
325
326	if (enable) {
327		struct dc_info_packet pps_sdp;
328		int i;
329
330		/* Configure for PPS packet size (128 bytes) */
331		REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP11_PPS, 1);
332
333		/* We need turn on clock before programming AFMT block
334		 *
335		 * TODO: We may not need this here anymore since update_generic_info_packet
336		 * no longer touches AFMT
337		 */
338		REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
339
340		/* Load PPS into infoframe (SDP) registers */
341		pps_sdp.valid = true;
342		pps_sdp.hb0 = 0;
343		pps_sdp.hb1 = DC_DP_INFOFRAME_TYPE_PPS;
344		pps_sdp.hb2 = 127;
345		pps_sdp.hb3 = 0;
346
347		for (i = 0; i < 4; i++) {
348			memcpy(pps_sdp.sb, &dsc_packed_pps[i * 32], 32);
349			enc1->base.vpg->funcs->update_generic_info_packet(
350							enc1->base.vpg,
351							11 + i,
352							&pps_sdp,
353							immediate_update);
354		}
355
356		/* SW should make sure VBID[6] update line number is bigger
357		 * than PPS transmit line number
358		 */
359		REG_UPDATE(DP_GSP11_CNTL,
360				DP_SEC_GSP11_LINE_NUM, 2);
361		REG_UPDATE_2(DP_MSA_VBID_MISC,
362				DP_VBID6_LINE_REFERENCE, 0,
363				DP_VBID6_LINE_NUM, 3);
364
365		/* Send PPS data at the line number specified above.
366		 * DP spec requires PPS to be sent only when it changes, however since
367		 * decoder has to be able to handle its change on every frame, we're
368		 * sending it always (i.e. on every frame) to reduce the chance it'd be
369		 * missed by decoder. If it turns out required to send PPS only when it
370		 * changes, we can use DP_SEC_GSP11_SEND register.
371		 */
372		REG_UPDATE(DP_GSP11_CNTL,
373			DP_SEC_GSP11_ENABLE, 1);
374		REG_UPDATE(DP_SEC_CNTL,
375			DP_SEC_STREAM_ENABLE, 1);
376	} else {
377		/* Disable Generic Stream Packet 11 (GSP) transmission */
378		REG_UPDATE(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, 0);
379		REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP11_PPS, 0);
380	}
381}
382
383
384/* this function read dsc related register fields to be logged later in dcn10_log_hw_state
385 * into a dcn_dsc_state struct.
386 */
387static void enc3_read_state(struct stream_encoder *enc, struct enc_state *s)
388{
389	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
390
391	//if dsc is enabled, continue to read
392	REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode);
393	if (s->dsc_mode) {
394		REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width);
395		REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num);
396
397		REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference);
398		REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num);
399
400		REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable);
401		REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
402	}
403}
404
405void enc3_stream_encoder_update_dp_info_packets_sdp_line_num(
406		struct stream_encoder *enc,
407		struct encoder_info_frame *info_frame)
408{
409	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
410
411	if (info_frame->adaptive_sync.valid == true &&
412		info_frame->sdp_line_num.adaptive_sync_line_num_valid == true) {
413		//00: REFER_TO_DP_SOF, 01: REFER_TO_OTG_SOF
414		REG_UPDATE(DP_SEC_CNTL1, DP_SEC_GSP5_LINE_REFERENCE, 1);
415
416		REG_UPDATE(DP_SEC_CNTL5, DP_SEC_GSP5_LINE_NUM,
417					info_frame->sdp_line_num.adaptive_sync_line_num);
418	}
419}
420
421void enc3_stream_encoder_update_dp_info_packets(
422	struct stream_encoder *enc,
423	const struct encoder_info_frame *info_frame)
424{
425	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
426	uint32_t value = 0;
427	uint32_t dmdata_packet_enabled = 0;
428
429	if (info_frame->vsc.valid) {
430		enc->vpg->funcs->update_generic_info_packet(
431				enc->vpg,
432				0,  /* packetIndex */
433				&info_frame->vsc,
434				true);
435	}
436	/* TODO: VSC SDP at packetIndex 1 should be retricted only if PSR-SU on.
437	 * There should have another Infopacket type (e.g. vsc_psrsu) for PSR_SU.
438	 * In addition, currently the driver check the valid bit then update and
439	 * send the corresponding Infopacket. For PSR-SU, the SDP only be sent
440	 * while entering PSR-SU mode. So we need another parameter(e.g. send)
441	 * in dc_info_packet to indicate which infopacket should be enabled by
442	 * default here.
443	 */
444	if (info_frame->vsc.valid) {
445		enc->vpg->funcs->update_generic_info_packet(
446				enc->vpg,
447				1,  /* packetIndex */
448				&info_frame->vsc,
449				true);
450	}
451	/* TODO: VSC SDP at packetIndex 1 should be restricted only if PSR-SU on.
452	 * There should have another Infopacket type (e.g. vsc_psrsu) for PSR_SU.
453	 * In addition, currently the driver check the valid bit then update and
454	 * send the corresponding Infopacket. For PSR-SU, the SDP only be sent
455	 * while entering PSR-SU mode. So we need another parameter(e.g. send)
456	 * in dc_info_packet to indicate which infopacket should be enabled by
457	 * default here.
458	 */
459	if (info_frame->vsc.valid) {
460		enc->vpg->funcs->update_generic_info_packet(
461				enc->vpg,
462				1,  /* packetIndex */
463				&info_frame->vsc,
464				true);
465	}
466	if (info_frame->spd.valid) {
467		enc->vpg->funcs->update_generic_info_packet(
468				enc->vpg,
469				2,  /* packetIndex */
470				&info_frame->spd,
471				true);
472	}
473	if (info_frame->hdrsmd.valid) {
474		enc->vpg->funcs->update_generic_info_packet(
475				enc->vpg,
476				3,  /* packetIndex */
477				&info_frame->hdrsmd,
478				true);
479	}
480	/* packetIndex 4 is used for send immediate sdp message, and please
481	 * use other packetIndex (such as 5,6) for other info packet
482	 */
483
484	if (info_frame->adaptive_sync.valid)
485		enc->vpg->funcs->update_generic_info_packet(
486				enc->vpg,
487				5,  /* packetIndex */
488				&info_frame->adaptive_sync,
489				true);
490
491	/* enable/disable transmission of packet(s).
492	 * If enabled, packet transmission begins on the next frame
493	 */
494	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
495	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
496	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
497	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, info_frame->adaptive_sync.valid);
498
499	/* This bit is the master enable bit.
500	 * When enabling secondary stream engine,
501	 * this master bit must also be set.
502	 * This register shared with audio info frame.
503	 * Therefore we need to enable master bit
504	 * if at least on of the fields is not 0
505	 */
506	value = REG_READ(DP_SEC_CNTL);
507	if (value)
508		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
509
510	/* check if dynamic metadata packet transmission is enabled */
511	REG_GET(DP_SEC_METADATA_TRANSMISSION,
512			DP_SEC_METADATA_PACKET_ENABLE, &dmdata_packet_enabled);
513
514	if (dmdata_packet_enabled)
515		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
516}
517
518static void enc3_dp_set_odm_combine(
519	struct stream_encoder *enc,
520	bool odm_combine)
521{
522	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
523
524	REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, odm_combine);
525}
526
527/* setup stream encoder in dvi mode */
528static void enc3_stream_encoder_dvi_set_stream_attribute(
529	struct stream_encoder *enc,
530	struct dc_crtc_timing *crtc_timing,
531	bool is_dual_link)
532{
533	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
534
535	if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
536		struct bp_encoder_control cntl = {0};
537
538		cntl.action = ENCODER_CONTROL_SETUP;
539		cntl.engine_id = enc1->base.id;
540		cntl.signal = is_dual_link ?
541			SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
542		cntl.enable_dp_audio = false;
543		cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
544		cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
545
546		if (enc1->base.bp->funcs->encoder_control(
547				enc1->base.bp, &cntl) != BP_RESULT_OK)
548			return;
549
550	} else {
551
552		//Set pattern for clock channel, default vlue 0x63 does not work
553		REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
554
555		//DIG_BE_TMDS_DVI_MODE : TMDS-DVI mode is already set in link_encoder_setup
556
557		//DIG_SOURCE_SELECT is already set in dig_connect_to_otg
558
559		/* set DIG_START to 0x1 to reset FIFO */
560		REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
561		udelay(1);
562
563		/* write 0 to take the FIFO out of reset */
564		REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);
565		udelay(1);
566	}
567
568	ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
569	ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
570	enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
571}
572
573/* setup stream encoder in hdmi mode */
574static void enc3_stream_encoder_hdmi_set_stream_attribute(
575	struct stream_encoder *enc,
576	struct dc_crtc_timing *crtc_timing,
577	int actual_pix_clk_khz,
578	bool enable_audio)
579{
580	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
581
582	if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
583		struct bp_encoder_control cntl = {0};
584
585		cntl.action = ENCODER_CONTROL_SETUP;
586		cntl.engine_id = enc1->base.id;
587		cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
588		cntl.enable_dp_audio = enable_audio;
589		cntl.pixel_clock = actual_pix_clk_khz;
590		cntl.lanes_number = LANE_COUNT_FOUR;
591
592		if (enc1->base.bp->funcs->encoder_control(
593				enc1->base.bp, &cntl) != BP_RESULT_OK)
594			return;
595
596	} else {
597
598		//Set pattern for clock channel, default vlue 0x63 does not work
599		REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
600
601		//DIG_BE_TMDS_HDMI_MODE : TMDS-HDMI mode is already set in link_encoder_setup
602
603		//DIG_SOURCE_SELECT is already set in dig_connect_to_otg
604
605		/* set DIG_START to 0x1 to reset FIFO */
606		REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
607		udelay(1);
608
609		/* write 0 to take the FIFO out of reset */
610		REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);
611		udelay(1);
612	}
613
614	/* Configure pixel encoding */
615	enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
616
617	/* setup HDMI engine */
618	REG_UPDATE_6(HDMI_CONTROL,
619		HDMI_PACKET_GEN_VERSION, 1,
620		HDMI_KEEPOUT_MODE, 1,
621		HDMI_DEEP_COLOR_ENABLE, 0,
622		HDMI_DATA_SCRAMBLE_EN, 0,
623		HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1,
624		HDMI_CLOCK_CHANNEL_RATE, 0);
625
626	/* Configure color depth */
627	switch (crtc_timing->display_color_depth) {
628	case COLOR_DEPTH_888:
629		REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
630		break;
631	case COLOR_DEPTH_101010:
632		if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
633			REG_UPDATE_2(HDMI_CONTROL,
634					HDMI_DEEP_COLOR_DEPTH, 1,
635					HDMI_DEEP_COLOR_ENABLE, 0);
636		} else {
637			REG_UPDATE_2(HDMI_CONTROL,
638					HDMI_DEEP_COLOR_DEPTH, 1,
639					HDMI_DEEP_COLOR_ENABLE, 1);
640			}
641		break;
642	case COLOR_DEPTH_121212:
643		if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
644			REG_UPDATE_2(HDMI_CONTROL,
645					HDMI_DEEP_COLOR_DEPTH, 2,
646					HDMI_DEEP_COLOR_ENABLE, 0);
647		} else {
648			REG_UPDATE_2(HDMI_CONTROL,
649					HDMI_DEEP_COLOR_DEPTH, 2,
650					HDMI_DEEP_COLOR_ENABLE, 1);
651			}
652		break;
653	case COLOR_DEPTH_161616:
654		REG_UPDATE_2(HDMI_CONTROL,
655				HDMI_DEEP_COLOR_DEPTH, 3,
656				HDMI_DEEP_COLOR_ENABLE, 1);
657		break;
658	default:
659		break;
660	}
661
662	if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
663		/* enable HDMI data scrambler
664		 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
665		 * Clock channel frequency is 1/4 of character rate.
666		 */
667		REG_UPDATE_2(HDMI_CONTROL,
668			HDMI_DATA_SCRAMBLE_EN, 1,
669			HDMI_CLOCK_CHANNEL_RATE, 1);
670	} else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
671
672		/* TODO: New feature for DCE11, still need to implement */
673
674		/* enable HDMI data scrambler
675		 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
676		 * Clock channel frequency is the same
677		 * as character rate
678		 */
679		REG_UPDATE_2(HDMI_CONTROL,
680			HDMI_DATA_SCRAMBLE_EN, 1,
681			HDMI_CLOCK_CHANNEL_RATE, 0);
682	}
683
684
685	/* Enable transmission of General Control packet on every frame */
686	REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
687		HDMI_GC_CONT, 1,
688		HDMI_GC_SEND, 1,
689		HDMI_NULL_SEND, 1);
690
691	/* Disable Audio Content Protection packet transmission */
692	REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);
693
694	/* following belongs to audio */
695	/* Enable Audio InfoFrame packet transmission. */
696	REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
697
698	/* update double-buffered AUDIO_INFO registers immediately */
699	ASSERT (enc->afmt);
700	enc->afmt->funcs->audio_info_immediate_update(enc->afmt);
701
702	/* Select line number on which to send Audio InfoFrame packets */
703	REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
704				VBI_LINE_0 + 2);
705
706	/* set HDMI GC AVMUTE */
707	REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
708}
709
710void enc3_audio_mute_control(
711	struct stream_encoder *enc,
712	bool mute)
713{
714	ASSERT (enc->afmt);
715	enc->afmt->funcs->audio_mute_control(enc->afmt, mute);
716}
717
718void enc3_se_dp_audio_setup(
719	struct stream_encoder *enc,
720	unsigned int az_inst,
721	struct audio_info *info)
722{
723	ASSERT (enc->afmt);
724	enc->afmt->funcs->se_audio_setup(enc->afmt, az_inst, info);
725}
726
727#define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
728#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
729
730static void enc3_se_setup_dp_audio(
731	struct stream_encoder *enc)
732{
733	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
734
735	/* --- DP Audio packet configurations --- */
736
737	/* ATP Configuration */
738	REG_SET(DP_SEC_AUD_N, 0,
739			DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
740
741	/* Async/auto-calc timestamp mode */
742	REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
743			DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
744
745	ASSERT (enc->afmt);
746	enc->afmt->funcs->setup_dp_audio(enc->afmt);
747}
748
749void enc3_se_dp_audio_enable(
750	struct stream_encoder *enc)
751{
752	enc1_se_enable_audio_clock(enc, true);
753	enc3_se_setup_dp_audio(enc);
754	enc1_se_enable_dp_audio(enc);
755}
756
757static void enc3_se_setup_hdmi_audio(
758	struct stream_encoder *enc,
759	const struct audio_crtc_info *crtc_info)
760{
761	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
762
763	struct audio_clock_info audio_clock_info = {0};
764
765	/* Setup audio in AFMT - program AFMT block associated with DIO */
766	ASSERT (enc->afmt);
767	enc->afmt->funcs->setup_hdmi_audio(enc->afmt);
768
769	/* HDMI_AUDIO_PACKET_CONTROL */
770	REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL,
771			HDMI_AUDIO_DELAY_EN, 1);
772
773	/* HDMI_ACR_PACKET_CONTROL */
774	REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
775			HDMI_ACR_AUTO_SEND, 1,
776			HDMI_ACR_SOURCE, 0,
777			HDMI_ACR_AUDIO_PRIORITY, 0);
778
779	/* Program audio clock sample/regeneration parameters */
780	get_audio_clock_info(crtc_info->color_depth,
781			     crtc_info->requested_pixel_clock_100Hz,
782			     crtc_info->calculated_pixel_clock_100Hz,
783			     &audio_clock_info);
784	DC_LOG_HW_AUDIO(
785			"\n%s:Input::requested_pixel_clock_100Hz = %d"	\
786			"calculated_pixel_clock_100Hz = %d \n", __func__,	\
787			crtc_info->requested_pixel_clock_100Hz,		\
788			crtc_info->calculated_pixel_clock_100Hz);
789
790	/* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
791	REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
792
793	/* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
794	REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
795
796	/* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
797	REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
798
799	/* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
800	REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
801
802	/* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
803	REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
804
805	/* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
806	REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
807
808	/* Video driver cannot know in advance which sample rate will
809	 * be used by HD Audio driver
810	 * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
811	 * programmed below in interruppt callback
812	 */
813}
814
815void enc3_se_hdmi_audio_setup(
816	struct stream_encoder *enc,
817	unsigned int az_inst,
818	struct audio_info *info,
819	struct audio_crtc_info *audio_crtc_info)
820{
821	enc1_se_enable_audio_clock(enc, true);
822	enc3_se_setup_hdmi_audio(enc, audio_crtc_info);
823	ASSERT (enc->afmt);
824	enc->afmt->funcs->se_audio_setup(enc->afmt, az_inst, info);
825}
826
827
828static const struct stream_encoder_funcs dcn30_str_enc_funcs = {
829	.dp_set_odm_combine =
830		enc3_dp_set_odm_combine,
831	.dp_set_stream_attribute =
832		enc2_stream_encoder_dp_set_stream_attribute,
833	.hdmi_set_stream_attribute =
834		enc3_stream_encoder_hdmi_set_stream_attribute,
835	.dvi_set_stream_attribute =
836		enc3_stream_encoder_dvi_set_stream_attribute,
837	.set_throttled_vcp_size =
838		enc1_stream_encoder_set_throttled_vcp_size,
839	.update_hdmi_info_packets =
840		enc3_stream_encoder_update_hdmi_info_packets,
841	.stop_hdmi_info_packets =
842		enc3_stream_encoder_stop_hdmi_info_packets,
843	.update_dp_info_packets_sdp_line_num =
844		enc3_stream_encoder_update_dp_info_packets_sdp_line_num,
845	.update_dp_info_packets =
846		enc3_stream_encoder_update_dp_info_packets,
847	.stop_dp_info_packets =
848		enc1_stream_encoder_stop_dp_info_packets,
849	.dp_blank =
850		enc1_stream_encoder_dp_blank,
851	.dp_unblank =
852		enc2_stream_encoder_dp_unblank,
853	.audio_mute_control = enc3_audio_mute_control,
854
855	.dp_audio_setup = enc3_se_dp_audio_setup,
856	.dp_audio_enable = enc3_se_dp_audio_enable,
857	.dp_audio_disable = enc1_se_dp_audio_disable,
858
859	.hdmi_audio_setup = enc3_se_hdmi_audio_setup,
860	.hdmi_audio_disable = enc1_se_hdmi_audio_disable,
861	.setup_stereo_sync  = enc1_setup_stereo_sync,
862	.set_avmute = enc1_stream_encoder_set_avmute,
863	.dig_connect_to_otg = enc1_dig_connect_to_otg,
864	.dig_source_otg = enc1_dig_source_otg,
865
866	.dp_get_pixel_format  = enc1_stream_encoder_dp_get_pixel_format,
867
868	.enc_read_state = enc3_read_state,
869	.dp_set_dsc_config = enc3_dp_set_dsc_config,
870	.dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet,
871	.set_dynamic_metadata = enc2_set_dynamic_metadata,
872	.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
873
874	.get_fifo_cal_average_level = enc2_get_fifo_cal_average_level,
875};
876
877void dcn30_dio_stream_encoder_construct(
878	struct dcn10_stream_encoder *enc1,
879	struct dc_context *ctx,
880	struct dc_bios *bp,
881	enum engine_id eng_id,
882	struct vpg *vpg,
883	struct afmt *afmt,
884	const struct dcn10_stream_enc_registers *regs,
885	const struct dcn10_stream_encoder_shift *se_shift,
886	const struct dcn10_stream_encoder_mask *se_mask)
887{
888	enc1->base.funcs = &dcn30_str_enc_funcs;
889	enc1->base.ctx = ctx;
890	enc1->base.id = eng_id;
891	enc1->base.bp = bp;
892	enc1->base.vpg = vpg;
893	enc1->base.afmt = afmt;
894	enc1->regs = regs;
895	enc1->se_shift = se_shift;
896	enc1->se_mask = se_mask;
897	enc1->base.stream_enc_inst = vpg->inst;
898}
899