dcn30_dio_link_encoder.c

  1/*
  2 * Copyright 2020 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#include "reg_helper.h"
 27
 28#include "core_types.h"
 29#include "link_encoder.h"
 30#include "dcn30_dio_link_encoder.h"
 31#include "stream_encoder.h"
 32#include "dc_bios_types.h"
 33#include "gpio_service_interface.h"
 34
 35#define CTX \
 36	enc10->base.ctx
 37#define DC_LOGGER \
 38	enc10->base.ctx->logger
 39
 40#define REG(reg)\
 41	(enc10->link_regs->reg)
 42
 43#undef FN
 44#define FN(reg_name, field_name) \
 45	enc10->link_shift->field_name, enc10->link_mask->field_name
 46
 47#define IND_REG(index) \
 48	(enc10->link_regs->index)
 49
 50
 51bool dcn30_link_encoder_validate_output_with_stream(
 52	struct link_encoder *enc,
 53	const struct dc_stream_state *stream)
 54{
 55		return dcn10_link_encoder_validate_output_with_stream(enc, stream);
 56}
 57
 58static const struct link_encoder_funcs dcn30_link_enc_funcs = {
 59	.read_state = link_enc2_read_state,
 60	.validate_output_with_stream =
 61			dcn30_link_encoder_validate_output_with_stream,
 62	.hw_init = enc3_hw_init,
 63	.setup = dcn10_link_encoder_setup,
 64	.enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
 65	.enable_dp_output = dcn20_link_encoder_enable_dp_output,
 66	.enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
 67	.disable_output = dcn10_link_encoder_disable_output,
 68	.dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
 69	.dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
 70	.update_mst_stream_allocation_table =
 71		dcn10_link_encoder_update_mst_stream_allocation_table,
 72	.psr_program_dp_dphy_fast_training =
 73			dcn10_psr_program_dp_dphy_fast_training,
 74	.psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
 75	.connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
 76	.enable_hpd = dcn10_link_encoder_enable_hpd,
 77	.disable_hpd = dcn10_link_encoder_disable_hpd,
 78	.is_dig_enabled = dcn10_is_dig_enabled,
 79	.destroy = dcn10_link_encoder_destroy,
 80	.fec_set_enable = enc2_fec_set_enable,
 81	.fec_set_ready = enc2_fec_set_ready,
 82	.fec_is_active = enc2_fec_is_active,
 83	.get_dig_frontend = dcn10_get_dig_frontend,
 84	.get_dig_mode = dcn10_get_dig_mode,
 85	.is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
 86	.get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
 87};
 88
 89void dcn30_link_encoder_construct(
 90	struct dcn20_link_encoder *enc20,
 91	const struct encoder_init_data *init_data,
 92	const struct encoder_feature_support *enc_features,
 93	const struct dcn10_link_enc_registers *link_regs,
 94	const struct dcn10_link_enc_aux_registers *aux_regs,
 95	const struct dcn10_link_enc_hpd_registers *hpd_regs,
 96	const struct dcn10_link_enc_shift *link_shift,
 97	const struct dcn10_link_enc_mask *link_mask)
 98{
 99	struct bp_encoder_cap_info bp_cap_info = {0};
100	const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
101	enum bp_result result = BP_RESULT_OK;
102	struct dcn10_link_encoder *enc10 = &enc20->enc10;
103
104	enc10->base.funcs = &dcn30_link_enc_funcs;
105	enc10->base.ctx = init_data->ctx;
106	enc10->base.id = init_data->encoder;
107
108	enc10->base.hpd_source = init_data->hpd_source;
109	enc10->base.connector = init_data->connector;
110
111	enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
112
113	enc10->base.features = *enc_features;
114
115	enc10->base.transmitter = init_data->transmitter;
116
117	/* set the flag to indicate whether driver poll the I2C data pin
118	 * while doing the DP sink detect
119	 */
120
121/*	if (dal_adapter_service_is_feature_supported(as,
122		FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
123		enc10->base.features.flags.bits.
124			DP_SINK_DETECT_POLL_DATA_PIN = true;*/
125
126	enc10->base.output_signals =
127		SIGNAL_TYPE_DVI_SINGLE_LINK |
128		SIGNAL_TYPE_DVI_DUAL_LINK |
129		SIGNAL_TYPE_LVDS |
130		SIGNAL_TYPE_DISPLAY_PORT |
131		SIGNAL_TYPE_DISPLAY_PORT_MST |
132		SIGNAL_TYPE_EDP |
133		SIGNAL_TYPE_HDMI_TYPE_A;
134
135	/* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
136	 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
137	 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
138	 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
139	 * Prefer DIG assignment is decided by board design.
140	 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
141	 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
142	 * By this, adding DIGG should not hurt DCE 8.0.
143	 * This will let DCE 8.1 share DCE 8.0 as much as possible
144	 */
145
146	enc10->link_regs = link_regs;
147	enc10->aux_regs = aux_regs;
148	enc10->hpd_regs = hpd_regs;
149	enc10->link_shift = link_shift;
150	enc10->link_mask = link_mask;
151
152	switch (enc10->base.transmitter) {
153	case TRANSMITTER_UNIPHY_A:
154		enc10->base.preferred_engine = ENGINE_ID_DIGA;
155	break;
156	case TRANSMITTER_UNIPHY_B:
157		enc10->base.preferred_engine = ENGINE_ID_DIGB;
158	break;
159	case TRANSMITTER_UNIPHY_C:
160		enc10->base.preferred_engine = ENGINE_ID_DIGC;
161	break;
162	case TRANSMITTER_UNIPHY_D:
163		enc10->base.preferred_engine = ENGINE_ID_DIGD;
164	break;
165	case TRANSMITTER_UNIPHY_E:
166		enc10->base.preferred_engine = ENGINE_ID_DIGE;
167	break;
168	case TRANSMITTER_UNIPHY_F:
169		enc10->base.preferred_engine = ENGINE_ID_DIGF;
170	break;
171	case TRANSMITTER_UNIPHY_G:
172		enc10->base.preferred_engine = ENGINE_ID_DIGG;
173	break;
174	default:
175		ASSERT_CRITICAL(false);
176		enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
177	}
178
179	/* default to one to mirror Windows behavior */
180	enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
181
182	result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
183						enc10->base.id, &bp_cap_info);
184
185	/* Override features with DCE-specific values */
186	if (result == BP_RESULT_OK) {
187		enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
188				bp_cap_info.DP_HBR2_EN;
189		enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
190				bp_cap_info.DP_HBR3_EN;
191		enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
192		enc10->base.features.flags.bits.IS_DP2_CAPABLE = bp_cap_info.IS_DP2_CAPABLE;
193		enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;
194		enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;
195		enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;
196		enc10->base.features.flags.bits.DP_IS_USB_C =
197				bp_cap_info.DP_IS_USB_C;
198	} else {
199		DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
200				__func__,
201				result);
202	}
203	if (enc10->base.ctx->dc->debug.hdmi20_disable) {
204		enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
205	}
206}
207
208#define AUX_REG(reg)\
209	(enc10->aux_regs->reg)
210
211#define AUX_REG_READ(reg_name) \
212		dm_read_reg(CTX, AUX_REG(reg_name))
213
214#define AUX_REG_WRITE(reg_name, val) \
215			dm_write_reg(CTX, AUX_REG(reg_name), val)
216void enc3_hw_init(struct link_encoder *enc)
217{
218	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
219
220/*
221	00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2
222	01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4
223	02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8
224	03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16
225	04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32
226	05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64
227	06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128
228	07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256
229*/
230
231/*
232	AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,
233	AUX_RX_START_WINDOW = 1 [6:4]
234	AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8]
235	AUX_RX_HALF_SYM_DETECT_LEN  = 1 [13:12] default is 1
236	AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1
237	AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0  default is 0
238	AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1  default is 1
239	AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1  default is 1
240	AUX_RX_PHASE_DETECT_LEN,  [21,20] = 0x3 default is 3
241	AUX_RX_DETECTION_THRESHOLD [30:28] = 1
242*/
243	AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
244
245	AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
246
247	//AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
248	// Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk
249	// 27MHz -> 0xd
250	// 100MHz -> 0x32
251	// 48MHz -> 0x18
252
253	// Set TMDS_CTL0 to 1.  This is a legacy setting.
254	REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);
255
256	dcn10_aux_initialize(enc10);
257}