dcn10_link_encoder.h

  1/*
  2 * Copyright 2012-15 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 *  and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#ifndef __DC_LINK_ENCODER__DCN10_H__
 27#define __DC_LINK_ENCODER__DCN10_H__
 28
 29#include "link_encoder.h"
 30
 31#define TO_DCN10_LINK_ENC(link_encoder)\
 32	container_of(link_encoder, struct dcn10_link_encoder, base)
 33
 34#define AUX_REG_LIST(id)\
 35	SRI(AUX_CONTROL, DP_AUX, id), \
 36	SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \
 37	SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id)
 38
 39#define HPD_REG_LIST(id)\
 40	SRI(DC_HPD_CONTROL, HPD, id)
 41
 42#define LE_DCN_COMMON_REG_LIST(id) \
 43	SRI(DIG_BE_CNTL, DIG, id), \
 44	SRI(DIG_BE_EN_CNTL, DIG, id), \
 45	SRI(DIG_CLOCK_PATTERN, DIG, id), \
 46	SRI(TMDS_CTL_BITS, DIG, id), \
 47	SRI(DP_CONFIG, DP, id), \
 48	SRI(DP_DPHY_CNTL, DP, id), \
 49	SRI(DP_DPHY_PRBS_CNTL, DP, id), \
 50	SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
 51	SRI(DP_DPHY_SYM0, DP, id), \
 52	SRI(DP_DPHY_SYM1, DP, id), \
 53	SRI(DP_DPHY_SYM2, DP, id), \
 54	SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
 55	SRI(DP_LINK_CNTL, DP, id), \
 56	SRI(DP_LINK_FRAMING_CNTL, DP, id), \
 57	SRI(DP_MSE_SAT0, DP, id), \
 58	SRI(DP_MSE_SAT1, DP, id), \
 59	SRI(DP_MSE_SAT2, DP, id), \
 60	SRI(DP_MSE_SAT_UPDATE, DP, id), \
 61	SRI(DP_SEC_CNTL, DP, id), \
 62	SRI(DP_VID_STREAM_CNTL, DP, id), \
 63	SRI(DP_DPHY_FAST_TRAINING, DP, id), \
 64	SRI(DP_SEC_CNTL1, DP, id), \
 65	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
 66	SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
 67
 68
 69#define LE_DCN10_REG_LIST(id)\
 70	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
 71	LE_DCN_COMMON_REG_LIST(id)
 72
 73struct dcn10_link_enc_aux_registers {
 74	uint32_t AUX_CONTROL;
 75	uint32_t AUX_DPHY_RX_CONTROL0;
 76	uint32_t AUX_DPHY_TX_CONTROL;
 77	uint32_t AUX_DPHY_RX_CONTROL1;
 78};
 79
 80struct dcn10_link_enc_hpd_registers {
 81	uint32_t DC_HPD_CONTROL;
 82};
 83
 84struct dcn10_link_enc_registers {
 85	uint32_t DIG_BE_CNTL;
 86	uint32_t DIG_BE_EN_CNTL;
 87	uint32_t DIG_CLOCK_PATTERN;
 88	uint32_t DP_CONFIG;
 89	uint32_t DP_DPHY_CNTL;
 90	uint32_t DP_DPHY_INTERNAL_CTRL;
 91	uint32_t DP_DPHY_PRBS_CNTL;
 92	uint32_t DP_DPHY_SCRAM_CNTL;
 93	uint32_t DP_DPHY_SYM0;
 94	uint32_t DP_DPHY_SYM1;
 95	uint32_t DP_DPHY_SYM2;
 96	uint32_t DP_DPHY_TRAINING_PATTERN_SEL;
 97	uint32_t DP_LINK_CNTL;
 98	uint32_t DP_LINK_FRAMING_CNTL;
 99	uint32_t DP_MSE_SAT0;
100	uint32_t DP_MSE_SAT1;
101	uint32_t DP_MSE_SAT2;
102	uint32_t DP_MSE_SAT_UPDATE;
103	uint32_t DP_SEC_CNTL;
104	uint32_t DP_VID_STREAM_CNTL;
105	uint32_t DP_DPHY_FAST_TRAINING;
106	uint32_t DP_DPHY_BS_SR_SWAP_CNTL;
107	uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;
108	uint32_t DP_SEC_CNTL1;
109	uint32_t TMDS_CTL_BITS;
110	/* DCCG  */
111	uint32_t CLOCK_ENABLE;
112	/* DIG */
113	uint32_t DIG_LANE_ENABLE;
114	/* UNIPHY */
115	uint32_t CHANNEL_XBAR_CNTL;
116	/* DPCS */
117	uint32_t RDPCSTX_PHY_CNTL3;
118	uint32_t RDPCSTX_PHY_CNTL4;
119	uint32_t RDPCSTX_PHY_CNTL5;
120	uint32_t RDPCSTX_PHY_CNTL6;
121	uint32_t RDPCSPIPE_PHY_CNTL6;
122	uint32_t RDPCSTX_PHY_CNTL7;
123	uint32_t RDPCSTX_PHY_CNTL8;
124	uint32_t RDPCSTX_PHY_CNTL9;
125	uint32_t RDPCSTX_PHY_CNTL10;
126	uint32_t RDPCSTX_PHY_CNTL11;
127	uint32_t RDPCSTX_PHY_CNTL12;
128	uint32_t RDPCSTX_PHY_CNTL13;
129	uint32_t RDPCSTX_PHY_CNTL14;
130	uint32_t RDPCSTX_PHY_CNTL15;
131	uint32_t RDPCSTX_CNTL;
132	uint32_t RDPCSTX_CLOCK_CNTL;
133	uint32_t RDPCSTX_PHY_CNTL0;
134	uint32_t RDPCSTX_PHY_CNTL2;
135	uint32_t RDPCSTX_PLL_UPDATE_DATA;
136	uint32_t RDPCS_TX_CR_ADDR;
137	uint32_t RDPCS_TX_CR_DATA;
138	uint32_t DPCSTX_TX_CLOCK_CNTL;
139	uint32_t DPCSTX_TX_CNTL;
140	uint32_t RDPCSTX_INTERRUPT_CONTROL;
141	uint32_t RDPCSTX_PHY_FUSE0;
142	uint32_t RDPCSTX_PHY_FUSE1;
143	uint32_t RDPCSTX_PHY_FUSE2;
144	uint32_t RDPCSTX_PHY_FUSE3;
145	uint32_t RDPCSTX_PHY_RX_LD_VAL;
146	uint32_t DPCSTX_DEBUG_CONFIG;
147	uint32_t RDPCSTX_DEBUG_CONFIG;
148	uint32_t RDPCSTX0_RDPCSTX_SCRATCH;
149	uint32_t RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG;
150	uint32_t DCIO_SOFT_RESET;
151	/* indirect registers */
152	uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2;
153	uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3;
154	uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2;
155	uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3;
156	uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2;
157	uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3;
158	uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2;
159	uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3;
160	uint32_t TMDS_DCBALANCER_CONTROL;
161	uint32_t PHYA_LINK_CNTL2;
162	uint32_t PHYB_LINK_CNTL2;
163	uint32_t PHYC_LINK_CNTL2;
164	uint32_t DIO_LINKA_CNTL;
165	uint32_t DIO_LINKB_CNTL;
166	uint32_t DIO_LINKC_CNTL;
167	uint32_t DIO_LINKD_CNTL;
168	uint32_t DIO_LINKE_CNTL;
169	uint32_t DIO_LINKF_CNTL;
170	uint32_t DIO_CLK_CNTL;
171	uint32_t DIG_BE_CLK_CNTL;
172};
173
174#define LE_SF(reg_name, field_name, post_fix)\
175	.field_name = reg_name ## __ ## field_name ## post_fix
176
177#define LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh)\
178	LE_SF(DIG0_DIG_BE_EN_CNTL, DIG_ENABLE, mask_sh),\
179	LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\
180	LE_SF(DIG0_DIG_BE_CNTL, DIG_MODE, mask_sh),\
181	LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\
182	LE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\
183	LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
184	LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\
185	LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\
186	LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1, mask_sh),\
187	LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE2, mask_sh),\
188	LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3, mask_sh),\
189	LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, mask_sh),\
190	LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL, mask_sh),\
191	LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\
192	LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\
193	LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\
194	LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\
195	LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\
196	LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\
197	LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\
198	LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\
199	LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, mask_sh),\
200	LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, mask_sh),\
201	LE_SF(DP0_DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, mask_sh),\
202	LE_SF(DP0_DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, mask_sh),\
203	LE_SF(DP0_DP_DPHY_TRAINING_PATTERN_SEL, DPHY_TRAINING_PATTERN_SEL, mask_sh),\
204	LE_SF(DP0_DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL, mask_sh),\
205	LE_SF(DP0_DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, mask_sh),\
206	LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL, mask_sh),\
207	LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VBID_DISABLE, mask_sh),\
208	LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE, mask_sh),\
209	LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
210	LE_SF(DP0_DP_CONFIG, DP_UDI_LANES, mask_sh),\
211	LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_LINE_NUM, mask_sh),\
212	LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_PRIORITY, mask_sh),\
213	LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC0, mask_sh),\
214	LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC1, mask_sh),\
215	LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT0, mask_sh),\
216	LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT1, mask_sh),\
217	LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC2, mask_sh),\
218	LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC3, mask_sh),\
219	LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT2, mask_sh),\
220	LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT3, mask_sh),\
221	LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\
222	LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_16_MTP_KEEPOUT, mask_sh),\
223	LE_SF(DP_AUX0_AUX_CONTROL, AUX_HPD_SEL, mask_sh),\
224	LE_SF(DP_AUX0_AUX_CONTROL, AUX_LS_READ_EN, mask_sh),\
225	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW, mask_sh),\
226	LE_SF(HPD0_DC_HPD_CONTROL, DC_HPD_EN, mask_sh)
227
228#define DCN_LINK_ENCODER_REG_FIELD_LIST(type) \
229	type DIG_ENABLE;\
230	type DIG_HPD_SELECT;\
231	type DIG_MODE;\
232	type DIG_FE_SOURCE_SELECT;\
233	type DIG_CLOCK_PATTERN;\
234	type DPHY_BYPASS;\
235	type DPHY_ATEST_SEL_LANE0;\
236	type DPHY_ATEST_SEL_LANE1;\
237	type DPHY_ATEST_SEL_LANE2;\
238	type DPHY_ATEST_SEL_LANE3;\
239	type DPHY_PRBS_EN;\
240	type DPHY_PRBS_SEL;\
241	type DPHY_SYM1;\
242	type DPHY_SYM2;\
243	type DPHY_SYM3;\
244	type DPHY_SYM4;\
245	type DPHY_SYM5;\
246	type DPHY_SYM6;\
247	type DPHY_SYM7;\
248	type DPHY_SYM8;\
249	type DPHY_SCRAMBLER_BS_COUNT;\
250	type DPHY_SCRAMBLER_ADVANCE;\
251	type DPHY_RX_FAST_TRAINING_CAPABLE;\
252	type DPHY_LOAD_BS_COUNT;\
253	type DPHY_TRAINING_PATTERN_SEL;\
254	type DP_DPHY_HBR2_PATTERN_CONTROL;\
255	type DP_LINK_TRAINING_COMPLETE;\
256	type DP_IDLE_BS_INTERVAL;\
257	type DP_VBID_DISABLE;\
258	type DP_VID_ENHANCED_FRAME_MODE;\
259	type DP_VID_STREAM_ENABLE;\
260	type DP_UDI_LANES;\
261	type DP_SEC_GSP0_LINE_NUM;\
262	type DP_SEC_GSP0_PRIORITY;\
263	type DP_MSE_SAT_SRC0;\
264	type DP_MSE_SAT_SRC1;\
265	type DP_MSE_SAT_SRC2;\
266	type DP_MSE_SAT_SRC3;\
267	type DP_MSE_SAT_SLOT_COUNT0;\
268	type DP_MSE_SAT_SLOT_COUNT1;\
269	type DP_MSE_SAT_SLOT_COUNT2;\
270	type DP_MSE_SAT_SLOT_COUNT3;\
271	type DP_MSE_SAT_UPDATE;\
272	type DP_MSE_16_MTP_KEEPOUT;\
273	type DC_HPD_EN;\
274	type TMDS_CTL0;\
275	type AUX_HPD_SEL;\
276	type AUX_LS_READ_EN;\
277	type AUX_RX_RECEIVE_WINDOW
278
279
280#define DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type) \
281		type RDPCS_PHY_DP_TX0_DATA_EN;\
282		type RDPCS_PHY_DP_TX1_DATA_EN;\
283		type RDPCS_PHY_DP_TX2_DATA_EN;\
284		type RDPCS_PHY_DP_TX3_DATA_EN;\
285		type RDPCS_PHY_DP_TX0_PSTATE;\
286		type RDPCS_PHY_DP_TX1_PSTATE;\
287		type RDPCS_PHY_DP_TX2_PSTATE;\
288		type RDPCS_PHY_DP_TX3_PSTATE;\
289		type RDPCS_PHY_DP_TX0_MPLL_EN;\
290		type RDPCS_PHY_DP_TX1_MPLL_EN;\
291		type RDPCS_PHY_DP_TX2_MPLL_EN;\
292		type RDPCS_PHY_DP_TX3_MPLL_EN;\
293		type RDPCS_TX_FIFO_LANE0_EN;\
294		type RDPCS_TX_FIFO_LANE1_EN;\
295		type RDPCS_TX_FIFO_LANE2_EN;\
296		type RDPCS_TX_FIFO_LANE3_EN;\
297		type RDPCS_EXT_REFCLK_EN;\
298		type RDPCS_TX_FIFO_EN;\
299		type UNIPHY_LINK_ENABLE;\
300		type UNIPHY_CHANNEL0_XBAR_SOURCE;\
301		type UNIPHY_CHANNEL1_XBAR_SOURCE;\
302		type UNIPHY_CHANNEL2_XBAR_SOURCE;\
303		type UNIPHY_CHANNEL3_XBAR_SOURCE;\
304		type UNIPHY_CHANNEL0_INVERT;\
305		type UNIPHY_CHANNEL1_INVERT;\
306		type UNIPHY_CHANNEL2_INVERT;\
307		type UNIPHY_CHANNEL3_INVERT;\
308		type UNIPHY_LINK_ENABLE_HPD_MASK;\
309		type UNIPHY_LANE_STAGGER_DELAY;\
310		type RDPCS_SRAMCLK_BYPASS;\
311		type RDPCS_SRAMCLK_EN;\
312		type RDPCS_SRAMCLK_CLOCK_ON;\
313		type DPCS_TX_FIFO_EN;\
314		type RDPCS_PHY_DP_TX0_DISABLE;\
315		type RDPCS_PHY_DP_TX1_DISABLE;\
316		type RDPCS_PHY_DP_TX2_DISABLE;\
317		type RDPCS_PHY_DP_TX3_DISABLE;\
318		type RDPCS_PHY_DP_TX0_CLK_RDY;\
319		type RDPCS_PHY_DP_TX1_CLK_RDY;\
320		type RDPCS_PHY_DP_TX2_CLK_RDY;\
321		type RDPCS_PHY_DP_TX3_CLK_RDY;\
322		type RDPCS_PHY_DP_TX0_REQ;\
323		type RDPCS_PHY_DP_TX1_REQ;\
324		type RDPCS_PHY_DP_TX2_REQ;\
325		type RDPCS_PHY_DP_TX3_REQ;\
326		type RDPCS_PHY_DP_TX0_ACK;\
327		type RDPCS_PHY_DP_TX1_ACK;\
328		type RDPCS_PHY_DP_TX2_ACK;\
329		type RDPCS_PHY_DP_TX3_ACK;\
330		type RDPCS_PHY_DP_TX0_RESET;\
331		type RDPCS_PHY_DP_TX1_RESET;\
332		type RDPCS_PHY_DP_TX2_RESET;\
333		type RDPCS_PHY_DP_TX3_RESET;\
334		type RDPCS_PHY_RESET;\
335		type RDPCS_PHY_CR_MUX_SEL;\
336		type RDPCS_PHY_REF_RANGE;\
337		type RDPCS_PHY_DP4_POR;\
338		type RDPCS_SRAM_BYPASS;\
339		type RDPCS_SRAM_EXT_LD_DONE;\
340		type RDPCS_PHY_DP_TX0_TERM_CTRL;\
341		type RDPCS_PHY_DP_TX1_TERM_CTRL;\
342		type RDPCS_PHY_DP_TX2_TERM_CTRL;\
343		type RDPCS_PHY_DP_TX3_TERM_CTRL;\
344		type RDPCS_PHY_DP_REF_CLK_MPLLB_DIV;\
345		type RDPCS_PHY_DP_MPLLB_MULTIPLIER;\
346		type RDPCS_PHY_DP_MPLLB_SSC_EN;\
347		type RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN;\
348		type RDPCS_PHY_DP_MPLLB_TX_CLK_DIV;\
349		type RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN;\
350		type RDPCS_PHY_DP_MPLLB_FRACN_EN;\
351		type RDPCS_PHY_DP_MPLLB_PMIX_EN;\
352		type RDPCS_PHY_DP_MPLLB_FRACN_QUOT;\
353		type RDPCS_PHY_DP_MPLLB_FRACN_DEN;\
354		type RDPCS_PHY_DP_MPLLB_FRACN_REM;\
355		type RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD;\
356		type RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE;\
357		type RDPCS_PHY_DP_MPLLB_SSC_PEAK;\
358		type RDPCS_PHY_DP_MPLLB_DIV_CLK_EN;\
359		type RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER;\
360		type RDPCS_PHY_TX_VBOOST_LVL;\
361		type RDPCS_PHY_HDMIMODE_ENABLE;\
362		type RDPCS_PHY_DP_REF_CLK_EN;\
363		type RDPCS_PLL_UPDATE_DATA;\
364		type RDPCS_SRAM_INIT_DONE;\
365		type RDPCS_TX_CR_ADDR;\
366		type RDPCS_TX_CR_DATA;\
367		type RDPCS_PHY_HDMI_MPLLB_HDMI_DIV;\
368		type RDPCS_PHY_DP_MPLLB_STATE;\
369		type RDPCS_PHY_DP_TX0_WIDTH;\
370		type RDPCS_PHY_DP_TX0_RATE;\
371		type RDPCS_PHY_DP_TX1_WIDTH;\
372		type RDPCS_PHY_DP_TX1_RATE;\
373		type RDPCS_PHY_DP_TX2_WIDTH;\
374		type RDPCS_PHY_DP_TX2_RATE;\
375		type RDPCS_PHY_DP_TX3_WIDTH;\
376		type RDPCS_PHY_DP_TX3_RATE;\
377		type DPCS_SYMCLK_CLOCK_ON;\
378		type DPCS_SYMCLK_GATE_DIS;\
379		type DPCS_SYMCLK_EN;\
380		type RDPCS_SYMCLK_DIV2_CLOCK_ON;\
381		type RDPCS_SYMCLK_DIV2_GATE_DIS;\
382		type RDPCS_SYMCLK_DIV2_EN;\
383		type DPCS_TX_DATA_SWAP;\
384		type DPCS_TX_DATA_ORDER_INVERT;\
385		type DPCS_TX_FIFO_RD_START_DELAY;\
386		type RDPCS_TX_FIFO_RD_START_DELAY;\
387		type RDPCS_REG_FIFO_ERROR_MASK;\
388		type RDPCS_TX_FIFO_ERROR_MASK;\
389		type RDPCS_DPALT_DISABLE_TOGGLE_MASK;\
390		type RDPCS_DPALT_4LANE_TOGGLE_MASK;\
391		type RDPCS_PHY_DPALT_DP4;\
392		type RDPCS_PHY_DPALT_DISABLE;\
393		type RDPCS_PHY_DPALT_DISABLE_ACK;\
394		type RDPCS_PHY_DP_MPLLB_V2I;\
395		type RDPCS_PHY_DP_MPLLB_FREQ_VCO;\
396		type RDPCS_PHY_DP_MPLLB_CP_INT_GS;\
397		type RDPCS_PHY_RX_VREF_CTRL;\
398		type RDPCS_PHY_DP_MPLLB_CP_INT;\
399		type RDPCS_PHY_DP_MPLLB_CP_PROP;\
400		type RDPCS_PHY_RX_REF_LD_VAL;\
401		type RDPCS_PHY_RX_VCO_LD_VAL;\
402		type DPCSTX_DEBUG_CONFIG; \
403		type RDPCSTX_DEBUG_CONFIG; \
404		type RDPCS_PHY_DP_TX0_EQ_MAIN;\
405		type RDPCS_PHY_DP_TX0_EQ_PRE;\
406		type RDPCS_PHY_DP_TX0_EQ_POST;\
407		type RDPCS_PHY_DP_TX1_EQ_MAIN;\
408		type RDPCS_PHY_DP_TX1_EQ_PRE;\
409		type RDPCS_PHY_DP_TX1_EQ_POST;\
410		type RDPCS_PHY_DP_TX2_EQ_MAIN;\
411		type RDPCS_PHY_DP_MPLLB_CP_PROP_GS;\
412		type RDPCS_PHY_DP_TX2_EQ_PRE;\
413		type RDPCS_PHY_DP_TX2_EQ_POST;\
414		type RDPCS_PHY_DP_TX3_EQ_MAIN;\
415		type RDPCS_PHY_DCO_RANGE;\
416		type RDPCS_PHY_DCO_FINETUNE;\
417		type RDPCS_PHY_DP_TX3_EQ_PRE;\
418		type RDPCS_PHY_DP_TX3_EQ_POST;\
419		type RDPCS_PHY_SUP_PRE_HP;\
420		type RDPCS_PHY_DP_TX0_VREGDRV_BYP;\
421		type RDPCS_PHY_DP_TX1_VREGDRV_BYP;\
422		type RDPCS_PHY_DP_TX2_VREGDRV_BYP;\
423		type RDPCS_PHY_DP_TX3_VREGDRV_BYP;\
424		type RDPCS_DMCU_DPALT_DIS_BLOCK_REG;\
425		type UNIPHYA_SOFT_RESET;\
426		type UNIPHYB_SOFT_RESET;\
427		type UNIPHYC_SOFT_RESET;\
428		type UNIPHYD_SOFT_RESET;\
429		type UNIPHYE_SOFT_RESET;\
430		type UNIPHYF_SOFT_RESET
431
432#define DCN20_LINK_ENCODER_REG_FIELD_LIST(type) \
433	type DIG_LANE0EN;\
434	type DIG_LANE1EN;\
435	type DIG_LANE2EN;\
436	type DIG_LANE3EN;\
437	type DIG_CLK_EN;\
438	type SYMCLKA_CLOCK_ENABLE;\
439	type DPHY_FEC_EN;\
440	type DPHY_FEC_READY_SHADOW;\
441	type DPHY_FEC_ACTIVE_STATUS;\
442	DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type);\
443	type VCO_LD_VAL_OVRD;\
444	type VCO_LD_VAL_OVRD_EN;\
445	type REF_LD_VAL_OVRD;\
446	type REF_LD_VAL_OVRD_EN;\
447	type AUX_RX_START_WINDOW; \
448	type AUX_RX_HALF_SYM_DETECT_LEN; \
449	type AUX_RX_TRANSITION_FILTER_EN; \
450	type AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; \
451	type AUX_RX_ALLOW_BELOW_THRESHOLD_START; \
452	type AUX_RX_ALLOW_BELOW_THRESHOLD_STOP; \
453	type AUX_RX_PHASE_DETECT_LEN; \
454	type AUX_RX_DETECTION_THRESHOLD; \
455	type AUX_TX_PRECHARGE_LEN; \
456	type AUX_TX_PRECHARGE_SYMBOLS; \
457	type AUX_MODE_DET_CHECK_DELAY;\
458	type DPCS_DBG_CBUS_DIS;\
459	type AUX_RX_PRECHARGE_SKIP;\
460	type AUX_RX_TIMEOUT_LEN;\
461	type AUX_RX_TIMEOUT_LEN_MUL
462
463#define DCN30_LINK_ENCODER_REG_FIELD_LIST(type) \
464	type TMDS_SYNC_DCBAL_EN;\
465	type PHY_HPO_DIG_SRC_SEL;\
466	type PHY_HPO_ENC_SRC_SEL;\
467	type DPCS_TX_HDMI_FRL_MODE;\
468	type DPCS_TX_DATA_SWAP_10_BIT;\
469	type DPCS_TX_DATA_ORDER_INVERT_18_BIT;\
470	type RDPCS_TX_CLK_EN
471
472#define DCN31_LINK_ENCODER_REG_FIELD_LIST(type) \
473	type ENC_TYPE_SEL;\
474	type HPO_DP_ENC_SEL;\
475	type HPO_HDMI_ENC_SEL
476
477#define DCN35_LINK_ENCODER_REG_FIELD_LIST(type) \
478	type DIG_BE_ENABLE;\
479	type DIG_RB_SWITCH_EN;\
480	type DIG_BE_MODE;\
481	type DIG_BE_CLK_EN;\
482	type DIG_BE_SOFT_RESET;\
483	type HDCP_SOFT_RESET;\
484	type DIG_BE_SYMCLK_G_CLOCK_ON;\
485	type DIG_BE_SYMCLK_G_HDCP_CLOCK_ON;\
486	type DIG_BE_SYMCLK_G_TMDS_CLOCK_ON;\
487	type DISPCLK_R_GATE_DIS;\
488	type DISPCLK_G_GATE_DIS;\
489	type REFCLK_R_GATE_DIS;\
490	type REFCLK_G_GATE_DIS;\
491	type SOCCLK_G_GATE_DIS;\
492	type SYMCLK_FE_R_GATE_DIS;\
493	type SYMCLK_FE_G_GATE_DIS;\
494	type SYMCLK_R_GATE_DIS;\
495	type SYMCLK_G_GATE_DIS;\
496	type DIO_FGCG_REP_DIS;\
497	type DISPCLK_G_HDCP_GATE_DIS;\
498	type SYMCLKA_G_HDCP_GATE_DIS;\
499	type SYMCLKB_G_HDCP_GATE_DIS;\
500	type SYMCLKC_G_HDCP_GATE_DIS;\
501	type SYMCLKD_G_HDCP_GATE_DIS;\
502	type SYMCLKE_G_HDCP_GATE_DIS;\
503	type SYMCLKF_G_HDCP_GATE_DIS;\
504	type SYMCLKG_G_HDCP_GATE_DIS
505
506struct dcn10_link_enc_shift {
507	DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
508	DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
509	DCN30_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
510	DCN31_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
511	DCN35_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
512};
513
514struct dcn10_link_enc_mask {
515	DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
516	DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
517	DCN30_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
518	DCN31_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
519	DCN35_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
520};
521
522struct dcn10_link_encoder {
523	struct link_encoder base;
524	const struct dcn10_link_enc_registers *link_regs;
525	const struct dcn10_link_enc_aux_registers *aux_regs;
526	const struct dcn10_link_enc_hpd_registers *hpd_regs;
527	const struct dcn10_link_enc_shift *link_shift;
528	const struct dcn10_link_enc_mask *link_mask;
529};
530
531
532void dcn10_link_encoder_construct(
533	struct dcn10_link_encoder *enc10,
534	const struct encoder_init_data *init_data,
535	const struct encoder_feature_support *enc_features,
536	const struct dcn10_link_enc_registers *link_regs,
537	const struct dcn10_link_enc_aux_registers *aux_regs,
538	const struct dcn10_link_enc_hpd_registers *hpd_regs,
539	const struct dcn10_link_enc_shift *link_shift,
540	const struct dcn10_link_enc_mask *link_mask);
541
542bool dcn10_link_encoder_validate_dvi_output(
543	const struct dcn10_link_encoder *enc10,
544	enum signal_type connector_signal,
545	enum signal_type signal,
546	const struct dc_crtc_timing *crtc_timing);
547
548bool dcn10_link_encoder_validate_rgb_output(
549	const struct dcn10_link_encoder *enc10,
550	const struct dc_crtc_timing *crtc_timing);
551
552bool dcn10_link_encoder_validate_dp_output(
553	const struct dcn10_link_encoder *enc10,
554	const struct dc_crtc_timing *crtc_timing);
555
556bool dcn10_link_encoder_validate_wireless_output(
557	const struct dcn10_link_encoder *enc10,
558	const struct dc_crtc_timing *crtc_timing);
559
560bool dcn10_link_encoder_validate_output_with_stream(
561	struct link_encoder *enc,
562	const struct dc_stream_state *stream);
563
564/****************** HW programming ************************/
565
566/* initialize HW */  /* why do we initialze aux in here? */
567void dcn10_link_encoder_hw_init(struct link_encoder *enc);
568
569void dcn10_link_encoder_destroy(struct link_encoder **enc);
570
571/* program DIG_MODE in DIG_BE */
572/* TODO can this be combined with enable_output? */
573void dcn10_link_encoder_setup(
574	struct link_encoder *enc,
575	enum signal_type signal);
576
577void enc1_configure_encoder(
578	struct dcn10_link_encoder *enc10,
579	const struct dc_link_settings *link_settings);
580
581/* enables TMDS PHY output */
582/* TODO: still need depth or just pass in adjusted pixel clock? */
583void dcn10_link_encoder_enable_tmds_output(
584	struct link_encoder *enc,
585	enum clock_source_id clock_source,
586	enum dc_color_depth color_depth,
587	enum signal_type signal,
588	uint32_t pixel_clock);
589
590void dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa(
591	struct link_encoder *enc,
592	enum clock_source_id clock_source,
593	enum dc_color_depth color_depth,
594	enum signal_type signal,
595	uint32_t pixel_clock);
596
597/* enables DP PHY output */
598void dcn10_link_encoder_enable_dp_output(
599	struct link_encoder *enc,
600	const struct dc_link_settings *link_settings,
601	enum clock_source_id clock_source);
602
603/* enables DP PHY output in MST mode */
604void dcn10_link_encoder_enable_dp_mst_output(
605	struct link_encoder *enc,
606	const struct dc_link_settings *link_settings,
607	enum clock_source_id clock_source);
608
609/* disable PHY output */
610void dcn10_link_encoder_disable_output(
611	struct link_encoder *enc,
612	enum signal_type signal);
613
614/* set DP lane settings */
615void dcn10_link_encoder_dp_set_lane_settings(
616	struct link_encoder *enc,
617	const struct dc_link_settings *link_settings,
618	const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
619
620void dcn10_link_encoder_dp_set_phy_pattern(
621	struct link_encoder *enc,
622	const struct encoder_set_dp_phy_pattern_param *param);
623
624/* programs DP MST VC payload allocation */
625void dcn10_link_encoder_update_mst_stream_allocation_table(
626	struct link_encoder *enc,
627	const struct link_mst_stream_allocation_table *table);
628
629void dcn10_link_encoder_connect_dig_be_to_fe(
630	struct link_encoder *enc,
631	enum engine_id engine,
632	bool connect);
633
634void dcn10_link_encoder_set_dp_phy_pattern_training_pattern(
635	struct link_encoder *enc,
636	uint32_t index);
637
638void dcn10_link_encoder_enable_hpd(struct link_encoder *enc);
639
640void dcn10_link_encoder_disable_hpd(struct link_encoder *enc);
641
642void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
643			bool exit_link_training_required);
644
645void dcn10_psr_program_secondary_packet(struct link_encoder *enc,
646			unsigned int sdp_transmit_line_num_deadline);
647
648bool dcn10_is_dig_enabled(struct link_encoder *enc);
649
650unsigned int dcn10_get_dig_frontend(struct link_encoder *enc);
651
652void dcn10_aux_initialize(struct dcn10_link_encoder *enc10);
653
654enum signal_type dcn10_get_dig_mode(
655	struct link_encoder *enc);
656
657void dcn10_link_encoder_get_max_link_cap(struct link_encoder *enc,
658	struct dc_link_settings *link_settings);
659#endif /* __DC_LINK_ENCODER__DCN10_H__ */