dcn31_afmt.h

  1/*
  2 * Copyright 2019 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#ifndef __DAL_DCN31_AFMT_H__
 27#define __DAL_DCN31_AFMT_H__
 28
 29
 30#define DCN31_AFMT_FROM_AFMT(afmt)\
 31	container_of(afmt, struct dcn31_afmt, base)
 32
 33#define AFMT_DCN31_REG_LIST(id) \
 34	SRI(AFMT_INFOFRAME_CONTROL0, AFMT, id), \
 35	SRI(AFMT_VBI_PACKET_CONTROL, AFMT, id), \
 36	SRI(AFMT_AUDIO_PACKET_CONTROL, AFMT, id), \
 37	SRI(AFMT_AUDIO_PACKET_CONTROL2, AFMT, id), \
 38	SRI(AFMT_AUDIO_SRC_CONTROL, AFMT, id), \
 39	SRI(AFMT_60958_0, AFMT, id), \
 40	SRI(AFMT_60958_1, AFMT, id), \
 41	SRI(AFMT_60958_2, AFMT, id), \
 42	SRI(AFMT_MEM_PWR, AFMT, id)
 43
 44struct dcn31_afmt_registers {
 45	uint32_t AFMT_INFOFRAME_CONTROL0;
 46	uint32_t AFMT_VBI_PACKET_CONTROL;
 47	uint32_t AFMT_AUDIO_PACKET_CONTROL;
 48	uint32_t AFMT_AUDIO_PACKET_CONTROL2;
 49	uint32_t AFMT_AUDIO_SRC_CONTROL;
 50	uint32_t AFMT_60958_0;
 51	uint32_t AFMT_60958_1;
 52	uint32_t AFMT_60958_2;
 53	uint32_t AFMT_MEM_PWR;
 54};
 55
 56#define DCN31_AFMT_MASK_SH_LIST(mask_sh)\
 57	SE_SF(AFMT0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
 58	SE_SF(AFMT0_AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
 59	SE_SF(AFMT0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\
 60	SE_SF(AFMT0_AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\
 61	SE_SF(AFMT0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\
 62	SE_SF(AFMT0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\
 63	SE_SF(AFMT0_AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\
 64	SE_SF(AFMT0_AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\
 65	SE_SF(AFMT0_AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\
 66	SE_SF(AFMT0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\
 67	SE_SF(AFMT0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\
 68	SE_SF(AFMT0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\
 69	SE_SF(AFMT0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\
 70	SE_SF(AFMT0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\
 71	SE_SF(AFMT0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\
 72	SE_SF(AFMT0_AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\
 73	SE_SF(AFMT0_AFMT_MEM_PWR, AFMT_MEM_PWR_FORCE, mask_sh),\
 74	SE_SF(AFMT0_AFMT_MEM_PWR, AFMT_MEM_PWR_DIS, mask_sh),\
 75	SE_SF(AFMT0_AFMT_MEM_PWR, AFMT_MEM_PWR_STATE, mask_sh)
 76
 77#define AFMT_DCN31_REG_FIELD_LIST(type) \
 78		type AFMT_AUDIO_INFO_UPDATE;\
 79		type AFMT_AUDIO_SRC_SELECT;\
 80		type AFMT_AUDIO_CHANNEL_ENABLE;\
 81		type AFMT_60958_CS_UPDATE;\
 82		type AFMT_AUDIO_LAYOUT_OVRD;\
 83		type AFMT_60958_OSF_OVRD;\
 84		type AFMT_60958_CS_CHANNEL_NUMBER_L;\
 85		type AFMT_60958_CS_CLOCK_ACCURACY;\
 86		type AFMT_60958_CS_CHANNEL_NUMBER_R;\
 87		type AFMT_60958_CS_CHANNEL_NUMBER_2;\
 88		type AFMT_60958_CS_CHANNEL_NUMBER_3;\
 89		type AFMT_60958_CS_CHANNEL_NUMBER_4;\
 90		type AFMT_60958_CS_CHANNEL_NUMBER_5;\
 91		type AFMT_60958_CS_CHANNEL_NUMBER_6;\
 92		type AFMT_60958_CS_CHANNEL_NUMBER_7;\
 93		type AFMT_AUDIO_SAMPLE_SEND;\
 94		type AFMT_MEM_PWR_FORCE;\
 95		type AFMT_MEM_PWR_DIS;\
 96		type AFMT_MEM_PWR_STATE
 97
 98struct dcn31_afmt_shift {
 99	AFMT_DCN31_REG_FIELD_LIST(uint8_t);
100};
101
102struct dcn31_afmt_mask {
103	AFMT_DCN31_REG_FIELD_LIST(uint32_t);
104};
105
106struct dcn31_afmt {
107	struct afmt base;
108	const struct dcn31_afmt_registers *regs;
109	const struct dcn31_afmt_shift *afmt_shift;
110	const struct dcn31_afmt_mask *afmt_mask;
111};
112
113void afmt31_poweron(
114		struct afmt *afmt);
115
116void afmt31_powerdown(
117		struct afmt *afmt);
118
119void afmt31_construct(struct dcn31_afmt *afmt31,
120	struct dc_context *ctx,
121	uint32_t inst,
122	const struct dcn31_afmt_registers *afmt_regs,
123	const struct dcn31_afmt_shift *afmt_shift,
124	const struct dcn31_afmt_mask *afmt_mask);
125
126#endif